EE241 - Spring 2005 Advanced Digital Integrated Circuits Lectures 4 and 5: Delay Modeling ISSCC 2005 Keynotes (Monday Morning) Nanoelectronics for the Ubiquitous Information Society, Daeje Chin, Minister of Information and Communications, Korea Ambient Intelligence: Broad Dreams and Nanoscale Realities, Hugo De Man, IMEC, Katholieke Universiteit Leuven, Belgium Innovation and Integration in the Nanoelectronics Era, Sunlin Chou, Intel, Hillsboro, OR Interesting Short Courses (on Su) Memory forum When processors hit the power wall 3d Integration 2 1
Interesting Sessions Mo Non-Volatile Memories Multimedia Processing Tu High-speed links and clock generators Microprocessors and Signal processing Low-Power wireless and advanced integration Clock distribution and power control High-speed interconnects and building blocks We Processor building blocks PLL, DLL and VCO s DRAM SRAM Clocking and I/O 3 Some other stuff Panels: Mo: Towards the Nanoscale transistor Tu: SRAM Design in the Nanoscale Era Th Circuit Design Forum Robust Design for Nanoscale circuits 4 2
Projects Projects info Target benchmark: ultra low-power 8051 microcontroller (and its components) Some interesting projects: Ultra low-power clock dividers/multipliers Sub-threshold design versus low-threshold design Low-current voltage converters/multipliers Design techniques for self-calibration Energy recovery and reversible computing The return of current-driven logic Error-resilient circuits and architectures Small-granularity self-timing / asynchronous 5 Device Models 3
K(V GS V THZ ) Model Drain current vs. gate-source voltage 8.0E-04 6.0E-04 I DS [A] 4.0E-04 2.0E-04 0.0E+00 0 0.2 0.4 0.6 0.8 1 1.2 V GS [V] V THZ 7 Transistor Leakage -3-4 log I DS [log A] -5-6 -7 Subthreshold slope -8-9 0 0.2 0.4 0.6 0.8 1 1.2 V GS [V] Leakage current is exponential with V GS V DS = 1.2V 8 4
Transistor Leakage 9 Transistor Leakage 8 6 IDS [na] 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 V DS [V] Two effects: diffusion current (like a bipolar transistor) exponential increase with V DS (DIBL) 10 5
Subthreshold Current Subthreshold behavior can be modeled physically 2 Vg VTh Vds W kt mkt q kt q Ids = µ e 1 e L q Or: Ids V gs W = I0 10 W0 ( ) V Th +γv ds S [Taur, Ning] 11 Leakage Components Courtesy of IEEE Press, New York. 2000 12 6
Leakage Components 1. pn junction reverse bias current 2. Weak inversion 3. Drain-induced barrier lowering (DIBL) 4. Gate-induced drain leakage (GIDL) 5. Punchthrough 6. Narrow width effect 7. Gate oxide tunneling 8. Hot carrier injection 13 Leakage Components Drain-induced barrier lowering (DIBL) Voltage at the drain lowers the source potential barrier Lowers V Th, no change on S Gate-induced drain leakage (GIDL) High field between gate and drain increases injection of carriers into substrate -> leakage (band-to-band leakage) 14 7
DIBL, GIDL, Weak Inversion Courtesy of IEEE Press, New York. 2000 15 Stack Effect NAND gate: Reduction: Courtesy of IEEE Press, New York. 2000 16 8
MOS Transistor as a Switch Discharging a capacitor Can solve: i = i i D D = D ( v ) DS dv C dt DS Prefer using equivalent resistances 17 MOS Transistor as a Switch Traversed path 18 9
MOS Transistor as a Switch Solving the integral: with appropriately calculated I dsat Averaging resistances: 19 Equivalent Resistance W/L=1, L=0.25µ 20 10
CMOS Performance t = ln 2 R Propagation delay: t phl = ( ln 2) ReqnCL plh ( ) eqp L C ln2 = 0.7 Short channel R eq f ( V DD ) for V DD >> V T Long channel R eq 1 V DD 21 MOS Capacitances Gate Capacitance Overlap Capacitance C GSO = C GDO = C ox x d W = C o W 22 11
MOS Capacitances Gate capacitance Non-linear channel capacitance Linear overlap, fringing capacitances Miller effect on overlap capacitance Non-linear drain diffusion capacitance PN junction Wiring capacitances Linear 23 Gate Capacitance 24 12
MOS Capacitances 0.25µm process 25 Gate and Drain Capacitances 2.0E-15 0.13um Cgs/um vs. Vgs 1.8E-15 1.6E-15 1.4E-15 1.2E-15 1.0E-15 8.0E-16 6.0E-16 NMOS VDS=VDD 4.0E-16 PMOS VDS=VDD NMOS VDS=0 2.0E-16 Vgs [V] PMOS VDS=0 0.0E+00 0.0 0.4 0.8 1.2 Cgs [F] Gate capacitance 2.00E-15 0.13um Cdb/um vs. Vds 1.80E-15 1.60E-15 NMOS VGS=0 PMOS VGS=0 1.40E-15 1.20E-15 1.00E-15 8.00E-16 6.00E-16 4.00E-16 2.00E-16 Vds (V) 0.00E+00 0.0 0.4 0.8 1.2 Cdb (F) Drain Capacitance 26 13
Gate Capacitances Gate capacitance is non-linear First order approximation with C ox WL (C ox L = 2fF/µm) This is an overestimation Need to find the actual equivalent capacitance by simulating it Since this is a linear approximation of non-linear function, it is valid only over the certain range Different capacitances for HL, LH transitions and power computation Drain capacitance non-linearity compensates But this changes with fanout 27 Gate Capacitance vs. V Th, V DD Nose, Sakurai, ISLPED 00 28 14
FO4 Inverter Delay In Shapes the input slope to FO4 t p FO4 load Suppresses Miller kickback 29 Calibrating Delays Step RC delay model is a good first-order approximation Accuracy can be improved by including: Slope effects Non-linear capacitive loading Signal arrival times Wire models 30 15
Input Slope Simulated vs. linear model 70 60 50 8 4 1 Driving gate fanout Delay [ps] 40 30 20 10 0 0 2 4 6 8 10 FanOut 31 Input slope We can model the delay as t p = 0.7*R ekv C When driving with non-step input, the rise/fall time is absorbed into R ekv R ekv is different than one extracted straight from I-V The output delay is linearly dependent on input rise/fall time t p = 0.7RC + ηt S η = 0.17 in this example (~1/6) The model is limited to a range of fanouts More accurate delay models propagate two quantities: delay and signal slope Both can be modeled either as linear or table lookups 32 16
Standard Cell Library Contains for each cell: Functional information: cell = a *b * c Timing information: function of input slew intrinsic delay output capacitance non-linear models used in tabular approach Physical footprint (area) Power characteristics Wire-load models - function of Block size Fan-out [from K. Keutzer] Library 33 Synopsys Delay Models Linear (CMOS2) delay model 34 17
Example Cell Timing 35 Delay Dependency on Edge Rate 36 18
Transition Time Linear: Piecewise linear: 37 Cell Characterization 38 19
Synopsys Nonlinear Delay Model Delay is a function of: 39 Synopsys Nonlinear Delay Model 40 20
Static Timing Analysis Combinational logic Combinational logic Combinational logic clk original circuit clk clk Combinational logic extracted block [from K. Keutzer] 41 Each Combinational Block Arrival time in green Interconnect delay in red Gate delay in blue 0 C W.10 1.20 0 1 A B.05.05.05 X 2 2 Y.20.20 2 Z.15 What s the right mathematical object to use to represent this physical object? f [from K. Keutzer] 42 21
Problem formulation - 1 Use a labeled directed graph G = <V,E> Vertices represent gates, primary inputs and primary outputs Edges represent wires Labels represent delays Now what do we do with this? 0 C W.10 1 0 1.20 0 0 A C B 1 A.05 B.05.1.05 1.2 1 X 0 2 2 W Y.05.20.20 X 2 2 Y Z 2.15.20 2.15 f f Z.20 [from K. Keutzer] 43 Problem formulation - Arrival Time Arrival time A(v) for a node v is time when signal arrives at node v A(X) A(Y) X Y d x z Z dy z A(Z) A( υ ) = max (A(u) + d u υ ) u FI( υ) where dυ u is delay from υ to u, FI(υ)= {X,Y}, and υ= {Z}. [from K. Keutzer] 44 22
Static Timing Analysis Computing critical (longest) path delay Longest path algorithm on DAG [Kirkpatrick, IBM Jo. R&D, 1966] Used in most ASIC designs today Limitations False paths Simultaneous arrival times 45 Signal Arrival Times NAND gate: 1 46 23
Signal Arrival Times NAND gate: 1 47 Simultaneous Arrival Times NAND gate: 48 24
Impact of Arrival Times Delay A Up to 25% B A arrives early B arrives early 0 t A - t B 49 Optimization for Performance Performance critical blocks Start with a synthesized design Easier to explore architectures Easy to verify Provides some level of performance optimization Understand the limits of synthesized designs 50 25
Optimization for Performance Options Technology choice CMOS, bipolar, BiCMOS, GaAs, Superconducting Logic level optimizations logic depth, network topology, fan-out, gate complexity Circuit optimizations logic style, transistor sizing Physical optimization implementation choice, layout strategy Do not ignore wiring!! 51 Logic Level Optimizations Logic Depth or Techniques: Restructuring, pipelining, retiming, technology mapping R R Well covered by today s logic and sequential synthesis 52 26
Logic Optimizations (2) Fanout Late arriving Tp = O(FO) also effects wiring capacitance Technique: Removal of common sub-expression Start from tree structure/output 53 Logic Optimizations (3) t p (nsec) 4.0 3.0 2.0 1.0 quadratic linear t phl 0.0 1 3 5 7 9 fan-in t p t plh Fanin T p = O(FI 2 )! Observation: only true if FI translates in series devices - otherwise linear e.g. NAND pull-down NOR pull-up AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4) 54 27
Logic Optimizations (4) t pnor t pnand tpinv t p (psec) F(Fan-in) Slope is a function of driving strength 1 2 3 4 5 6 7 Fan-out All the gates have the same drive current 55 Technology Mapping for Performance Alternative coverings Use low FI modules on critical path(s) Library composition? 56 28