Engine managemen IC for Small Engines Daa Shee Rev 1.0, 2012-10-01 Auomoive Power
Table of Conens Table of Conens 1 Overview....................................................................... 3 2 Block Diagram................................................................... 4 3 Pin Configuraion................................................................ 5 3.1 Pin Assignmen................................................................... 5 3.2 Pin Definiions and Funcions........................................................ 5 4 General Produc Characerisics.................................................... 7 4.1 Absolue Maximum Raings......................................................... 7 4.2 Funcional Range................................................................. 8 4.3 Thermal Resisance............................................................... 8 5 Volage Regulaor................................................................ 9 5.1 Volage Regulaor................................................................. 9 5.2 Power On Rese and Rese Oupu................................................... 9 5.3 Wachdog Operaion.............................................................. 10 6 Power Drivers.................................................................. 14 6.1 Low-Side Drivers................................................................ 14 6.2 Elecrical Characerisics.......................................................... 15 7 K-Line......................................................................... 18 7.1 K-Line......................................................................... 18 8 Applicaion Informaion.......................................................... 21 8.1 Furher Applicaion Informaion...................................................... 21 9 Package Oulines............................................................... 22 10 Revision Hisory................................................................ 23 Daa Shee 2 Rev 1.0, 2012-10-01
Engine managemen IC for Small Engines TLE8088EM 1 Overview Feaures Supply 5 V (±2%), 250mA Over-emperaure and Over-curren Proecion Wachdog and Rese Funcion K-Line Transceiver 1 low side driver for inducive loads wih maximum operaion curren of 2.6A including over-emperaure, over-curren proecion and open load/shor o GND in off diagnosis 1 low side driver for resisive loads wih maximum operaion curren of 3A including over-emperaure and over-curren proecion Small Package PG-SSOP-24 Exposed Pad Temperaure Range: -40 C o 150 C Green Produc (RoHS complian) AEC Qualified PG-SSOP-24 Descripion TLE8088EM is an engine managemen IC based on Infineon Smar Power Technology (SPT). I is proeced by embedded proecion funcions and inegraes a Power Supply, K-line and power sages o drive differen loads in an Engine Managemen Sysem. I is designed o provide a compac and cos opimized soluion for Engine Managemen and Powerrain Sysems. I is specially suiable for one cylinder moorcycle engine managemen sysem. Type Package Marking TLE8088EM PG-SSOP-24 TLE8088EM Daa Shee 3 Rev 1.0, 2012-10-01
Engine managemen IC TLE 8088 EM Block Diagram 2 Block Diagram Vs V5DD 5V volage regulaor NRO WDI Wachdog & Rese WDE RX TX K Line ransceiver KIO ST IN1 LS-Driver 1 OUT1 IN2 LS-Driver 2 OUT2 AGND GND Figure 1 Block Diagram Daa Shee 4 Rev 1.0, 2012-10-01
Engine managemen IC TLE 8088 EM Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen n.c. 1 1 24 24 n.c. GND 2 2 23 23 GND KIO 3 3 22 22 RX OUT1 4 4 21 21 TX OUT2 5 5 20 20 IN1 VS 6 6 19 19 IN2 AGND 7 7 18 18 ST WDE 8 8 17 17 WDI V5DD 9 9 16 16 NRO n.c. 10 10 15 15 n.c. n.c. 11 11 14 14 n.c. n.c. 12 12 13 13 n.c. PG-SSOP-24.vsd Figure 2 Pin Configuraion 3.2 Pin Definiions and Funcions Pin Symbol Funcion 1 n.c. No conneced 2 GND Power Ground 3 KIO K-Line bus connecion 4 OUT1 Oupu channel 1 5 OUT2 Oupu channel 2 6 VS Baery volage: 100nF ceramic capacior direcly conneced a he IC o ground 7 AGND Analog ground: should be conneced o he sysem logic ground 8 WDE Wachdog enable: acive high, inernal pull up 9 V5DD 5V supply oupu: conneced o exernal blocking capacior. 10 n.c. No conneced 11 n.c. No conneced 12 n.c. No conneced 13 n.c. No conneced 14 n.c. No conneced 15 n.c. No conneced 16 NRO Rese oupu: open drain, acive low 17 WDI Wachdog inpu: rigger inpu for wachdog pulses 18 ST Saus signal: oupu diagnosic signal 19 IN2 Conrol Inpu Channel 2: inernal pull down Daa Shee 5 Rev 1.0, 2012-10-01
Pin Configuraion Pin Symbol Funcion 20 IN1 Conrol Inpu Channel 1: inernal pull down 21 TX Logic level inpu for daa o be ransmied on he K-Line bus KIO 22 RX Logic oupu of daa received from he K-Line bus KIO. 23 GND Power Ground 24 n.c. No conneced Exposed pad should be conneced o GND and o he ground plane of he ECU Daa Shee 6 Rev 1.0, 2012-10-01
General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings Absolue Maximum Raings T j = -40 C o +150 C; All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. Volages 4.1.1 Coninuous Volage on pin Vs V S -0.3 40 V 4.1.2 Coninuous Volage on pin OUT1 V OUT1-0.3 30 V IN1=0V 4.1.3 Coninuous Volage on pin OUT2, KIO V OUT2, KIO -0.3 35 V IN2=0V TX=V5DD 4.1.4 IN1, IN2, V5DD, RxD, TxD, ST, NRO, V x -0.3 5.5 V 2) WDI, WDE Temperaures 4.1.5 Juncion Temperaure T j -40 150 C 4.1.6 Sorage Temperaure T sg -55 150 C ESD Suscepibiliy 4.1.7 ESD Resisiviy o GND, Vs, K-LINE, V ESD -4 4 kv HBM 3) OUT1,2 4.1.8 ESD Resisiviy o GND, oher pins V ESD -2 2 kv HBM 3) 4.1.9 Elecro Saic Discharge Volage Charged Device Model - CDM 4.1.10 Elecro Saic Discharge Volage Charged Device Model - CDM No subjec o producion es, specified by design 2) For oupus no shor circui is allowed 3) ESD suscepibiliy, HBM according o EIA/JESD 22-A114B (1.5KOhm, 100pF) 4) ESD suscepibiliy, Charged Device Model CDM EIA/JESD22-C101-C V ESD -500 500 V All Pins CDM 4) V ESD -750 750 V Pin 1, 12, 13, 24 (corner pins) CDM 4) Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. Daa Shee 7 Rev 1.0, 2012-10-01
Engine managemen IC TLE 8088 EM General Produc Characerisics 4.2 Funcional Range Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. 4.2.1 Supply Volage V S 6 18 V 4.2.2 Juncion Temperaure T j -40 150 C Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. 4.3 Thermal Resisance Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. 4.3.1 Juncion o Case R hjc 6.3 9 K/W Measured o exposed pad 4.3.2 Juncion o Ambien R hja 29 K/W 2) No subjec o producion es, specified by design. 2) Specified R hja value is according o Jedec JESD51-2,-5,-7 a naural convecion on FR4 2s2p board; The Produc (Chip+Package) was simulaed on a 76.2 x 114.3 x 1.5 mm board wih 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a hermal via array under he exposed pad conaced he firs inner copper layer.. Daa Shee 8 Rev 1.0, 2012-10-01
Volage Regulaor 5 Volage Regulaor 5.1 Volage Regulaor The TLE8088EM inegraes a volage regulaor for load currens up o 250mA. The volage applied o pin VS is regulaed a pin V5DD o 5.0 V wih a precision of ±2%. The sophisicaed design allows o achieve sable operaion even wih ceramic oupu capaciors down o 470nF. The volage regulaor feaures under-volage rese, power on rese and wachdog. I is proeced agains over-curren, shor circui and over emperaure condiions. The low-side swich funcion and he K-line ransceiver are independen of he rese and wachdog signals. VS Vref + I VS - V5DD I V5DD e.g. µc Figure 3 5V Supply 5.2 Power On Rese and Rese Oupu Rese oupu is an open drain oupu. When he level of V V5DD reaches he rese hreshold V RT, he signal a NRO remains low for he power-on rese delay ime T RD. The rese funcion and iming is illusraed in Figure 4. The rese reacion ime RR avoids wrong riggering caused by shor gliches on he V5DD-line. In case of V5DD power down (V V5DD < V RT for > RR ) a logic low signal is generaed a he pin NRO o rese an exernal micro conroller. The level of he rese hreshold for increasing V V5DD is for he hyseresis (V RH ) higher han he level for decreasing V V5DD. The rese and wachdog signals are for exernal use and do no affec he sae of he channels and K-line ransceiver. The correc funcionaliy of he devices is ensured by an independen volage monioring circuiry. Daa Shee 9 Rev 1.0, 2012-10-01
Volage Regulaor Vs V V5DD < RR V RT V NRO T RD RR RR T RD V NRO_H V NRO_L Figure 4 Rese Funcion and Timing Diagram 5.3 Wachdog Operaion Afer power on, he rese oupu signal a he NRO pin is kep LOW for he power-on rese delay ime T RD of yp. 15ms. Wih he LOW o HIGH ransiion of he signal a NRO he micro conroller rese is released. The TLE8088EM inegraes a wachdog funcion. If WDE is conneced o low, he wachdog funcion is disabled. If he WDE is conneced o 5V or lef open, he wachdog funcion is enabled. A pull up curren source is inegraed in he WDE pin. Afer he acivaion of he wachdog funcion, he iming of he signal on WDI from he micro-conroller mus correspond he WD-Period T WD,p specified in he elecrical characerisics. A Re-Trigger of he WD-Period is done wih a HIGH-o-LOW ransiion a he WDI-pin wihin he ime T WD,p. A HIGH o LOW ransiion of he wachdog rigger signal on pin WDI is aken as a rigger. To avoid wrong riggering due o parasiic gliches wo HIGH samples followed by wo LOW samples (sample period sam yp. 64μs ) are decoded as a valid rigger, see Figure 6. A rese is generaed (NRO goes LOW) for he ime T WR if here is no rigger pulse during he Wachdog Period as shown in Figure 5. Daa Shee 10 Rev 1.0, 2012-10-01
Volage Regulaor Vs V 5DD V RT VNRO T RD Normal operaion rr T WR Trigger Window sam WDI 1. Correc Trigger T WD,p No Trigger causing rese Figure 5 Wachdog Timing Diagram WDI Valid rigger WD period resar T WD,p ime-ou No rigger WD ime-ou No rigger WD ime-ou No rigger WD ime-ou sam Figure 6 Wachdog valid rigger Daa Shee 11 Rev 1.0, 2012-10-01
Volage Regulaor Elecrical Characerisics: Volage Regulaor V S = 13.5 V, T j = -40 C o +150 C, all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. Oupu V5DD 5.3.1 Oupu Volage V V5DD 4.90 5.00 5.10 V 0mA < I V5DD < 150mA 6V < V s < 18V 5.3.2 Oupu Volage V V5DD 4.90 5.00 5.10 V 0mA < I V5DD < 250mA 6V < V s < 18V 5.3.3 Oupu Curren Limiaion I V5DD 250 650 ma V V5DD = 0V, 6V < V s < 18V 5.3.4 Load Regulaion ΔV V5DD,Lo 20 mv 1 ma < I V5DD < 150mA 5.3.4a Load Regulaion ΔV V5DD,Lo 50 mv 1 ma < I V5DD < 250mA 5.3.5 Line Regulaion ΔV V5DD,Li 10 mv I V5DD = 1 ma; 10 V < V s < 18V 5.3.6 Power Supply Rejecion Raio PSRR 60 db f r = 100 Hz; V r = 0.5 Vpp 5.3.7 Oupu Capacior C Q 470 nf ESR(C Q ) 10 Ω 5.3.8 Low Drop Volage V V5DD 4.80 V I V5DD = 1mA V S =5V 5.3.9 4.40 V I V5DD = 150mA V S =5V; afer device ramp-up (V S >9V) 5.3.9a 4.15 V I V5DD = 250mA V S =5V; afer device ramp-up (V S >9V) Curren Consumpion 5.3.10 Quiescen Curren I q 4 ma I V5DD = 0A; CH1,CH2 off, K-Line off WDE 5.3.11 Low Level Inpu Volage V IN,L 1.00 V 5.3.12 High Level Inpu Volage V IN,H 2.00 V 5.3.13 Hyseresis WDE V IN,HYS 50 250 mv 5.3.14 Inpu Pull Up Curren I IN_PU_L -20-50 -100 µa V IN =0V I IN_PU_H -2.40 µa V IN =4.4V Wachdog Inpu WDI 5.3.15 Low Level Inpu Volage V IN,L 1.00 V 5.3.16 High Level Inpu Volage V IN,H 2.00 V 5.3.17 Inpu Volage Hyseresis V IN,HYS 50 250 mv Daa Shee 12 Rev 1.0, 2012-10-01
Volage Regulaor Elecrical Characerisics: Volage Regulaor (con d) V S = 13.5 V, T j = -40 C o +150 C, all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. 5.3.18 Inpu Pull Down Curren I IN_PD_H 20 50 100 µa V IN =5V I IN_PD_L 2.40 µa V IN =0.6V 5.3.19 Wachdog Sampling Time sam 40 64 130 µs 5.3.20 Wachdog Period T WD,p 50 60 70 ms 5.3.21 Wachdog Rese Time T WR 120 240 360 µs Rese Oupu NRO 5.3.22 Oupu Volage Rese Swiching V RT 4.00 4.25 4.50 V V V5DD decreasing Threshold 5.3.23 Rese Hyseresis V RH 10 150 mv 5.3.24 Low Level Oupu Volage V NRO,L 1.10 V I NRO =1mA 5.3.25 Leakage Curren I NRO,LK 1 µa V RT = 5V 5.3.26 Power-on Rese Delay Time T RD 10 15 20 ms 5.3.27 Rese Reacion Time RR 1 4 8 µs Over Temperaure Proecion 5.3.28 Over-emperaure T OT 150 200 C 5.3.29 Over-emperaure Hyseresis T OTH 20 C No subjec o producion es, specified by design. Daa Shee 13 Rev 1.0, 2012-10-01
Power Drivers 6 Power Drivers 6.1 Low-Side Drivers The power sages are buil by N-channel power MOSFET ransisors. The channels are universal muli channel swiches bu mosly suiable o be used in Engine Managemen Sysems. Wihin an Engine Managemen Sysem, he bes fi of he channels o he ypical loads is: Channel 1 for injecor, valves or similar sized solenoids wih a maximum operaion curren requiremen of 2.6A Channel 2 for malfuncion indicaion lamps or oher resisive loads wih a maximum curren requiremen of 3A V ba OUT I D L, R L V ba OUT I D R V DScl V DS V DS GND GND Channel 1 Channel 2 Figure 7 Low-side Swiches Channel 1 has open load deecion in off sae. If an open load condiion persiss for a ime longer han he filer ime d, an open load will be deeced and he ST pin se o low. On he rising edge of he IN1 signal he ST pin will be released afer he ime ST,clear, see Figure 9. In over-curren siuaion channel 1 will be swiched off and kep lached. Addiionally he ST signal will be se o low afer he seling ime ST,se,OC. On he falling edge of he IN1 signal he ST pin will be released afer he ime ST,clear, see Figure 10. Therefore channel 1 can be swiched on again by oggling he IN1 pin. During an over-emperaure even he ST signal is se o low and will urn back o high if he failure condiion is disappeared (see Table. Table 1 Truh Table for Diagnosics of CH1 Open Load Over Curren Over Temperaure ST Saus 0 0 0 1 Normal operaion 1 x x 0 Failure deeced x 1 x 0 Failure deeced and lached Channel 1 is swiched off x x 1 0 Failure deeced and channel 1 is swiched off Failure Siuaion ST 0 = Siuaion doesn exis 1 = Normal operaion 1 = Siuaion exiss 0 = Failure deeced X = 0 or 1 In over-curren siuaion he channel 2 will be swiched off, and afer yp. 4ms he channel will be swiched on again. Channel 2 is also over-emperaure proeced. In over-emperaure siuaion channel 2 will be swiched off and will resar if he juncion emperaure falls by hermal shudown hyseresis T OTH. Daa Shee 14 Rev 1.0, 2012-10-01
Power Drivers 6.2 Elecrical Characerisics Elecrical Characerisics V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. Oupu Channel Resisance 6.2.1 On Sae Resisance CH1 R DSon 0.60 0.70 Ω I Dnom =1.3A; T j =150 C 6.2.2 On Sae Resisance CH2 R DSon 1.10 1.20 Ω I Dnom =0.3A; T j =150 C Inpu Characerisics 6.2.3 Parallel Inpu Pin Low level IN1,IN2 6.2.4 Parallel Inpu Pin High level IN1,IN2 6.2.5 Parallel Inpu Pin Hyseresis IN1,IN2 6.2.6 Parallel Inpu Pin Inpu Pull Down Curren IN1, IN2 V IN,L 1.00 V V IN,H 2.00 V V IN,HYS 50 250 mv I IN_PD_H 20 50 100 µa V IN =5V I IN_PD_L 2.40 µa V IN =0.6V Clamping Volage 6.2.7 Oupu Clamping Volage CH1 V DScl 30 35 40 V I OUT1 =0.02A Leakage Currens 6.2.8 Oupu Leakage Curren in Off Mode, CH1 6.2.9 Oupu Leakage Curren in Off Mode, CH2 I Doff 3 µa V DS =13.5V; T j =150 C 2) I Doff 3 µa V DS =13.5V; T j =150 C Timing 6.2.10 Turn-on Delay Time CH1 don 0.25 1 µs V s = 13.5V, I DS1 = 1.3A, resisive 3) load 6.2.11 Turn-on Delay Time CH2 don 0.15 1.2 µs V s = 13.5V, I DS2 = 0.3A, resisive load 6.2.12 Turn-off Delay Time CH1 doff 0.65 1.5 µs V s = 13,5V, I DS1 = 1.3A, resisive load 6.2.13 Turn-off Delay Time CH2 doff 0.35 1.5 µs V s = 13.5V, I DS2 = 0.3A, resisive load 6.2.14 Turn-on Time CH1 son 0.45 1.2 µs V s = 13.5V, I DS1 = 1.3A, resisive load Daa Shee 15 Rev 1.0, 2012-10-01
Power Drivers Elecrical Characerisics (con d) V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. 6.2.15 Turn-on Time CH2 son 0.20 1 µs V s = 13.5V, I DS2 = 0.3A, resisive load 6.2.16 Turn-off Time CH1 soff 0.40 1.2 µs V s = 13.5V, I DS1 = 1.3A, resisive load 6.2.17 Turn-off Time CH2 soff 0.20 1 µs V s = 13.5V, I DS2 = 0.3A, resisive load Over Curren Proecion 6.2.18 Oupu Curren Swich Off I DS_OC 2.6 5 A 6V < V S < 18V Threshold CH1 6.2.19 Oupu Curren Swich off I DS_OC 3.0 6.5 A 6V < V S < 18V Threshold CH2 6.2.20 Off Time of CH2 in Curren Swich off 3 8 ms Off 6.2.21 Curren Swich off Filer Time CH1, CH2 CL_f 0.5 3 µs Open Load Diagnosis for CH 1 in OFF sae 6.2.22 Open Load Deecion Threshold V DSol 2.00 2.80 3.20 V Volage for CH 1 6.2.23 Oupu pull-down Diagnosis Curren I Dpd 50 100 150 μa V DS = 13.5 V 6.2.24 Open Load Diagnosis Delay Time d 100 200 µs Saus Signal 6.2.25 Low level oupu volage V OUT_L 0.4 V I NRO =100μA 6.2.26 High level oupu volage V OUT_H V 5DD V I NRO = 100μA 0.4 6.2.27 Saus seling ime afer Over ST,se,OC 20 µs Curren 6.2.28 Saus Clear Time ST,clear 20 µs Over Temperaure Proecion 6.2.29 Over emperaure T OT 150 200 C 6.2.30 Over emperaure hyseresis T OTH 20 C No subjec o producion es, specified by design. 2) in OFF mode open load diagnosis pull down curren acive 3) Definiion see Figure 8 Daa Shee 16 Rev 1.0, 2012-10-01
Power Drivers V INx 50% V OUTx V BATT 80% 20% don son doff soff Figure 8 Timing IN1 VDSol Open Load V DS Figure 9 ST Open Load Deecion d ST,clear IN1 IDS_OC Over Curren Swich-off I DS CL_f Figure 10 ST Over Curren Deecion ST,se,OC ST,clear Daa Shee 17 Rev 1.0, 2012-10-01
K-Line 7 K-Line 7.1 K-Line The K-Line module is a serial link bus inerface device designed o provide bi-direcional half-duplex communicaion inerfacing. I is designed o inerface beween he vehicles via he special ISO K-line and mees he ISO norm 9141 specificaion. The device's K line bus driver's oupu is proeced agains bus shors. K-Line module ransforms 5.0V micro-conroller logic signals o baery level logic signals and vice versa. The over curren limiaion limis he curren o a specified limi. In case of over-emperaure on OUT1 he low-side swich and he oupu sage KIO will be swiched off and can only be re-acivaed if he emperaure has decreased below he minimum hyseresis value.. VS RX V5DD KIO TX Driver & Proecion Figure 11 K-Line Daa Shee 18 Rev 1.0, 2012-10-01
K-Line Elecrical Characerisics: K-Line Table 2 Elecrical Characerisics: K-Line V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Pos. Parameer Symbol Limi Values Uni Condiions min. yp. max. Oupu RX 7.1.1 Low Level Oupu Volage V RX,L 0.4 V I RX =100μA 7.1.2 High Level Oupu Volage V RX,H V 5DD - 0.4 V I RX =-100μA Inpu TX 7.1.3 Inpu Pin Low level V TX,L 1.00 V 7.1.4 Inpu Pin High level V TX,H 3.20 V 7.1.5 Inpu Pin Hyseresis V TX,HYS 280 500 700 mv 7.1.6 Inpu Pin Pull Up Curren I IN_PU -70-150 µa VTX=0 KIO inpu / Oupu 7.1.7 Low Level Oupu Volage V KIO,L 1.4 V TX=low, R KIO =480Ω 7.1.8 Curren Limiaion I KIO(lim) 40 140 ma 7.1.9 Oupu Pull-Down curren I KIO,PD 5 15 µa TX=high KIO Inpu Comparaor 7.1.10 Inpu Low Volage V IN_L 0.4*V s V 7.1.11 Inpu High Volage V IN_H 0.6*V s V 7.1.12 Inpu Threshold Hyseresis V IN_Hys 0.02*V s 0.175* V s V Transfer characerisics KIO->RX and TX->KIO CRX=25pF; RKIO=540Ω; CKIO<=1.3nF; Vs=13.5V 7.1.13 Transmission Frequency KIO->RX f RKIO 500 khz C KIO =0pF 7.1.14 Transmission Frequency TX->KIO f TKIO 100 khz 7.1.15 Off Delay / Rise Time drr 0.05 0.5 µs C RX,load =1.6pF 2) KIO->RX 7.1.16 Off Delay / Rise ime drt 0.05 0.5 µs C KIO,load =1.6pF TX->KIO 7.1.17 On Delay / Fall ime dfr 0.05 0.5 µs C RX,load =1.6pF 2) KIO->RX 7.1.18 On Delay / Fall ime dft 0.05 0.5 µs C KIO,load =1.6pF 2) TX->KIO No subjec o producion es, specified by design. 2) For definiion see Figure 12 2) Daa Shee 19 Rev 1.0, 2012-10-01
K-Line. V TX 50% V KIO drt dft 70% 50% 30% V RX 70% 30% drr dfr Figure 12 Transfer characerisics Daa Shee 20 Rev 1.0, 2012-10-01
Engine managemen IC TLE 8088 EM Applicaion Informaion 8 Applicaion Informaion Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. V BAT ECU V BAT 100µF 510Ω 2.2nF 4.7nF LOAD inducive 4.7nF LOAD resisive o µc o Loads 470nF 100nF Close o IC pin 1 nc ( 2 3 4 5 6 7 8 9 10 11 24 nc ( GND GND KIO RX OUT2 TX OUT1 IN1 VS IN2 AGND ST WDE WDI V5DD NRO nc ( nc ( nc ( nc ( nc ( TLE 8088 nc ( 23 22 21 20 19 18 17 16 15 14 12 13 o µc ( Pins marked as no conneced (nc) are inernally no bonded. Relaed pads can be used for faciliaing he PCB rouing. Figure 13 Applicaion Diagram Noe: This is a very simplified example of an applicaion circui. The funcion mus be verified in he real applicaion. 8.1 Furher Applicaion Informaion For furher informaion you may conac hp://www.infineon.com/ Daa Shee 21 Rev 1.0, 2012-10-01
Package Oulines 9 Package Oulines 0.25 2) ±0.05 +0 0.1-0.1 Sand Off 0.65 (1.47) C 1.7 MAX. 0.2 M C A-B D 24x 0.08 C Seaing Plane 2x 0.1 CD 3.9 ±0.1 D 0.35 x 45 6 ±0.2 0.19 +0.06 0.64 ±0.25 0.2 8 MAX. M D A Index Marking 24 13 1 12 B 8.65 ±0.1 0.1 C A-B 2x Boom View 1 12 24 13 6.4 ±0.25 2.65 ±0.25 Figure 14 Does no include plasic or meal prorusion of 0.15 max. per side 2) Does no include dambar prorusion of 0.13 max. PG-SSOP-24 Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions, he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp://www.infineon.com/packages. Dimensions in mm Daa Shee 22 Rev 1.0, 2012-10-01
Revision Hisory 10 Revision Hisory Revision Dae Changes 1.0 2012-10-01 Daa Shee Release Daa Shee 23 Rev 1.0, 2012-10-01
Ediion 2012-10-01 Published by Infineon Technologies AG 81726 Munich, Germany 2012 Infineon Technologies AG All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.