ACPL-6L, ACPL-M6L, ACPL-W6L, ACPL-K6L Ultra-Low-Power MBd Digital CMOS Optocouplers Data Sheet Description The Avago ultra-low-power ACPL-x6xL digital optocouplers combine an AlGaAs light emitting diode (LED) and an integrated high gain photodetector. The optocoupler consumes extremely low power, at maximum. ma I DD current per channel across temperature. With a forward LED current as low as.6 ma, most microprocessors can directly drive the LED. An internal Faraday shield provides a guaranteed common-mode transient immunity specification of 2 kv/μs. Maximum AC and DC circuit isolation is achieved while maintaining TTL/CMOS compatibility. The optocouplers' CMOS outputs are slew-rate controlled and designed to allow the rise and fall time to be controlled over a wide load-capacitance range. The ACPL-x6xL series operates from both.v and V supply voltages with guaranteed AC and DC performance from C to + C. These low-power optocouplers are suitable for high speed logic interface applications. Functional Diagrams Anode Cathode ACPL-M6L 6 V DD Vo GND Anode 8 V DD Cathode Cathode2 Anode2 2 ACPL-6L/K6L SHIELD 7 6 Vo Vo 2 GND Features Ultra-low I DD current:. ma/channel maximum Low input current:.6 ma Built-in slew-rate controlled outputs 2 kv/μs minimum Common-Mode Rejection (CMR) at V CM = V High speed: MBd minimum Guaranteed AC and DC performance over wide temperature: C to + C Wide package selection: SO-, SO-8, stretched SO-6, and stretched SO-8 Safety approval UL 77 recognized 7V rms for minute for ACPL-6L/M6L and V rms for minute for ACPL-W6L/K6L CSA Approval IEC/EN/DIN EN 677-- approval for Reinforced Insulation RoHS-compliant Applications Communication interfaces: RS8, CANBus, and I 2 C Microprocessor system interfaces Digital isolation for A/D and D/A convertors Anode NC* 2 ACPL-W6L 6 V DD Vo TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H Cathode SHIELD GND A. μf bypass capacitor must be connected between pins V DD and GND. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments.
Ordering Information The ACPL-6L and ACPL-M6L are UL Recognized with an isolation voltage of 7V rms for minute per UL77. The ACPL-W6L and ACPL-K6L are UL Recognized with an isolation voltage of V rms for minute per UL77. All devices are RoHS-compliant. Part number Option RoHS-Compliant Package Surface Mount Tape and Reel UL77 Vrms / Minute rating IEC/EN/DIN EN 677-- Quantity ACPL-M6L -E SO- X per tube -6E X X per tube -E X X per reel -6E X X X per reel ACPL-6L -E SO-8 X per tube -6E X X per tube -E X X per reel -6E X X X per reel ACPL-W6L -E Stretched X X per tube -6E S6 X X X per tube -E X X X per reel -6E X X X X per reel ACPL-K6L -E Stretched X X 8 per tube -6E S8 X X X 8 per tube -E X X X per reel -6E X X X X per reel To form an ordering part number, choose a part number from the part number column and combine it with the desired option from the RoHS option column. Example: Part number ACPL-M6L-6E describes an optocoupler with a surface mount SO- package; delivered in Tape and Reel with parts-per-reel; with IEC/EN/DIN EN 677-- Safety Approval; and full RoHS compliance. Option data sheets are available. Contact your Avago sales representative or authorized distributor for information. 2
Package Outline Drawings ACPL-6L SO-8 Package LAND PATTERN RECOMMENDATION.9 (.7).6 (.2).97.27 (. ±.) 8 7 6 DEVICE PART NUMBER LEAD-FREE PIN NNNN Z YYWW EEE 2 TEST RATING CODE DATE CODE LOT ID.99 ±.2 (.26 ±.8).9 (.6) 7.9 (.29).6 ±.76 (.6 ±.).27 (.) BSC.27 (.) *.8 ±.27 (.2 ±.) 7 X.2 (.7).7 ±.27 (.2 ±.).2 (.6) ~ 7.228 ±.2 (.9 ±.) * Total package length (inclusive of mold flash).27 ±.2 (.2 ±.) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is. mm (6 mils) max. Lead coplanarity =. mm (. inches) max. Option number not marked..2 ±.2 (.8 ±.). (.2) MIN. ACPL-M6L SO- Package DEVICE PART NUMBER. ±. (.7 ±.) LEAD FREE PIN DOT NNNN Z YYWW EEE.6 ±.* (.2 ±.) TEST RATING CODE. ±. (.6 ±.2) 7. ±.2 (.276 ±.8) DATE CODE LOT ID LAND PATTERN RECOMMENDATION. (.).9 (.7).27 (.) 2. (.).6 (.2).8 (.7) 8.26 (.2) 2. ±. (.98 ±.).2 ±.2 (. ±.). ±.2 (.6 ±.).27 (.) BSC.7 (.28) MIN 7 MAX. Dimensions in millimeters (inches). Note: Foating Lead Protrusion is. mm (6 mils) max. * Maximum Mold flash on each side is. mm (.6). MAX. LEAD COPLANARITY =.2 (.)
ACPL-W6L Stretched SO-6 Package 6.8±.2 (.8±.).27 (.) BSG LAND PATTERN RECOMMENDATION 2.6 (.98) RoHS-COMPLIANCE INDICATOR.76 (.) NNNN YYWW EEE PART NUMBER DATE CODE Lot ID.9 (.7) 7 2.8±.27 (.±.). (.8) 7 6.87 (.268 +.27 +. -. ).9±.27 (.6±.).2±. (.8±.).8±.27 (.2±.) Dimensions in Millimeters (Inches). Lead coplanarity =. mm (. inches). ACPL-K6L Stretched SO-8 Package.7±.2 (.29±.).±.2 (.±.).8±.2 (.2±.) LAND PATTERN RECOMMENDATION 8 7 6 PART NUMBER RoHS-COMPLIANCE INDICATOR NNNN YYWW EEE DATE CODE Lot ID 6.87±.27 (.268±.).9 (.) 2.6 (.) 7 2. (.8) 7.9±.27 (.6±.).8±.27 (.2±.).2±. (.±.).27 (.) BSG.8±. (.±.) Dimensions in Millimeters (Inches). Lead coplanarity =. mm (. inches)..7±.2 (.29±.).±.2 (.±.)
Reflow Soldering Profile The recommended reflow soldering conditions are per JEDEC Standard J-STD-2 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-6L, ACPL-M6L, ACPL-W6L and ACPL-K6L are approved by the following organizations: IEC/EN/DIN EN 677-- (Option 6 only) UL Approval under UL 77 component recognition program up to V ISO = 7V rms for the ACPL-M6L/6L and V ISO = V rms for the ACPL-W6L/K6L File E6. CSA Approval under CSA Component Acceptance Notice #, File CA 882. Insulation and Safety Related Specifications ACPL-W6L ACPL-K6L Units Conditions L().9 8 mm Measured from input terminals to output terminals, shortest distance through air. Parameter Symbol ACPL-6L ACPL-M6L Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(2).8 8 mm Measured from input terminals to output terminals, shortest distance path along body..8.8.8 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI 7 7 7 V DIN IEC 2/VDE Part Isolation Group IIIa IIIa IIIa Material Group (DIN VDE, /89, Table )
IEC/EN/DIN EN 677-- Insulation Characteristics* (Option 6) Description Installation classification per DIN VDE /9, Table for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage 6 V rms for rated mains voltage V rms Symbol ACPL-6L/ ACPL-M6L I IV I IV I III Characteristic ACPL-W6L/ ACPL-K6L I IV I IV I IV I III Climatic Classification //2 //2 Pollution Degree (DIN VDE /9) 2 2 Unit Maximum Working Insulation Voltage V IORM 67 V peak Input to Output Test Voltage, Method b* V PR 6 27 V peak V IORM x.87 = V PR, % Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a* V PR 97 82 V peak V IORM x.6 = V PR, Type and Sample Test, t m = sec, Partial discharge < pc Highest Allowable Overvoltage (Transient Overvoltage t ini = 6 sec) V IOTM 6 8 V peak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = V R S > 9 > 9 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 677--) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figures for dependence of P S and I S on ambient temperature. 6 7 2 6 C ma mw POWER OUTPUT PS, INPUT CURRENT IS 8 6 2 Surface Mount SO-8 Product P S (mw) I S (ma) POWER OUTPUT PS, INPUT CURRENT IS 7 6 2 Surface Mount SSO-6/SSO-8 Product P S (mw) I S (ma) 2 7 2 7 T S CASE TEMPERATURE ( C) 2 7 2 7 2 T S CASE TEMPERATURE ( C) 6
Absolute Maximum Ratings Parameter Symbol Min. Max. Units Condition Storage Temperature T S +2 C Operating Temperature T A + C Reverse Input Voltage V R V Supply Voltage V DD 6. V Average Forward Input Current I F 8 ma Peak Forward Input Current I F(TRAN) A μs Pulse Width, < pulses/second (I F at μs pulse width, <% duty cycle) 8 ma μs Pulse Width, <% Duty Cycle Output Current I O ma Output Voltage V O. V DD +. V Input Power Dissipation P I mw Output Power Dissipation P O 2 mw Lead Solder Temperature T LS 26 C for sec.,.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Operating Temperature T A + C Input Current, Low Level I FL 2 μa Input Current, High Level I FH.6 6. ma Power Supply Voltage V DD 2.7. V Forward Input Voltage V F (OFF).8 V Electrical Specifications (DC) Over the recommended temperature (T A = C to + C) and supply voltage (2.7V V DD.V). All typical specifications are at V DD = V and T A = 2 C. Parameter Symbol Channel Min. Typ. Max. Units Test Conditions Input Forward Voltage V F.9..7 V I F = 2 ma Figures and 2 Input Reverse Breakdown Voltage BV R V I R = μa Logic High Output Voltage Logic Low Output Voltage V OH V DD. V DD V I F = ma, V I = V (R T =.68 kω) or (R T = 87Ω), I O = 2 μa V DD. V DD V I F = ma, V I = V (R T =.68 kω) or (R T = 87Ω), I O =.2 ma V OL.. V I F = 2 ma, V I = V (R T =.68 kω) or V I =.V (R T = 87Ω), I O = 2 μa.8. V I F = 2 ma, V I = V (R T =.68 kω) or V I =.V (R T = 87Ω), I O =.2 ma Input Threshold Current I TH.7. ma Figure Logic Low Output I DDL Single.8. ma Figure Supply Current Dual.6 2.6 Logic High Output I DDH Single.8. ma Figure Supply Current Dual.6 2.6 Input Capacitance C IN 6 pf f = MHz, V F = V Input Diode Temperature Coefficient ΔV F /ΔT A.6 mv/ C I F = 2 ma 7
Switching Specifications (AC) Over the recommended temperature (T A = C to + C) and supply voltage (2.7V V DD.V). All typical specifications are at V DD = V, T A = 2 C. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time t PHL 6 8 ns I F = 2 ma, V I = V, R T =.68 kω, to Logic Low Output [] C L = pf, CMOS Signal Levels. Propagation Delay Time to Logic High Output [] t PLH 8 ns Pulse Width t PW ns Pulse Width Distortion [2] PWD 6 ns Propagation Delay Skew [] t PSK ns Output Rise Time (% to 9%) Output Fall Time (9% to %) Static Common-Mode Transient Immunity at Logic High Output [] Static Common-Mode Transient Immunity at Logic Low Output [] I F = 2 ma, V I =.V, R T = 87Ω, C L = pf, CMOS Signal Levels. Figures 6 and 7 t R 2 ns I F = 2 ma, V I = V, R T =.68 kω, C L = pf, CMOS Signal Levels. ns I F = 2 ma, V I =.V, R T = 87Ω, C L = pf, CMOS Signal Levels. t F 2 ns I F = 2 ma, V I = V, R T =.68 kω, C L = pf, CMOS Signal Levels. ns I F = 2 ma, V I =.V, R T = 87Ω, C L = pf, CMOS Signal Levels. CM H 2 kv/μs V CM = V, T A = 2 C, I F = ma, V I = V (R T =.68 kω) or (R T = 87Ω), C L = pf, CMOS Signal Levels. Figure 8 CM L 2 kv/μs V CM = V, T A = 2 C, V I = V (R T =.68 kω) or V I =.V (R T = 87Ω), I F = 2 ma, C L = pf, CMOS Signal Levels. Figure 8 Dynamic Common-Mode Transient Immunity [6] CMR D kv/μs V CM = V, T A = 2 C, I F = 2 ma, V I = V (R T =.68 kω) or V I =. V (R T = 87Ω), MBd datarate, the absolute increase of PWD < ns Figure 8 Notes:. t PHL propagation delay is measured from the % (V in or I F ) on the rising edge of the input pulse to the % V DD of the falling edge of the V O signal. t PLH propagation delay is measured from the % (V in or I F ) on the falling edge of the input pulse to the % level of the rising edge of the V O signal. 2. PWD is defined as t PHL - t PLH.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.. CM H is the maximum tolerable rate of rise of the common-mode voltage to assure that the output will remain in a high logic state.. CM L is the maximum tolerable rate of fall of the common-mode voltage to assure that the output will remain in a low logic state. 6. CM D is the maximum tolerable rate of the common-mode voltage during data transmission to assure that the absolute increase of the PWD is less than ns. Package Characteristics All typicals are at T A = 2 C. Parameter Symbol Part Number Min. Typ. Max. Units Test Conditions Input-Output Insulation V ISO ACPL-6L ACPL-M6L ACPL-W6L ACPL-K6L 7 V rms RH < % for min. T A = 2 C Input-Output Resistance R I-O 2 Ω V I-O = V Input-Output Capacitance C I-O.6 pf f = MHz, T A = 2 C 8
9 IF - FORWARD CURRENT (ma) Ith - INPUT THRESHOLD CURRENT (ma) IDDH - LOGIC HIGH OUTPUT SUPPLY CURRENT (ma)...8.6..2..2... V F - FORWARD VOLTAGE (V).V V - -2 2 6 8 2 T A - TEMPERATURE ( C).9.8.7.6....2. V F T A = 2 C Figure. Typical input diode forward current characteristic. Figure. Typical input threshold current versus temperature. I F.V V - 8 2 T A - TEMPERATURE ( C) Figure. Typical logic high output supply current (per channel) versus temperature. tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION (ns) 6 2 T PHL_.V T PLH_.V PWD_.V -. 2 2.... 6 I F - PULSE INPUT CURRENT (ma) Figure 6. Typical switching speed versus pulse input with a V supply voltage. VF - FORWARD VOLTAGE (V) IDDL - LOGIC LOW OUTPUT SUPPLY CURRENT (ma)......2.2.... tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION (ns) - -2 2 6 8 T A - TEMPERATURE ( C) Figure 2. Typical V F versus temperature..9.8.7.6....2. 6 2.V V - 8 2 T A - TEMPERATURE ( C) Figure. Typical logic low output supply current (per channel) versus temperature. T PHL_.V T PLH_.V PWD_.V -. 2 2.... 6 I F - PULSE INPUT CURRENT (ma) Figure 7. Typical switching speed versus pulse input current with a.v supply voltage.
Supply Bypassing, LED Bias Resistors and PC Board Layout The ACPL-x6xL optocouplers are extremely easy to use and feature high-speed, push-pull CMOS outputs. Pull-up resistors are not required. The external components required for proper operation are the input limiting resistors and the output bypass capacitor. Capacitor values should be. μf. For each capacitor, the total lead length connecting the capacitor to the V DD and GND pins should not exceed 2 mm. For ACPL-M6L/W6L: V I =.V: R = Ω ±%, R 2 = 6Ω ±% V I =.V: R = Ω ±%, R 2 = 68Ω ±% R T = R + R 2 R /R 2. For ACPL-6L/K6L: V I =.V: R = Ω ±%, R 2 = Ω ±% V I =.V: R = 8Ω ±%, R 2 = 8Ω ±% R T = R + R 2 R /R 2 V I R I F XXX YWW 6 V DD C =. µf V o V I R I F 2 XXX YWW 6 V DD C =. µf V o GND R 2 GND 2 GND R 2 GND 2 ACPL-M6L ACPL-W6L R V I R 2 GND R 2 GND 2 I F 2 7 XXX YWW 8 6 V DD C =. µf V o V o2 V I R I F GND 2 ACPL-6L/K6L.V/V A IF B Anode Cathode Shield VDD Vo GND C =. µf Output Monitoring node V CM V O V O V V DD GND SWITCH AT A: I = ma F SWITCH AT B: I = 2 ma F V CM (PEAK) V O (min.) V O (max.) CM H CM L Pulse Gen + V CM - Figure 8. Recommended PCB layout and input current-limiting resistor selection.
Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew Propagation delay is a figure of merit that describes how quickly a logic signal propagates through a system. The propagation delay from low-to-high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high-to-low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL. PWD determines the maximum data rate of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, a PWD of 2-% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS22, RS22, T-, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As shown in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges. V I % DATA V O 2.V, CMOS INPUTS CLOCK t PSK V I % DATA V O 2.V, CMOS OUTPUTS CLOCK t PSK Figure 9. Propagation delay skew waveform. t PSK Figure. Parallel data transmission example.
Optocoupler CMR Performance The principal protection against common-mode noise comes from the fundamental isolation properties of the optocoupler, and this in turn is directly related to the Input-Output leakage capacitance of the optocoupler. To provide maximum protection to circuitry connected to the input or output of the optocoupler, the leakage capacitance is minimized by having large separation distances at all points in the optocoupler construction, including the LED/photodiode interface. In addition to the optocouplers' basic physical construction, additional circuit design steps mitigate the effects of common-mode noise. The most important of these is the Faraday shield on the photodetector stage. A Faraday shield is effective in optocouplers because the internal modulation frequency (light) is many orders of magnitude higher than the common-mode noise frequency. Improving CMR Performance at the Application Level In an end application, it is desirable that the optocouplers' common-mode isolation be as close as possible to that indicated in the data sheet specifications. The first step in meeting this goal is to ensure maximum separation between PCB interconnects on either side of the optocoupler is maintained and that PCB tracks beneath the optocoupler are avoided. It is inevitable that a certain amount of CMR noise will be coupled into the inputs and this can potentially result in false-triggering of the input. This problem is frequently observed in devices with high input impedance. In some cases, this can cause momentary missing pulses and may even cause input circuitry to latch-up in some alternate technologies. The ACPL-x6xL optocoupler family does not have an input latch-up issue. Even at very high CMR levels, such as those experienced in end equipment level tests (for example IEC6--), the ACPL-x6xL series is immune to latch-up because of the simple diode structure of the LED. In some cases, achieving the rated data sheet CMR performance level is not possible in an application. This is often because of the practical requirement to actually connect the isolator input to the output of a dynamically changing signal rather than statically tying the input to V DD or GND. A data sheet CMR specmanship issue is often seen with alternative technology isolators that are based on AC-encoding techniques. To address achievable end application performance on data sheets, the ACPL-x6xL optocouplers include an additional typical performance specification for dynamic CMR in the electrical parameter table. The dynamic CMR specification indicates the typical achievable CMR performance as the input is toggled on or off during a CMR transient. The logic output of the ACPL-x6xL optocouplers is mainly controlled by LED current level, and since the LED current features very fast rise and fall times, dynamic noise immunity is essentially the same as static noise immunity. Despite their immunity to input latch-up and the excellent dynamic CMR immunity, ACPL-x6xL optocoupler devices are still potentially vulnerable to misoperation caused by turning the LED either on or off during a CMR disturbance. If the LED status could be ensured by design, the overall application level CMR performance would be that of the photodetector. To benefit from the inherently high CMR capabilities of the ACPL-x6xL family, take the following precautions when operating the LED at the application level. In particular, ensure that the LED stays either on or off during a CMR transient. Some common design techniques to accomplish this include the following: Keep the LED On: Overdrive the LED with a higher-than-required forward current. Keep the LED Off: i) Reverse bias the LED during the off state. ii) Minimize the off-state impedance across the anode and cathode of the LED during the off state. All of these methods allow the full CMR capability of the ACPL-x6xL family to be achieved, but they do have practical implementation issues or require a compromise on power consumption. There is, however, an effective method to meet the goal of maintaining the LED status during a CMR event with no other design compromises other than a single added resistor. This CMR optimization takes advantage of the differential connection to the LED. By ensuring the common-mode impedances at both the cathode and anode of the LED are equal, the CMR transient on the LED is effectively canceled. As shown in Figure, this is easily achieved by using two, instead of one, input bias resistors. 2
Split LED Bias Resistor for Optimum CMR Figure shows the recommended drive circuit for the ACPL-x6xL that gives optimum common-mode rejection. The two current-setting resistors balance the commonmode impedances at the LED s anode and cathode. Common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which is not wanted when the LED should be on) or conversely causing current to be injected into the LED (which is not wanted when the LED should be off). Figure 2 shows the parasitic capacitances (C LA and C LC ) between the LED s anode and cathode, and output ground. Also shown in Figure 2 on the input side is an AC-equivalent circuit. Table shows that the directions of I LP and I LN depend on the polarity of the common-mode transient. For transients occurring when the LED is on, common-mode rejection (CM L, since the output is at "low" state) depends on LED current (I F ). For conditions where I F is close to For ACPL-M6L/W6L: V DD =.V: R = Ω ±%, R 2 = 6Ω ±% V DD =.V: R = Ω ±%, R 2 = 68Ω ±% R T = R + R 2 R /R 2. the switching threshold (I TH ), CM L also depends on the extent to which I LP and I LN balance each other. In other words, any condition where a common-mode transient causes a momentary decrease in I F (meaning when dv CM /dt > and I FP > I FN, referring to Table ) also causes a common-mode failure for transients that are fast enough. Likewise for a common-mode transient that occurs when the LED is off (meaning CM H, since the output is at "high" state), if an imbalance between I LP and I LN results in a transient I F equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below 2V, which constitutes a CM H failure. The resistors recommended in Figure include both the output impedance of the logic driver circuit and the external limiting resistor. The balanced I LED -setting resistors help equalize the common-mode voltage change at the anode and cathode. This reduces I LED changes caused by transient coupling through the parasitic capacitors C LA and C LC shown in Figure 2. For ACPL-6L/K6L: V DD =.V: R = Ω ±%, R 2 = Ω ±% V DD =.V: R = 8Ω ±%, R 2 = 8Ω ±% R T = R + R 2 R /R 2 R V DD2 V DD V O R 2. µf 7LS or any totem-pole output logic gate GND Shield GND 2 Figure. Recommended high-cmr drive circuit for the ACPL-x6xL.
For ACPL-M6L/W6L: V DD =.V: R = Ω ±%, R 2 = 6Ω ±% V DD =.V: R = Ω ±%, R 2 = 68Ω ±% R T = R + R 2 R /R 2. For ACPL-6L/K6L: V DD =.V: R = Ω ±%, R 2 = Ω ±% V DD =.V: R = 8Ω ±%, R 2 = 8Ω ±% R T = R + R 2 R /R 2 R V DD2 I LP V O R 2 C LA. µf I LN C LC Shield GND 2 Figure 2. AC equivalent circuit of ACPL-x6xL. Table. Common-Mode Pulse Polarity and LED Current Transients dv CM /dt Value Resultant I LP Flow Direction Resultant I LN Flow Direction Positive (> ) Away from the LED anode through C LA Negative (< ) Toward the LED anode through C LA If I LP < I LN, LED current I F is momentarily: If I LP > I LN, LED current I F is momentarily: Away from the LED Increased Decreased cathode through C LC Toward the LED Decreased Increased cathode through C LC
Slew-Rate Controlled Outputs Feature Typically, the output slew rate (rise and fall time) will vary with the output load, as more time is required to charge up the higher load. The propagation delay and the PWD both increase with the load capacitance. This will be an issue especially in parallel communication because different communication lines will have different load capacitances. However, Avago s new optocoupler ACPL-x6xL has a built-in slew-rate controlled feature to ensure that the output slew rate remains stable across wide load capacitance. Figure shows the rise time and fall time for ACPL-x6xL at.v and V. Rise Time (ns) 2 2 Rise Time (V DD =.V) pf pf 22 pf pf 7 pf pf 2 2 6 8 Temperature ( C) 2 Fall Time (V DD =.V) 2 Fall Time (ns) pf pf 22 pf pf 7 pf pf 2 2 6 8 Temperature ( C) 2 Rise Time (V DD =.V) 2 Rise Time (ns) pf pf 22 pf pf 7 pf pf 2 2 6 8 Temperature ( C) 2 Fall Time (V DD =.V) Rise Time (ns) 2 pf pf 22 pf pf 7 pf pf 2 2 6 8 Temperature ( C) Figure. Rise and Fall time of ACPL-x6xL across wide-load capacitance.
Speed Improvement A peaking capacitor can be placed across the input current-limit resistor (Figure ) to achieve enhanced speed performance. The value of the peaking capacitor is dependent on the rise and fall time of the input signal, supply voltages, and LED input driving current (I F ). Figure shows significant improvement of propagation delay and pulse with distortion with an added peak capacitor at a driving current of 2 ma and.v/v power supply. tp or PWD (ns) 6 2 V DD2 = V, I F = 2 ma T PHL T PLH T PHL T PLH PWD No Peaking With Peaking V in + GND C peak R 2 R SHIELD. µf V DD2 V GND 2 Figure. Connection of peaking capacitor (C peak ) in parallel with the input limiting resistor (R ) to improve speed performance. 2 2 6 8 Temp ( C) (i) V DD = V, C peak = 7 pf, R = 8Ω tp or PWD (ns) 6 2 T PHL V DD2 =.V, I F = 2 ma T PHL T PLH PWD T PLH No Peaking With Peaking 2 2 6 8 Temp ( C) (ii) V DD =.V, C peak = 7 pf, R = Ω Figure. Improvement of t p and PWD with an added pf peaking capacitor in parallel of input limiting resistor. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. The term Broadcom refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com. Data subject to change. Copyright 26 by Broadcom. All rights reserved. AV2-2EN - September 2, 26 Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxe denotes a lead-free product
Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Avago Technologies: ACPL-6L-E ACPL-M6L-E ACPL-M6L-6E ACPL-M6L-E ACPL-M6L-6E ACPL-6L-6E ACPL-6L-E ACPL-6L-6E ACPL-K6L-E ACPL-K6L-6E ACPL-K6L-E ACPL-K6L-6E ACPL-W6L-E ACPL-W6L-6E ACPL-W6L-E ACPL-W6L-6E