A Low-Noise Programmable-Gain Amplifier for 25Gb/s Multi-Mode Fiber Receivers in 28 nm CMOS FDSOI F. Radice 1, M. Bruccoleri 1, E. Mammei 2, M. Bassi 3, A. Mazzanti 3 1 STMicroelectronics, Cornaredo, Italy 2 STMicroelectronics, Pavia, Italy 3 Università degli Studi di Pavia, Pavia, Italy ESSCIRC 1 of 19
Outline Introduction PGA Design Motivation System-level specifications Circuit design Experimental results Frequency- and Time-domain measurements Considerations and comparisons Conclusions ESSCIRC 2 of 19
Multi-Mode Fibers LANs Data Center is the main MMF market IEEE802.3aq standard foresees a link capable of 16X25Gb/s-per-lane data streams MMF link capability severely limited by Modal Dispersion Electronic Dispersion Compensation (EDC) required ESSCIRC 3 of 19
Dispersion in Multi-Mode Fibers Large fiber core size enables propagation of several modes Different speed leads to different time of arrival and pulse broadening 3 different pulses proposed in IEEE802.3aq to represent channel response ESSCIRC 4 of 19
Electronic Dispersion Compensation AFE PGA w/ EMPHASYS EDC FIR Analog or digital DFE Analog FIR FDBK EDC composed by feed-forward (FIR) and feedback (DFE) equalizers Either analog or digital implementations are possible In both cases, PGA with fine programmable gain is key to exploit maximum dynamic range of the EDC High frequency boost introduced by the PGA helps limiting SNR degradation of FIR equalizer ESSCIRC 5 of 19
Impact of FIR Equalizer on SNR To provide boost near Nyquist frequency, FIR coefficients needs to be alternatively positive and negative in sign DC and energy-rich medium frequencies are attenuated Analog PGA able to recovery the loss at Nyquist relaxes FIR noise specification or ADC resolution Low noise PGA design is key to preserve the advantage ESSCIRC 6 of 19
RX system-level specifications I in TIA Opto-coupler Photo-diode PGA Standard dictates RX optical power from min -6.5dBm to max 0.5dBm and loss of stressors is up to 15dB @ Nyquist Assuming 3dB opto-coupler loss 0.5 A/W photo-diode responsivity (giving 28µA<I in,0pk <140µA) 50dBΩ TIA gain; 25dB SNR @ TIA output (BER=10-12 with some margin); 200mVp-p signal at PGA output PGA requirements are 13.5 to 27.5dB PGA voltage gain range < 0.45mV rms input-referred noise a variable frequency boost up to 10 15 db @ Nyquist ESSCIRC 7 of 19
RX system-level simulations Flat-band PGA Transistor level FIR EDC (behavioural) A MMF Channel Model Coefficients tuning engine Transistor level PGA w/ HF boost FIR EDC (behavioural) B ~8dB peak @ Nyquist ESSCIRC 8 of 19
Proposed Programmable Gain Amplifier (1) Two cascaded fixed-gain (8dB) input stages Two PGA stages with voltage gain ranging from 0 to 14dB Programmable high-frequency peaking by leveraging series and shunt peaking inductors Modified offset nulling loop to suppress noise of the error amplifier ESSCIRC 9 of 19
Proposed Programmable Gain Amplifier (2) PGA stages made of 50 diff. pair in parallel, 40 on simultaneously, 10 with flipped polarity: 20g mi g m 40g mi, and 0dB A v 7dB with 0.6dB step Tail current of each element regulated by 4 additional thermometric bits to refine gain step to ~0.15dB granularity does not impact EDC performance, according to system simulations Device parasitic cap. nearly constant, yielding a stable shape of the transfer function, independent from gain setting ESSCIRC 10 of 19
High-Frequency Boost with RC degeneration Transconductor with RC degeneration is the most popular configuration to provide HF boost: HHHH bbbbbbbbbb = 1 + gg mm RR Degeneration resistor (R) adds significant in-band noise (v 2 n,in) Trade-off between HF boost and v 2 n,in Need small R and high g m ( power) for low noise ESSCIRC 11 of 19
High frequency boost with inductive peaking (1) shunt (a) and series (b) peaking exploited for HF boost HHHH bbbbbbbbbb (a) 1 2ωω nn RRRR 1 + 1 2ωω nn RRRR 2 (b) HHHH bbbbbbbbbb 1 ωω nn RRRR Well suited for high operation frequency Does not add noisy components. No trade-off between HF boost and in-band gain ESSCIRC 12 of 19
High frequency boost with inductive peaking (2) C=90fF R=50Ohm L=580pH C=90fF R=50Ohm L=1.5nH Shunt peaking entails lower-valued lower-q inductors low area Series peaking features a sharp HF roll-off (3rd order network) better filtering of out-of-band noise. Hence we resorted to both ESSCIRC 13 of 19
Chip Microphotograph Manufactured in 28nmFDSOI CMOS technology by STMicroelectronics Ball Grid Array (BGA) flip-chip plastic package Current consumption is 32mA from 1V supply ESSCIRC 14 of 19
AC Measurements Programmable gain from 15dB to 29dB Coarse gain step: 1dB/step Fine gain step: 0.15dB/step -3dB bandwidth > 15GHz Peaking programmable from 0dB to 14dB independent from gain configuration Integrated equivalent input noise less than 300uVrms ESSCIRC 15 of 19
Time Domain Measurements 25Gb/s eye diagram with 5mVp-p input signal and maximum gain 9dB boost exploited to compensate cable, PCB and package losses Waveform acquired without scope averaging, demonstrate good SNR ESSCIRC 16 of 19
Summary and comparison Gain and boost comparable with state-of-the art, but peaking can be tuned independently from gain level Ultra-fine gain steps ~4x equivalent input noise reduction for comparable power dissipation ESSCIRC 17 of 19
Conclusions An analog PGA featuring high-frequency peaking in front of the EDC limits SNR penalty or ADC resolution requirements A 25Gb/s PGA for MMF receivers with up to 14 db HF boost independent from gain configuration and 15 to 29dB gain has been proposed in 28 nm CMOS FDSOI Shunt and series inductors are exploited to achieve programmable high-frequency boost not impairing gain and with a sharp out-of-band rolloff The solution enables very low equivalent input noise at maximum boost (300 μv rms ) with limited power dissipation ESSCIRC 18 of 19