FEATRES Gain of Stable MHz Gain Bandwidth V/µs Slew Rate V/mV DC Gain, R L = Ω mv Maximum Input ffset Voltage ±V Minimum utput Swing into Ω ide Supply Range: ±.V to ±V 7mA Supply Current 9ns Settling Time to.%, V Step Drives All Capacitive Loads APPLICATI S ideband Amplifiers Buffers Active Filters Video and RF Amplification Cable Drivers Data Acquisition Systems DESCRIPTI Very High Speed perational Amplifier The is a very high speed operational amplifier with excellent DC performance. The features reduced input offset voltage and higher DC gain than devices with comparable bandwidth and slew rate. The circuit is a single gain stage with outstanding settling characteristics. The fast settling time makes the circuit an ideal choice for data acquisition systems. The output is capable of driving a Ω load to ±V with ±V supplies and a Ω load to ± 3V on ± V supplies. The circuit is also capable of driving large capacitive loads which makes it useful in buffer or cable driver applications. The is a member of a family of fast, high performance amplifiers that employ Linear Technology Corporation s advanced bipolar complementary processing. TYPICAL APPLICATI MHz,A V = Instrumentation Amplifier Gain of Pulse Response k Ω pf V IN Ω V T k TA TA
ABSLTE AXI RATI GS Total Supply Voltage (V to V )... 3V Differential Input Voltage... ±V Input Voltage...±V S utput Short Circuit Duration (Note )... Indefinite perating Temperature Range C... C to 7 C Maximum Junction Temperature Plastic Package... C Storage Temperature Range... C to C Lead Temperature (Soldering, sec.)... 3 C PACKAGE/RDER I FR NLL IN IN V N PACKAGE -LEAD PLASTIC DIP TP VIE 7 3 NLL V T NC S PACKAGE -LEAD PLASTIC SIC T J MAX = C, θ JA = 3 C/ (N) T J MAX = C, θ JA = C/ (S) P ATI RDER PART NMBER CN CS S PART MARKING ELECTRICAL CHARA CTERISTICS,, V CM = V unless otherwise noted. SYMBL PARAMETER CNDITINS MIN TYP MAX NITS V S Input ffset Voltage (Note ).. mv I S Input ffset Current na I B Input Bias Current µa e n Input Noise Voltage f = khz 7. nv/ Hz i n Input Noise Current f = khz. pa/ Hz R IN Input Resistance V CM = ±V MΩ Differential 7 kω C IN Input Capacitance pf Input Voltage Range V Input Voltage Range 3 V CMRR Common-Mode Rejection Ratio V CM = ±V 9 db PSRR Power Supply Rejection Ratio V S = ±V to ±V 9 db A VL Large Signal Voltage Gain V T = ±V, R L = Ω. V/mV V T utput Swing R L = Ω ±. ±3.3 V I T utput Current V T = ±V ma SR Slew Rate (Note 3) V/µs Full Power Bandwidth V Peak, (Note ). MHz GB Gain Bandwidth f = MHz MHz t r, t f Rise Time, Fall Time A VCL =, % to 9%,.V 7 ns vershoot A VCL =,.V % Propagation Delay % V IN to % V T 7 ns t s Settling Time V Step,.%, A V = 9 ns Differential Gain f = 3.MHz, A V =, R L = Ω. % Differential Phase f = 3.MHz, A V =, R L = Ω.7 Deg R utput Resistance A VCL =, f = MHz. Ω I S Supply Current 7 9 ma
ELECTRICAL CHARA CTERISTICS V S = ±V,, V CM = V unless otherwise noted. SYMBL PARAMETER CNDITINS MIN TYP MAX NITS V S Input ffset Voltage (Note ).. mv I S Input ffset Current na I B Input Bias Current µa Input Voltage Range. V Input Voltage Range 3. V CMRR Common-Mode Rejection Ratio V CM = ±.V 9 db A VL Large-Signal Voltage Gain V T = ±.V, R L = Ω V/mV V T = ±.V, R L = Ω 3 V/mV V T utput Voltage R L = Ω ±3. ±3.7 V R L = Ω ±3. ±3.3 V I T utput Current V T = ±3V ma SR Slew Rate (Note 3) V/µs Full Power Bandwidth 3V Peak, (Note ) 3.3 MHz GB Gain Bandwidth f = MHz MHz t r, t f Rise Time, Fall Time A VCL =, % to 9%,.V 9 ns vershoot A VCL =,.V % Propagation Delay % V IN to % V T 9 ns t s Settling Time.V to.v,.%, A V = 7 ns I S Supply Current 7 9 ma ELECTRICAL CHARA CTERISTICS C T A 7 C, V CM = V unless otherwise noted. SYMBL PARAMETER CNDITINS MIN TYP MAX NITS V S Input ffset Voltage, (Note ).. mv V S = ±V, (Note ).. mv Input V S Drift µv/ C I S Input ffset Current and V S = ±V na I B Input Bias Current and V S = ±V 9 µa CMRR Common-Mode Rejection Ratio, V CM = ±V and V S = ± V, V CM = ±.V 93 db PSRR Power Supply Rejection Ratio V S = ±V to ±V 9 db A VL Large Signal Voltage Gain, V T = ±V, R L = Ω. V/mV V S = ±V, V T = ±.V, R L = Ω V/mV V T utput Swing, R L = Ω ±. ±3.3 V V S = ±V, R L = Ω or Ω ±3. ±3.3 V I T utput Current, V T = ±V ma V S = ±V, V T = ±3V ma SR Slew Rate, (Note 3) V/µs I S Supply Current and V S = ±V 7. ma Note : A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. Note : Input offset voltage is tested with automated test equipment in < second. Note 3: Slew rate is measured between ±V on an output swing of ±V on ±V supplies, and ±V on an output swing of ±3.V on ±V supplies. Note : Full power bandwidth is calculated from the slew rate measurement: FPB = SR/πVp. 3
TYPICAL PERFR A CE CHARA CTERISTICS MAGNITDE F INPT VLTAGE (V) Input Common-Mode Range vs utput Voltage Swing vs Supply Voltage Supply Current vs Supply Voltage Supply Voltage V S < mv V CM VCM SPPLY CRRENT (ma). 7. 7.. TPT VLTAGE SING (V) R L = Ω V S = 3mV V S V S. SPPLY VLTAGE (±V) TPC SPPLY VLTAGE (±V) TPC SPPLY VLTAGE (±V) TPC3 TPT VLTAGE SING (Vp-p) 3 utput Voltage Swing vs Input Bias Current vs Input pen-loop Gain vs Resistive Load Common-Mode Voltage Resistive Load V S = 3mV V S = ±V INPT BIAS CRRENT (µa)... 3. I B I B I B = PEN-LP GAIN (db) 9 7 V S = ±V k 3. k LAD RESISTANCE (Ω) TPC INPT CMMN-MDE VLTAGE (V) TPC LAD RESISTANCE (Ω) TPC SPPLY CRRENT (ma) 9 7 utput Short-Circuit Current vs Supply Current vs Temperature Input Bias Current vs Temperature Temperature 7 INPT BIAS CRRENT (µa)..7... 3.7 3. I B I I B B = 7 TPT SHRT-CIRCIT CRRENT (ma) 3 3 SRCE SINK V S = ±V 7 TEMPERATRE ( C) TPC7 TEMPERATRE ( C) TPC TEMPERATRE ( C) TPC9
TYPICAL PERFR A CE CHARA CTERISTICS INPT VLTAGE NISE (nv/ Hz) Power Supply Rejection Ratio vs Common-Mode Rejection Ratio vs Input Noise Spectral Density Frequency Frequency i n e n A V = R S = k. k k FREQENCY (Hz) TPC.. INPT CRRENT NISE (pa/ Hz) PER SPPLY REJECTIN RATI (db) PSRR k k M FREQENCY (Hz) PSRR M TPC M CMMN MDE REJECTIN RATI (db) k k M M FREQENCY (Hz) LTXXXX TPCXX M VLTAGE GAIN (db) Voltage Gain and Phase vs Frequency Response vs Frequency utput Swing vs Settling Time Capacitive Load V S = ±V V S = ±V k k M FREQENCY (Hz) M M PHASE MARGIN (DEG) TPT SING (V) V S = ± mv SETTLING A V = A V = A V = A V = SETTLING TIME (ns) VLTAGE MAGNITDE (db) M A V = C = pf C = pf C = pf M FREQENCY (HZ) C = pf C = pf M TPC3 LTC TPC TPC TPT IMPEDANCE (Ω). Closed-Loop utput Impedance vs Frequency Gain Bandwidth vs Temperature Slew Rate vs Temperature A V = GAIN BANDIDTH (MHz) 3 9 SLE RATE (V/µs) 3 3 A V = SR SR. k k M M FREQENCY (Hz) M 7 7 TEMPERATRE ( C) 7 TEMPERATRE ( C) TPC TPC7 TPC
APPLICATI S I FR ATI The may be inserted directly into HA, HA, AD7, EL and LM3 applications, provided that the amplifier configuration is a noise gain of or greater, and the nulling circuitry is removed. The suggested nulling circuit for the is shown below. ffset Nulling Layout and Passive Components As with any high speed operational amplifier, care must be taken in board layout in order to obtain maximum performance. Key layout issues include: use of a ground plane, minimization of stray capacitance at the input pins, short lead lengths, RF-quality bypass capacitors located close to the device (typically.µf to.µf), and use of low ESR bypass capacitors for high drive current applications (typically µf to µf tantalum). Sockets should be avoided when maximum frequency performance is required, although low profile sockets can provide reasonable performance up to MHz. For more details see Design Note. Feedback resistor values greater than k are not recommended because a pole is formed with the input capacitance which can cause peaking. If feedback resistors greater than k are used, a parallel capacitor of pf to pf should be used to cancel the input pole and optimize dynamic performance. Transient Response 3 k V The gain-bandwidth is MHz when measured at MHz. The actual frequency response in gain of is considerably higher than 3MHz due to peaking caused by a second pole beyond the gain of crossover point. This is reflected in the small-signal transient response. Higher noise gain configurations exhibit less overshoot as seen in the inverting gain of response. 7 V.µF.µF AI Small Signal, A V = Small Signal, A V = The large-signal response in both inverting and noninverting gain shows symmetrical slewing characteristics. Normally the noninverting response has a much faster rising edge than falling edge due to the rapid change in input common-mode voltage which affects the tail current of the input differential pair. Slew enhancement circuitry has been added to the so that the noninverting slew rate response is balanced. Large Signal, A V = Large Signal, A V = Input Considerations Resistors in series with the inputs are recommended for the in applications where the differential input voltage exceeds ±V continuously or on a transient basis. An example would be in noninverting configurations with high input slew rates or when driving heavy capacitive loads. The use of balanced source resistance at each input is recommended for applications where DC accuracy must be maximized. Capacitive Loading AI AI3 The is stable with all capacitive loads. This is accomplished by sensing the load induced output pole and adding compensation at the amplifier gain node. As the capacitive load increases, both the bandwidth and phase margin decrease so there will be peaking in the frequency
APPLICATI S I FR ATI domain and in the transient response. The photo of the small-signal response with pf load shows % peaking. The large-signal response with a,pf load shows the output slew rate being limited by the short-circuit current. A V =, C L = pf Lag Compensation ein Bridge scillator A V =, C L =,pf The can drive coaxial cable directly, but for best pulse fidelity the cable should be doubly terminated with a resistor in series with the output. TYPICAL APPLICATI V IN Ω pf #37 LAMP k A V =, f < 3MHz 3Ω S V T TA3 AI Compensation The has a typical gain-bandwidth product of MHz which allows it to have wide bandwidth in high gain configurations (i.e., in a gain of it will have a bandwidth of about MHz). The amplifier is stable in a noise gain of so the ratio of the output signal to the inverting input must be / or less. Straightforward gain configurations of or are stable, but there are a few configurations that allow the amplifier to be stable for lower signal gains (the noise gain, however, remains or more). ne example is the summing amplifier shown in the typical applications section below. Each input signal has a gain of R F /R IN to the output, but it is easily seen that this configuration is equivalent to a gain of as far as the amplifier is concerned. Lag compensation can also be used to give a low frequency gain less than with a high frequency gain of or greater. The example below has a DC gain of one, but an AC gain of. The break frequency of the RC combination across the amplifier inputs should be approximately a factor of less than the gain bandwidth of the amplifier divided by the high frequency gain (in this case / of MHz/ or 3MHz). V IN R Ω R Cable Driving R3 7Ω Summing Amplifier R F 7 Ω CABLE R 7Ω V T TA.k pf pf.k V T >V P-P MHz V IN V IN V IN n R IN R IN R IN V T TA R IN = nr F TA Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. 7
SI PLII FED SCHE V 7 ATIC NLL BIAS IN 3 IN BIAS T V LT TA PACKAGE DESCRIPTI.3.3 (7..) Dimensions in inches (millimeters) unless otherwise noted... (.3.) N Package -Lead Plastic DIP.3 ±. (3.3 ±.7). (.) MAX 7.9. (.9.3).3...3..3 ( ). (.) TYP. ±. (.3 ±.3). ±. (. ±.). (3.7) MIN. ±.3 (.7 ±.7). (.) MIN 3. ±. (.3 ±.) N 39.. (..).. (.3.).3.9 (.3.7) S Package -Lead Plastic SIC.. (..).9.97 (..) 7 TYP....7..9 (.3.3). (.7) BSC.. (.79.97)..7 (3. 3.9) Linear Technology Corporation 3 McCarthy Blvd., Milpitas, CA 93-77 () 3-9 FAX: () 3-7 TELEX: 99-3977 3 S 39 LT/GP 9 K REV A LINEAR TECHNLGY CRPRATIN 99