FEATURES 3µV Maximum Offset Voltage pa Maximum Input Bias Current 3µA Supply Current Rail-to-Rail Output Swing µa Supply Current in Shutdown db Minimum Voltage Gain (V S = ±V).µV/ C Maximum V OS Drift nv/ Hz Input Noise Voltage.7V to ±V Supply Voltage Operation Operating Temperature Range: C to C Space Saving 3mm 3mm DFN Package APPLICATIO S U Thermocouple Amplifiers Precision Photo Diode Amplifiers Instrumentation Amplifiers Battery-Powered Precision Systems DESCRIPTIO U LT 3µA, nv/ Hz, Rail-to-Rail Output Precision Op Amp with Shutdown The LT op amp combines low noise and high precision input performance with low power consumption and rail-to-rail output swing. Input offset voltage is trimmed to less than 3µV. The low drift and excellent long-term stability guarantee a high accuracy over temperature and over time. The pa maximum input bias current and db minimum voltage gain further maintain this precision over operating conditions. The LT works on any power supply voltage from.7v to 3V, and draws only 3µA of supply current on a V supply. A power saving shutdown feature reduces supply current to µa. The output voltage swings to within mv of either supply rail, making the amplifier a good choice for low voltage single supply operation. The LT is fully specified at V and ±V supplies and from C to C. The device is available in SO- and space-saving 3mm 3mm DFN packages. This op amp is also available in dual (LT) and quad (LT) packages., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO U Single Supply Current Source for Platinum RTD k AT C RTD* R k, % R k, % R.k.% R Ω % C.µF V OUT = mv AT C 3µV/ C C TO C V S =.7V TO V I CC 3µA µf *OMEGA F3 kω,.% PLATINUM RTD () -3 TAa 3 V S LT 7 LT79-. V S PERCENTAGE OF UNITS (%) Distribution of Offset Voltage Drift V S = ±.V........ DISTRIBUTION (µv/ C) SO- PACKAGES TAb sn fs
LT ABSOLUTE AXI U RATI GS W W W (Note ) Total Supply Voltage (V to V )... V Differential Input Voltage (Note )... V Input Voltage, Shutdown Voltage... V to V Input Current (Note )... ±ma Output Short-Circuit Duration (Note 3)... Indefinite Operating Temperature Range (Note ).. C to C Specified Temperature Range (Note )... C to C U U W PACKAGE/ORDER I FOR ATIO U Maximum Junction Temperature DD Package... C SO- Package... C Storage Temperature Range DD Package... C to C SO- Package... C to C Lead Temperature (Soldering, sec)... 3 C NULL IN IN V 3 TOP VIEW DD PACKAGE -LEAD (3mm 3mm) PLASTIC DFN T JMAX = C, θ JA = C/W UNDERSIDE METAL INTERNALLY CONNECTED TO V (PCB CONNECTION OPTIONAL) 7 NULL V OUT SHDN ORDER PART NUMBER LTCDD LTIDD LTACDD LTAIDD DD PART MARKING* LADU *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. NULL IN IN 3 V TOP VIEW 7 S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/W NULL V OUT SHDN ORDER PART NUMBER LTCS LTIS LTACS LTAIS S PART MARKING I A AI ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. V S = V, V; V CM =.V; R L to V; SHDN =.V, unless otherwise specified. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage (Note 7) LTAS 3 µv T A = C to 7 C µv T A = C to C 7 µv LTS µv T A = C to 7 C µv T A = C to C µv LTADD µv T A = C to 7 C µv T A = C to C µv LTDD 3 µv T A = C to 7 C µv T A = C to C 3 µv V OS / T Input Offset Voltage Drift (Note ) LTAS, LTS.. µv/ C LTADD,LTDD..3 µv/ C sn fs
ELECTRICAL CHARACTERISTICS LT The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. V S = V, V; V CM =.V; R L to V; SHDN =.V, unless otherwise specified. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I OS Input Offset Current (Note 7) LTAS pa T A = C to 7 C pa T A = C to C pa LTS pa T A = C to 7 C 3 pa T A = C to C pa LTADD pa T A = C to 7 C 3 pa T A = C to C pa LTDD 3 pa T A = C to 7 C pa T A = C to C pa I B Input Bias Current (Note 7) LTAS ± pa T A = C to 7 C ± pa T A = C to C ± pa LTS ± pa T A = C to 7 C ±3 pa T A = C to C ± pa LTADD ± pa T A = C to 7 C ±3 pa T A = C to C ± pa LTDD ±3 pa T A = C to 7 C ± pa T A = C to C ± pa Input Noise Voltage.Hz to Hz nv P-P e n Input Noise Voltage Density f = khz nv/ Hz i n Input Noise Current Density f = khz. pa/ Hz R IN Input Resistance Common Mode, V CM = V to 3.V GΩ Differential MΩ C IN Input Capacitance pf V CM Input Voltage Range (Positive) Guaranteed by CMRR 3. V Input Voltage Range (Negative) Guaranteed by CMRR.7 V CMRR Common Mode Rejection Ratio V CM = V to 3.V 7 3 db Minimum Supply Voltage Guaranteed by PSRR..7 V PSRR Power Supply Rejection Ratio V S =.7V to 3V, V CM = /V S 3 db A VOL Large-Signal Voltage Gain R L = k, V OUT = V to V 3 V/mV R L = k, V OUT = V to V V/mV V OUT Maximum Output Swing No Load, mv Overdrive 3 mv (Positive, Referred to V ) mv I SOURCE = ma, mv Overdrive 7 mv mv Maximum Output Swing No Load, mv Overdrive mv (Negative, Referred to V) mv I SINK = ma, mv Overdrive mv 7 mv sn fs 3
LT ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. V S = V, V; V CM =.V; R L to V; SHDN =.V, unless otherwise specified. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I SC Output Short-Circuit Current (Note 3) V OUT = V, V Overdrive (Source) ma ma The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. V S = ±V, V CM = V, R L to V; SHDN =.V, unless otherwise specified. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage (Note 7) LTAS µv T A = C to 7 C µv T A = C to C µv V OUT = V, V Overdrive (Sink) ma ma SR Slew Rate A V =, R F = k, R G = k..9 V/µs T A = C to 7 C. V/µs T A = C to C. V/µs GBW Gain Bandwidth Product f = khz 33 khz khz t s Settling Time A V =,.%, V OUT =.V to 3.V µs t r, t f Rise Time, Fall Time A V =, % to 9%,.V Step µs I SHDN SHDN Pin Current SHDN V.V (On). µa SHDN = V.V (Off) µa t SHDN SHDN Turn-On, Turn-Off Time SHDN = V (On) to V.V (Off) µs SHDN = V.V (Off) to V (On) µs I S Supply Current SHDN V.V (On) 3 µa T A = C to 7 C 9 µa T A = C to C µa SHDN = V.V (Off) µa µa LTS µv T A = C to 7 C µv T A = C to C µv LTADD µv T A = C to 7 C µv T A = C to C 3 µv LTDD 3 µv T A = C to 7 C µv T A = C to C µv V OS / T Input Offset Voltage Drift (Note ) LTAS, LTS.. µv/ C LTADD,LTDD..3 µv/ C I OS Input Offset Current (Note 7) LTAS pa T A = C to 7 C pa T A = C to C pa LTS pa T A = C to 7 C 3 pa T A = C to C pa LTADD pa T A = C to 7 C 3 pa T A = C to C pa sn fs
LT ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. V S = ±V, V CM = V, R L to V; SHDN =.V, unless otherwise specified. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I OS Input Offset Current (Note 7) LTDD 3 pa T A = C to 7 C pa T A = C to C pa I B Input Bias Current (Note 7) LTAS ± pa T A = C to 7 C ± pa T A = C to C ± pa LTS ± pa T A = C to 7 C ±3 pa T A = C to C ± pa LTADD ± pa T A = C to 7 C ±3 pa T A = C to C ± pa LTDD ±3 pa T A = C to 7 C ± pa T A = C to C ± pa Input Noise Voltage.Hz to Hz nv P-P e n Input Noise Voltage Density f = khz 3 nv/ Hz i n Input Noise Current Density f = khz. pa/ Hz R IN Input Resistance Common Mode, V CM = ±3.V GΩ Differential MΩ C IN Input Capacitance pf V CM Input Voltage Range Guaranteed by CMRR ±3. ± V CMRR Common Mode Rejection Ratio V CM = 3.V to 3.V 3 db db Minimum Supply Voltage Guaranteed by PSRR ±. ±.3 V PSRR Power Supply Rejection Ratio V S = ±.3V to ±V 3 db A VOL Large-Signal Voltage Gain R L = k, V OUT = 3.V to 3.V V/mV V/mV R L = k, V OUT = 3.V to 3.V V/mV 3 V/mV V OUT Maximum Output Swing No Load, mv Overdrive mv (Positive, Referred to V ) mv I SOURCE = ma, mv Overdrive 9 mv mv Maximum Output Swing No Load, mv Overdrive mv (Negative, Referred to V) mv I SINK = ma, mv Overdrive mv 3 mv I SC Output Short-Circuit Current (Note 3) V OUT = V, V Overdrive (Source) ma ma V OUT = V, V Overdrive (Sink) ma ma sn fs
LT ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. V S = ±V, V CM = V, R L to V; SHDN =.V, unless otherwise specified. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SR Slew Rate A V =, R F = k, R G = k.. V/µs T A = C to 7 C.7 V/µs T A = C to C. V/µs GBW Gain Bandwidth Product f = khz 7 3 khz khz t s Settling Time A V =,.%, V OUT = V to V µs t r, t f Rise Time, Fall Time A V =, % to 9%,.V Step µs I SHDN SHDN Pin Current SHDN V.V (On). µa Note : Absolute Maximum Ratings are those beyond which the life of the device may be impaired. Note : The inputs are protected by backtoback diodes and internal series resistors. If the differential input voltage exceeds V, the input current must be limited to less than ma. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum ratings. Note : Both the LTC and LTI are guaranteed functional over the operating temperature range of C to C. Note : The LTC is guaranteed to meet the specified performance SHDN = V.V (Off) µa t SHDN SHDN Turn-On, Turn-Off Time SHDN = V (On) to V.V (Off) µs SHDN = V.V (Off) to V (On) µs I S Supply Current SHDN V.V (On) 33 µa T A = C to 7 C 3 µa T A = C to C µa SHDN = V.V (Off) µa from C to 7 C and is designed, characterized and expected to meet specified performance from C to C but is not tested or QA sampled at these temperatures. The LTI is guaranteed to meet specified performance from C to C. Note : This parameter is not % tested. Note 7: The specifications for V OS, I B and I OS depend on the grade and on the package. The following table clarifies the notations used in the specification table: Standard Grade A Grade S Package LTS LTAS DFN Package LTDD LTADD TYPICAL PERFOR A CE CHARACTERISTICS PERCENT OF UNITS (%) 3 UW Distribution of Input Offset Voltage V S = V, V LTAS 3 3 INPUT OFFSET VOLTAGE (µv) G OFFSET VOLTAGE (µv) 7 7 Input Offset Voltage vs Temperature V S = V, V REPRESENTATIVE UNITS 7 TEMPERATURE ( C) G OFFSET VOLTAGE (µv) Offset Voltage vs Input Common Mode Voltage V S = ±V TYPICAL PART T A = C T A = C INPUT COMMON MODE VOLTAGE (V) G3 sn fs
LT TYPICAL PERFOR A CE CHARACTERISTICS UW INPUT BIAS CURRENT (pa) 9 7 3 Input Bias Current vs Temperature V S = V, V TYPICAL PART I B I B 7 TEMPERATURE ( C) G pa/div Input Bias Current vs Input Common Mode Voltage T A = C T A = C V/DIV G INPUT VOLTAGE NOISE DENSITY (nv/ Hz) e n, i n vs Frequency CURRENT NOISE VOLTAGE NOISE V S = ±V G INPUT CURRENT NOISE DENSITY (fa/ Hz) TOTAL INPUT NOISE (µv/ Hz)... Total Input Noise vs Source Resistance V S = V, V f = khz TOTAL NOISE RESISTOR NOISE ONLY NOISE VOLTAGE (.µv/div).hz to Hz Noise V S = ±V NOISE VOLTAGE (.µv/div).hz to Hz Noise V S = ±V. k k k M M SOURCE RESISTANCE (Ω) M 3 7 9 TIME (SEC) 3 7 9 TIME (SEC) G7 G G9 OUTPUT VOLTAGE SWING (mv) V Output Voltage Swing vs Temperature OUTPUT HIGH OUTPUT LOW V S = V, V NO LOAD V 7 TEMPERATURE ( C) G OUTPUT HIGH SATURATION VOLTAGE (V)... Output Saturation Voltage vs Load Current (Output High) V S = V, V T A = C T A = C. LOAD CURRENT (ma) G OUTPUT LOW SATURATION VOLTAGE (V)... Output Saturation Voltage vs Load Current (Output Low) V S = V, V T A = C T A = C. LOAD CURRENT (ma) G sn fs 7
LT TYPICAL PERFOR A CE CHARACTERISTICS SUPPLY CURRENT (µa) 3 3 UW Supply Current vs Supply Voltage Warm-Up Drift THD Noise vs Frequency T A = C T A = C SUPPLY VOLTAGE (±V) G3 CHANGE IN OFFSET VOLTAGE (µv) 3 ±V ±.V 3 9 TIME AFTER POWER-ON (SECONDS) G THD NOISE (%).... V S = V, V V OUT = V P-P A V = : R L = k A V = : R F = R G = k A V = A V = k k k G THD Noise vs Frequency Settling Time vs Output Step Settling Time vs Output Step V S = ±V V IN = V P-P V S = ±V A V = V S = ±V A V = THD NOISE (%).. A V = A V = OUTPUT STEP (V).%.% OUTPUT STEP (V).%.%.. k k 3 7 9 SETTLING TIME (µs) 3 7 9 SETTLING TIME (µs) G G7 G COMMON MODE REJECTION RATIO (db) CMRR vs Frequency TA = C V S = V, V V S = ±V POWER SUPPLY REJECTION RATIO (db) PSRR vs Frequency PSRR PSRR V S = V, V k k k M. k k k M G G sn fs
LT TYPICAL PERFOR A CE CHARACTERISTICS OUTPUT IMPEDANCE (Ω). UW Output Impedance vs Frequency Open-Loop Gain vs Frequency Gain and Phase vs Frequency V S = V, V A V = A V = A V =. k k k M G OPEN-LOOP GAIN (db) V S = V, V R L = k.. k k k M M G3 OPEN-LOOP GAIN (db) 3 3 GAIN PHASE V S = V, V R L = k k k k M M G PHASE SHIFT (DEG) GAIN (db) Gain vs Frequency, A V = Gain vs Frequency, A V = V S = V, V C L = pf C L = pf GAIN (db) V S = V, V C L = pf C L = pf SUPPLY CURRENT IN SHUTDOWN (µa) 3 3 Supply Current in Shutdown Mode vs Temperature V S = V, V V S = ±V k k k M k k k M 3 3 7 9 TEMPERATURE ( C) G G G3 Small-Signal Transient Response Large-Signal Transient Response Rail-to-Rail Output Swing V mv/div V/DIV V V/DIV V A V = µs/div G7 A V = µs/div G V S = ±V A V = µs/div G9 V S = V, V sn fs 9
LT APPLICATIO S I FOR ATIO U W U U Preserving Input Precision Preserving the input accuracy of the LT requires that the applications circuit and PC board layout do not introduce errors comparable to or greater than the µv typical offset of the amplifier. Temperature differentials across the input connections can generate thermocouple voltages of s of microvolts, so the connections to the input leads should be short, close together, and away from heat dissipating components. Air currents across the board can also generate temperature differentials. The extremely low input bias currents (pa typical) allow high accuracy to be maintained with high impedance sources and feedback resistors. The LT low input bias currents are obtained by a cancellation circuit onchip. The input bias currents are permanently trimmed at wafer testing to a low level. Do not try to balance the input resistances in each input lead; instead, keep the resistance at either input as low as possible for maximum accuracy. Leakage currents on the PC board can be higher than the LT s input bias current. For example, GΩ of leakage between a V supply lead and an input lead will generate.na! Surround the input leads by a guard ring, driven to the same potential as the input common mode, to avoid excessive leakage in high impedance applications. Input Protection The LT features on-chip back-to-back diodes between the input devices, along with Ω resistors in series with either input. This internal protection limits the input current to approximately ma (the maximum allowed) for a V differential input voltage. Use additional external series resistors to limit the input current to ma in applications where differential inputs of more than V are expected. For example, a k resistor in series with each input provides protection against 3V differential voltage. Input Common Mode Range The LT output is able to swing nearly to each power supply rail (rail-to-rail out), but the input stage is limited to operating between V V and V.V. Exceeding this common mode range will cause the gain to drop to zero, however no phase reversal will occur. Total Input Noise The LT amplifier contributes negligible noise to the system when driven by sensors (sources) with impedance between kω and MΩ. Throughout this range, total input noise is dominated by the ktr S noise of the source. If the source impedance is less than kω, the input voltage noise of the amplifier starts to contribute with a minimum noise of nv/ Hz for very low source impedance. If the source impedance is more than MΩ, the input current noise of the amplifier, multiplied by this high impedance, starts to contribute and eventually dominate. Total input noise spectral density can be calculated as: vn( TOTAL) = en ktrs ( inrs ) where e n = nv/ Hz, i n =.pa/ Hz and R S the total impedance at the input, including the source impedance. sn fs
LT APPLICATIO S I FOR ATIO Offset Voltage Adjustment U W U U The input offset voltage of the LT and its drift with temperature are permanently trimmed at wafer testing to the low level as specified in the electrical characteristic. However, if further adjustment of V OS is desired, nulling with a k potentiometer is possible and will not degrade drift with temperature. Trimming to a value other than zero creates a drift of (V OS /3µV) µv/ C, e.g., if V OS is adjusted to 3µV, the change in drift will be µv/ C. The adjustment range with a k pot is approximately ±.9mV (see Figures A and B). The sensitivity and resolution of the nulling can be improved by using a smaller pot in conjunction with fixed resistors. The configuration shown has an approximate nulling range of ±µv (see Figures A and B). Standard Adjustment. INPUT 3 k LT V ee V CC 7 OUTPUT Fa CHANGE IN OFFSET VOLTAGE (mv).............. POTENTIOMETER POSITION Figure A Figure B Fb Improved Sensitivity Adjustment INPUT 3 k k k LT V ee V CC 7 OUTPUT Fa CHANGE IN OFFSET VOLTAGE (µv)..... POTENTIOMETER POSITION Figure A Figure B Fb sn fs
LT APPLICATIO S I FOR ATIO Shutdown The LT can be put into shutdown mode to conserve power. When the SHDN pin is biased at less than.v above the negative supply, the part operates normally. When pulled V or more above V, the supply current drops to about µa, shutting down the op amp. The output of the LT op amp is not isolated from the inputs while in shutdown mode. Therefore, this shutdown feature cannot be used for multiplexing applications. There is an internal k resistor at the SHDN pin. If the SHDN voltage source is more than V above the negative supply, an external series resistor can be placed between the source and SHDN pin to reduce SHDN pin current (see Figure 3). For an example of suggested values see Table. The resistors listed ensure that the voltage at the SHDN pin is V above the negative supply. Table V SHDN (V) U W U U R SHDN (kω) NONE 3 77k 3k 3k V SHDN V EE Capacitive Loads R SHDN SHDN Figure 3 k V EE F3 The LT can drive capacitive loads up to pf in unity gain. The capacitive load driving capability increases as the amplifier is used in higher gain configurations. A small series resistance between the output and the load further increases the amount of capacitance that the amplifier can drive. Rail-to-Rail Operation The LT outputs can swing to within millivolts of either supply rail, but the inputs cannot. However, for most op amp configurations, the inputs need to swing less than the outputs. Figure shows the basic op amp configurations, lists what happens to the op amp inputs and specifies whether or not the op amp must have rail-to-rail inputs. Select a rail-to-rail input op amp only when really necessary, because the input precision specifications are usually inferior. V IN R G V REF V IN R G V REF NONINVERTING: A V = R F /R G INPUTS MOVE AS MUCH AS V IN, BUT THE OUTPUT MOVES MORE INPUT MAY NOT HAVE TO BE RAIL-TO-RAIL R F INVERTING: A V = R F /R G OP AMP INPUTS DO NOT MOVE, BUT ARE FIXED AT DC BIAS POINT V REF INPUT DOES NOT HAVE TO BE RAIL-TO-RAIL V IN R F F NONINVERTING: A V = INPUTS MOVE AS MUCH AS THE OUTPUT INPUT MUST BE RAIL-TO-RAIL FOR OVERALL CIRCUIT RAIL-TO-RAIL PERFORMANCE Figure. Some Op Amp Configurations Do Not Require Rail-to-Rail Inputs to Achieve Rail-to-Rail Outputs sn fs
LT SI PLIFIED SCHE ATIC W W V 7 NULL R3 R NULL R R Q7 Q Q Q9 Q Q R C C BIAS CURRENT GENERATOR IN IN 3 R Ω R Ω Q3 Q D D Q Q Q C B A Q B A Q Q Q7 C Q D3 D D Q3 Q C3 Q OUT SHDN Q Q9 Q V SS sn fs 3
LT PACKAGE DESCRIPTIO U DD Package -Lead Plastic DFN (3mm 3mm) (Reference LTC DWG # --9).7 ±. 3. ±.. ±.. ±. ( SIDES) PACKAGE OUTLINE. ±.. BSC.3 ±. ( SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R =. TYP.3 ±. PIN TOP MARK 3. ±. ( SIDES). ±. ( SIDES). REF.7 ±.... ±..3 ±. ( SIDES) BOTTOM VIEW EXPOSED PAD NOTE:. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-9 VARIATION OF (WEED-). ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED. BSC (DD) DFN 3 sn fs
LT PACKAGE DESCRIPTIO U S Package -Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # --). BSC. ±..9.97 (..) NOTE 3 7. MIN. ±... (.79.97)..7 (3. 3.9) NOTE 3.3 ±. TYP RECOMMENDED SOLDER PAD LAYOUT 3.. (.3.).. (..) TYP.3.9 (.3.7).. (..).. (..7) NOTE: INCHES. DIMENSIONS IN (MILLIMETERS)..9 (.3.3) TYP. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED." (.mm). (.7) BSC SO 33 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. sn fs
LT TYPICAL APPLICATIO U Precision JFET Input Transimpedance Photodiode Amplifier C.pF C3 pf V R3 k, % J R 33k, % U LT R k % V R.k U LT3 V OUT S V C.µF C.µF J: PHILIPS BF S: SIEMENS/INFINEON SFH3 PHOTODIODE (~3pF) V SUPPLY = ±V I SUPPLY =.ma BANDWIDTH = MHz A Z = kω OUTPUT OFFSET µv TYPICALLY TA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT/ Dual/Quad Precision Op Amps 3µA, Rail-to-Rail Output LT Low Power, Picoamp Input Precision Op Amp pa Input Bias Current LT Rail-to-Rail Output, Picoamp Input Precision Op Amp C LOAD up to pf sn fs LT/TP 3 K PRINTED IN USA Linear Technology Corporation 3 McCarthy Blvd., Milpitas, CA 93-77 () 3-9 FAX: () 3-7 www.linear.com LINEAR TECHNOLOGY CORPORATION 3