191362; Rev 2; 6/4 Quad, SPST Analog Switch General Description The quad analog switch features onresistance matching (4Ω max) between switches and guarantees onresistance flatness over the signal range (9Ω max). This low onresistance switch conducts equally well in either direction. It guarantees low charge injection (1pC max), low power consumption (35µW max), and an electrostatic discharge (ESD) tolerance of 2V minimum per Method 315.7. The new design offers lower offleakage current over temperature (less than 5nA at +85 C). The quad, singlepole/singlethrow (SPST) analog switch has two normally closed switches and two normally open switches. Switching times are less than 25ns for ton and less than 7ns for toff. Operation is from a single +4.5V to +4V supply or bipolar ±4.5V to ±2V supplies. Applications SampleandHold Circuits Test Equipment HeadsUp Displays Guidance and Control Systems Military Radios Communication Systems BatteryOperated Systems PBX, PABX Audio Signal Routing Modems/Faxes Features Pin Compatible with IndustryStandard DG213 Guaranteed RON Match Between Channels (4Ω max) Guaranteed RFLAT(ON) Over Signal Range (9Ω max) Guaranteed Charge Injection (1pC max) Low OffLeakage Current Over Temperature (<5nA at +85 C) Withstands 2V min ESD, per Method 315.7 Low RDS(ON) (85Ω max) SingleSupply Operation +4.5V to +4V BipolarSupply Operation ±4.5V to ±2V Low Power Consumption (35µW max) RailtoRail Signal Handling TTL/CMOSLogic Compatible Pin Configurations/ Functional Diagrams/TruthTable Ordering Information PART TEMP RANGE PINPACKAGE TOP VIEW D1 IN1 IN2 D2 16 15 14 13 CPE C to +7 C 16 Plastic DIP CSE C to +7 C 16 Narrow SO CEE C to +7 C 16 QSOP S1 1 12 S2 CUE C to +7 C 16 TSSOP** CC/D C to +7 C Dice* 2 3 11 1 ETE 4 C to +85 C 16 Thin QFN (5mm x 5mm) EPE 4 C to +85 C 16 Plastic DIP S4 4 9 S3 ESE 4 C to +85 C 16 Narrow SO EEE 4 C to +85 C 16 QSOP 5 D4 6 7 IN4 IN3 THIN QFN 8 D3 EUE 4 C to +85 C 16 TSSOP** *Contact factory for dice specifications. **Contact factory for availability. Pin Configurations continued at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 18886294642, or visit Maxim s website at www.maximic.com.
ABSOLUTE MAXIMUM RATINGS Voltage Referenced to...+44v...44v to...+44v...(.3v) to ( +.3V) Digital Inputs V V (Note 1)...( 2V) to ( + 2V) or 3mA (whichever occurs first) Continuous Current (any terminal)...3ma Peak Current, or (pulsed at 1ms, 1% duty cycle max)...1ma Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate 1.53mW/ C above +7 C)...842mW Narrow SO (derate 8.7mW/ C above +7 C)...696mW QSOP (derate 8.3mW/ C above +7 C)...667mW Thin QFN (derate 33.3mW/ C above +7 C)...2667mW TSSOP (derate 6.7mW/ C above +7 C)...457mW Operating Temperature Ranges C... C to +7 C E...4 C to +85 C Storage Temperature Range...65 C to +165 C Lead Temperature (soldering, 1sec)...+3 C Note 1: Signals on,, or exceeding or are clamped by internal diodes. Limit forward current to maximum current rating. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supplies ( = 15V, =, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) UNITS Analog Signal Range V ANALOG (Note 3) 15 15 V DrainSource OnResistance R DS(ON) V D = ±1V, 55 7 I S = 1mA T A = T MIN to T MAX 85 Ω OnResistance Match V 4 R D = ±1V, Between Channels (Note 4) DS(ON) I S = 1mA T A = T MIN to T MAX 5 Ω OnResistance Flatness (Note 4) R FLAT(ON) V D = ±5V, 9 I S = 1mA T A = T MIN to T MAX 15 Ω Source Leakage Current V D = ±14V,.5.1.5 IS(OFF) (Note 5) V S = 14V na DrainOff Leakage Current (Note 5) DrainOn Leakage Current (Note 5) Input Current with Input Voltage High Input Current with Input Voltage Low ID(OFF) I D(ON) or I S(ON) I INH ± V D = ±14V, V S = 14V ± V D = ±14V, V S = ±14V V IN = 2.4V, all others =.8V.5.1.5.5.8.5 T A = T MIN to T MAX 1 1.5.1.5 I INL V IN =.8V, all others = 2.4V.5.1.5 SUPPLY PowerSupply Range, ±4.5 ±2. V Positive Supply Current I+ 1.1 1 V IN = or 5V Negative Supply Current I 1.1 1 V IN = or 5V 2 na na
ELECTRICAL CHARACTERISTICS Dual Supplies (continued) ( = 15V, =, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) UNITS Logic Supply Current I L 1.1 1 V IN = or 5V Ground Current I 1.1 1 V IN = or 5V DYNAMIC TurnOn Time (Note 3) t ON V S = ±1V, Figure 2 15 25 ns TurnOff Time (Note 3) t OFF V S = ±1V, Figure 2 9 12 ns BreakBeforeMake Time Delay (Note 3) t D Figure 3 5 2 ns Charge Injection (Note 3) OffIsolation Rejection Ratio (Note 6) C L = 1nF, V GEN =, Q 5 1 pc R GEN =, Figure 4 R L = 5Ω, C L = 5pF, OIRR 6 db f = 1MHz, Figure 5 Crosstalk (Note 7) R L = 5Ω, C L = 5pF, f = 1MHz, Figure 6 1 db SourceOff Capacitance C S(OFF) f = 1MHz, Figure 7 4 pf DrainOff Capacitance C D(OFF) f = 1MHz, Figure 7 4 pf SourceOn Capacitance C S(ON) f = 1MHz, Figure 8 16 pf DrainOn Capacitance C D(ON) f = 1MHz, Figure 8 16 pf ELECTRICAL CHARACTERISTICS Single Supply ( = 12V, = V, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) UNITS Analog Signal Range V ANALOG 12 V DrainSource = 5V; V D = 3V, 8V; 1 16 R OnResistance DS(ON) I S = 1mA T A = T MIN to T MAX 2 Ω SUPPLY PowerSupply Range, 4.5 4 V PowerSupply Current I+ 1.1 1 V IN = or 5V Negative Supply Current I 1.1 1 V IN = or 5V Logic Supply Current I L 1.1 1 V IN = or 5V Ground Current I 1.1 1 V IN = or 5V 3
ELECTRICAL CHARACTERISTICS Single Supply (continued) ( = 12V, =, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER DYNAMIC TurnOn Time (Note 3) TurnOff Time (Note 3) Charge Injection (Note 3) SYMBOL t ON t OFF Q V S = 8V, Figure 2 V S = 8V, Figure 2 C L = 1nF, V GEN =, R GEN =, Figure 4 CONDITIONS MIN TYP MAX (Note 2) 3 4 6 2 5 1 UNITS ns ns pc Note 2: Typical values are for design aid only, are not guaranteed and are not subject to production testing. The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 3: Guaranteed by design. Note 4: Onresistance match between channels and flatness are guaranteed only with bipolarsupply operation. Flatness is defined as the difference between the maximum and the minimum value of onresistance as measured at the extremes of the specified analog signal range. Note 5: Leakage parameters I S(OFF), I D(OFF), I D(ON), and I S(ON) are 1% tested at the maximum rated hot temperature and guaranteed at +25 C. Note 6: OffIsolation Rejection Ratio = 2log (V D /V S ). Note 7: Between any two switches. Typical Operating Characteristics (, unless otherwise noted.) ON LEAKAGE (na) RDS(ON) (Ω) 2 1 1 T A = +85 C ON LEAKAGE CURRENTS T A = +125 C = 15V = 2 15 1 5 5 1 15 V S, 15 125 1 75 5 25 ONRESISTANCE vs. V D (UNIPOLAR SUPPLY VOLTAGE) = 5V = 1V = 15V = 2V 1 4 RDS(ON) (Ω) OFF LEAKAGE (na) 1.5.5 1 12 9 6 3 OFF LEAKAGE CURRENTS T A = +85 C 15 1 5 5 1 15 V S, T A = +125 C = 15V = ONRESISTANCE vs. V D (BIPOLAR SUPPLY VOLTAGE) V± = ±5V V± = ±1V V± = ±15V V± = ±2V 2 5 VIN (V) RDS(ON) (Ω) 3.5 3. 2.5 2. 1.5.5 ING THRESHOLD vs. BIPOLAR SUPPLY VOLTAGE IN HIGH MIN IN LOW MAX ±5 ±1 ±15 ±2 BIPOLAR SUPPLY VOLTAGE (V) 1 8 6 4 2 ONRESISTANCE vs. V D (BIPOLAR SUPPLY VOLTAGE AND TEMPERATURE) = 15V, = T A = +125 C T A = 55 C 3 6 5 1 15 2 2 1 1 2 15 1 5 5 1 15 4
Typical Operating Characteristics (continued) (, unless otherwise noted.) RDS(ON) (Ω) 15 125 1 75 5 ONRESISTANCE vs. V D (UNIPOLAR SUPPLY VOLTAGE AND TEMPERATURE) T A = +125 C T A = 4 C 25 = 12V = 4 8 12 7 TIME (ns) 16 12 8 4 ING TIME vs. BIPOLAR SUPPLY VOLTAGE t ON t OFF ±5 ±1 ±15 ±2 BIPOLAR SUPPLY VOLTAGE (V) 8 TIME (ns) 2 15 1 5 ING TIME vs. UNIPOLAR SUPPLY VOLTAGE t ON t OFF = 1 15 2 25 UNIPOLAR SUPPLY VOLTAGE (V) 9 2 1 = 15V = C L = 1nF CHARGE INJECTION vs. V D VOLTAGE 1 1 5 = 12V = V C L = 1nF CHARGE INJECTION vs. V D VOLTAGE 11 Q (pc) Q (pc) 1 5 2 15 1 1 15 1 5 1 15 5
DIP/SO/TSSOP PIN THIN QFN NAME 1, 8, 9, 16 6, 7, 14, 15 IN1 IN4 Logic Control Input 2, 7, 1, 15 5, 8, 13, 16 D1 D4 AnalogSwitch Drain Output 3, 6, 11, 14 1, 4, 9, 12 S1 S4 AnalogSwitch Source Output 4 2 NegativeSupply Voltage Input 5 3 Ground 12 1 VL LogicSupply Voltage Input FUNCTION 13 11 PositiveSupply Voltage Input Connected to Substrate EP PAD Exposed Pad. Connect PAD to. Pin Description Applications Information General Operation 1) Switches are open when power is off. 2),, and should not exceed or, even with the power off. 3) Switch leakage is from each analog switch terminal to or, not to other switch terminals. Operation with Supply Voltages Other than ±15V Using supply voltages less than ±15V will reduce the analog signal range. The operates with ±4.5V to ±2V bipolar supplies or with a +4.5V to +4V single supply; connect to when operating with a single supply. Also, all device types can operate with unbalanced supplies such as +24V and 5V. must be connected to to be TTL compatible, or to for CMOSlogic level inputs. The Typical Operating Characteristics graphs show typical onresistance with ±2V, ±15V, ±1V, and ±5V supplies. (Switching times increase by a factor of two or more for operation at ±5V.) Overvoltage Protection Proper powersupply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence on first, followed by,, and logic inputs. If powersupply sequencing is not possible, add two small, external signal diodes in series with supply pins for overvoltage protection (Figure 1). Adding diodes reduces the analog signal range to 1V below and 1V above, but low switch resistance and low leakage characteristics are unaffected. Device operation is unchanged, and the difference between and should not exceed +44V. V g S Figure 1. Overvoltage Protection Using External Blocking Diodes D 6
LOGIC OUTPUT +3V V V 5% V OUT.8 x V OUT t ON t OFF tf < 2ns tr < 2ns.8 x V OUT LOGIC OUTPUT OUTPUT Timing Diagrams/Test Circuits +3V V V D V V D V V O2 V O1 5% t D.9V O t D.9V O LOGIC WAVEFORM IS INVERTED FOR ES THAT HAVE THE OPPOSITE LOGIC SENSE. +15V LOGIC +3V +15V C L INCLUDES FIXTURE AND STRAY CAPACITANCE. R L C L V OUT R REPEAT TEST FOR CHANNELS 2, 3, AND 4. L V OUT = V D ( ) Figure 2. Switching Time R L + R DS(ON) V D = 1V V O1 V D = 1V V O2 RL1 R L2 C L2 LOGIC V R L = 1Ω C L = 35pF C L INCLUDES FIXTURE AND STRAY CAPACITANCE. LOGIC. Figure 3. BreakBeforeMake Test Circuit C L1 7
Timing Diagrams/Test Circuits (continued) V OUT V IN Q = V OUT C L V OUT SIGNAL GENERATOR NETWORK ANALYZER 1dBm R GEN = 5Ω or +2.4V R L 1nF +15V 1nF 5Ω or +2.4V +15V R GEN V OUT Figure 6. Crosstalk V GEN C L 1nF +15V V IN = +3V Figure 4. Charge Injection CAPACITANCE METER or +2.4V f = 1MHz 1nF 1nF +15V SIGNAL GENERATOR 1dBm Figure 7. Source/DrainOff Capacitance R GEN = 5Ω or +2.4V 1nF +15V NETWORK ANALYZER R L 1nF CAPACITANCE METER f = 1MHz or +2.4V Figure 5. OffIsolation Rejection Ratio V S 1nF Figure 8. Source/DrainOn Capacitance 8
TOP VIEW Pin Configurations (continued) IN1 D1 S1 1 2 3 4 5 16 15 14 13 12 IN2 D2 S2 S4 6 11 S3 D4 7 1 D3 IN4 8 9 IN3 DIP/SO/QSOP/TSSOP LOGIC SW 1, SW 4 SW 2, SW 3 1 OFF ON ON OFF ES SHOWN FOR LOGIC "" Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maximic.com/packages.) TSSOP4.4mm.EPS 9
Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maximic.com/packages.) MARKING D D/2 XXXXX E/2 k D2 C L D2/2 b L.1 M C A B E2/2 QFN THIN.EPS E (NE1) X e LC E2 PIN # 1 I.D. DETAIL A e (ND1) X e PIN # 1 I.D..35x45 DETAIL B e L1 L C L LC L L.1 C e e A.8 C C A1 A3 DRAWING NOT TO SCALE PACKAGE OUTLINE, 16, 2, 28, 32L THIN QFN, 5x5x.8mm 2114 G 1 2 PKG. 16L 5x5 SYMBOL MIN. NOM. MAX. A A1 A3 b D E e L1 N ND NE JEDEC NOTES:.7.75.8.2.5.2 REF..25 4.9 4.9 16 4 4 WHHB COMMON DIMENSIONS.3.35.25.3 5. 5.1 4.9 5. 5. 5.1 4.9 5..8 BSC..65 BSC. k.25 L.3.4.5 2L 5x5 MIN. NOM. MAX..7.75.8.7.75.8.7.75.8.2.5.2.5.2.5.25.45.2 REF..55 2 5 5 WHHC.35 5.1 5.1.65 28L 5x5 MIN. NOM. MAX..2 4.9 4.9.25.45.2 REF..25 5. 5..5 BSC..55 28 7 7 WHHD1.3 5.1 5.1.65 32L 5x5 MIN. NOM. MAX. 4.9 4.9.25.3.2 REF..2.25.3 5. 5..5 BSC..4 32 8 8 WHHD2 5.1 5.1.5 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 951 SPP12. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. EXPOSED PAD VARIATIONS PKG. D2 E2 L DOWN CODES BONDS MIN. NOM. MAX. MIN. NOM. MAX. ±.15 ALLOWED T16551 3. 3.1 3.2 3. 3.1 3.2 ** NO T16552 3. 3.1 3.2 3. 3.1 3.2 ** YES T1655N1 3. 3.1 3.2 3. 3.1 3.2 ** NO T2552 3. 3.1 3.2 3. 3.1 3.2 ** NO T2553 3. 3.1 3.2 3. 3.1 3.2 ** YES T2554 3. 3.1 3.2 3. 3.1 3.2 ** NO T2555 3.15 3.25 3.35 3.15 3.25 3.35.4 Y T28551 3.15 3.25 3.35 3.15 3.25 3.35 ** NO T28552 2.6 2.7 2.8 2.6 2.7 2.8 ** NO T28553 3.15 3.25 3.35 3.15 3.25 3.35 ** YES T28554 2.6 2.7 2.8 2.6 2.7 2.8 ** YES T28555 2.6 2.7 2.8 2.6 2.7 2.8 ** NO T28556 3.15 3.25 3.35 3.15 3.25 3.35 ** NO T28557 2.6 2.7 2.8 2.6 2.7 2.8 ** YES T28558 3.15 3.25 3.35 3.15 3.25 3.35.4 Y T2855N1 3.15 3.25 3.35 3.15 3.25 3.35 ** N T32552 3. 3.1 3.2 3. 3.1 3.2 ** NO T32553 3. 3.1 3.2 3. 3.1 3.2 ** YES T32554 3. 3.1 3.2 3. 3.1 3.2 ** NO T3255N1 3. 3.1 3.2 3. 3.1 3.2 ** NO ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN.25 mm AND.3 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO22, EXCEPT EXPOSED PAD DIMENSION FOR T28551, T28553 AND T28556. 1. WARPAGE SHALL NOT EXCEED.1 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. DRAWING NOT TO SCALE PACKAGE OUTLINE, 16, 2, 28, 32L THIN QFN, 5x5x.8mm 2114 G 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 1 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 4873776 24 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.