dvanced Process Technology Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching PChannel Fully valanche Rated LeadFree Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G PD 9487 HEXFET Power MOSFET D S V DSS = 50V R DS(on) = 0.29Ω I D = 3 The TO220 package is universally preferred for all commercialindustrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO220 TO220B contribute to its wide acceptance throughout the industry. bsolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 3 I D @ T C = C Continuous Drain Current, V GS @ V 9.0 I DM Pulsed Drain Current 44 P D @T C = 25 C Power Dissipation W Linear Derating Factor 0.7 W/ C V GS GatetoSource Voltage ± 20 V E S Single Pulse valanche Energy2 3 mj I R valanche Current 6.6 E R Repetitive valanche Energy mj dv/dt Peak Diode Recovery dv/dt 3 5.0 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 632 or M3 screw lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase.4 R θcs CasetoSink, Flat, Greased Surface 0.50 C/W R θj Junctiontombient 62 /5/03
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 50 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.20 V/ C Reference to 25 C, I D = m R DS(on) Static DraintoSource OnResistance 0.29 V GS = V, I D = 6.6 4, T J = 25 C Ω 0.58 V GS = V, I D = 6.6 4, T J = 50 C V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 3.6 S V DS = 50V, I D = 6.6 I DSS DraintoSource Leakage Current 25 V DS = 50V, V GS = 0V µ 250 V DS = 20V, V GS = 0V, T J = 50 C I GSS GatetoSource Forward Leakage V GS = 20V n GatetoSource Reverse Leakage V GS = 20V Q g Total Gate Charge 66 I D = 6.6 Q gs GatetoSource Charge 8. nc V DS = 20V Q gd GatetoDrain ("Miller") Charge 35 V GS = V, See Fig. 6 and 3 4 t d(on) TurnOn Delay Time 4 V DD = 75V t r Rise Time 36 I ns D = 6.6 t d(off) TurnOff Delay Time 53 R G = 6.8Ω t f Fall Time 37 R D = 2Ω, See Fig. Between lead, D L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 860 V GS = 0V C oss Output Capacitance 220 pf V DS = 25V C rss Reverse Transfer Capacitance 30 ƒ =.0MHz, See Fig. 5 SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 3 (Body Diode) showing the I SM Pulsed Source Current integral reverse G 44 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.6 V T J = 25 C, I S = 6.6, V GS = 0V 4 t rr Reverse Recovery Time 60 240 ns T J = 25 C, I F = 6.6 Q rr Reverse RecoveryCharge.2.7 µc di/dt = /µs 4 t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) 2 Starting T J = 25 C, L = 4mH R G = 25Ω, I S = 6.6. (See Figure 2) 3 I SD 6.6, di/dt 620/µs, V DD V (BR)DSS, T J 75 C 4 Pulse width 300µs; duty cycle 2%.
I D, DraintoSource Current () VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T Jc = 25 C V DS, DraintoSource Voltage (V) I D, DraintoSource Current () VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T CJ = 75 C V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics, Fig 2. Typical Output Characteristics, I D, DraintoSource Current () T = 25 C J V DS = 50V 20µs PULSE WIDTH 4 5 6 7 8 9 V, GatetoSource Voltage (V) GS T = 75 C J R DS(on), DraintoSource On Resistance (Normalized) 2.5 2.0.5.0 0.5 I = D V GS = V 0.0 60 40 20 0 20 40 60 80 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature
C, Capacitance (pf) 2000 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd 600 C oss = C ds Cgd C iss 200 C oss 800 C rss 400 0 V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) 20 6 2 8 4 I D = 6.6 V DS = 20V V DS = 75V V DS = 30V FOR TEST CIRCUIT 0 SEE FIGURE 3 0 20 40 60 80 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage I SD, Reverse Drain Current () T = 75 C J T = 25 C J I D, Drain Current () OPERTION IN THIS RE LIMITED BY RDS(on) µs µs ms V GS = 0V 0. 0.2 0.6.0.4.8 V SD, SourcetoDrain Voltage (V) T C = 25 C T J = 75 C Single Pulse ms 0 V, DraintoSource Voltage (V) DS Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating rea
5 V DS R D I D, Drain Current () 2 9 6 R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. Fig a. Switching Time Test Circuit V DD 3 0 25 50 75 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature t d(on) t r t d(off) t f % 90% V DS Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase
Fig 2a. Unclamped Inductive Test Circuit I S V DS L R G D.U.T V DD IS 20V DRIVER tp 0.0Ω 5V E S, Single Pulse valanche Energy (mj) 800 600 400 200 TOP BOTTOM ID 2.7 4.7 6.6 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Fig 2c. Maximum valanche Energy Vs. Drain Current tp V (BR)DSS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. V Q G 2V.2µF 50KΩ.3µF Q GS Q GD D.U.T. V DS V G V GS 3m Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit
Peak Diode Recovery dv/dt Test Circuit D.U.T* 3 Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer 2 4 V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD * Reverse Polarity of D.U.T for PChannel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =V ] *** D.U.T. I SD Waveform Reverse Recovery Current Repplied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 4. For PChannel HEXFETS
TO220B Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) 4.69 (.85) 4.20 (.65) B.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) 2 3 4 6.47 (.255) 6. (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LED SSIGNMENTS LED SSIGNMENTS HEXFET IGBTs, CoPCK GTE GTE 2 DRIN GTE 2 DRIN 3 SOURCE 2 COLLECTOR 3 SOURCE 4 DRIN 3 EMITTER 4 DRIN 4 COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) DIMENSIONING & TOLERNCING PER NSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO220B. 2 CONTROLLING DIMENSION : INCH 4 HETSINK & LED MESUREMENTS DO NOT INCLUDE BURRS. TO220B Part Marking Information EXMPLE: THIS IS N IRF LOT CODE 789 SSEMBLED ON WW 9, 997 IN THE SSEMBLY LINE "C" Note: "P" in assembly line position indicates "LeadFree" INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE PRT NUMBER DTE CODE YER 7 = 997 WEEK 9 LINE C Data and specifications subject to change without notice. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (3) 25275 TC Fax: (3) 2527903 Visit us at www.irf.com for sales contact information./03