Model checking in the cloud VIGYAN SINGHAL OSKI TECHNOLOGY

Similar documents
Meeting the Challenges of Formal Verification

Lies, Damned Lies and Hardware Verification. Mike Bartley, Test and Verification Solutions

Introduction to co-simulation. What is HW-SW co-simulation?

Getting to Work with OpenPiton. Princeton University. OpenPit

Introducing Functional Qualification

Formal Hardware Verification: Theory Meets Practice

Policy-Based RTL Design

Overview of Design Methodology. A Few Points Before We Start 11/4/2012. All About Handling The Complexity. Lecture 1. Put things into perspective

Trends in Functional Verification: A 2014 Industry Study

RESPONSIBILITY OF THE SEMICONDUCTOR DESIGN INFRASTRUCTURE

Agenda. 9:30 Registration & Coffee Networking and Sponsor Table-tops Welcome and introduction

Making your ISO Flow Flawless Establishing Confidence in Verification Tools

SYSTEM-ON-A-CHIP (SOC) VERIFICATION METHODS December 6th, 2003

The challenges of low power design Karen Yorav

ERAU the FAA Research CEH Tools Qualification

REVOLUTIONIZING THE COMPUTING LANDSCAPE AND BEYOND.

Virtual Prototyping - For Real Success

Agenda. 9:30 Registration & Coffee Networking and Sponsor Table-tops Welcome and introduction

VLSI testing Introduction

Functional Verification of CSI-2 Rx-PHY using AMS Co-simulations

Simulation + Emulation = Verification Success

The future of formal model checking is NOW!

Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques.

Digital Systems Design

High Speed Digital Systems Require Advanced Probing Techniques for Logic Analyzer Debug

Design in the Late-Silicon Age

Questa ADMS supports all three major methodologies for mixed-signal verification:

Questa ADMS. Analog-Digital Mixed-Signal Simulator. Mixed-Signal Simulator for Modern Design. A Flexible Mixed-Signal Strategy

AMS Verification for High Reliability and Safety Critical Applications by Martin Vlach, Mentor Graphics

Lecture 1. Tinoosh Mohsenin

Practical Concurrent ASIC and System Design and Verification

Chapter 1 Introduction to VLSI Testing

CMOS Technology for Computer Architects

A SURVEY OF VIRTUAL PROTOTYPING TECHNIQUES FOR SYSTEM DEVELOPMENT AND VALIDATION


The role of testing in verification and certification Kerstin Eder

Lecture Perspectives. Administrivia

Using Digital Verification Techniques on Mixed-Signal SoCs with CustomSim and VCS

Two for One: Leveraging SerDes Flows for AMI Model Development

Lecture 30. Perspectives. Digital Integrated Circuits Perspectives

Low Power Design Methods: Design Flows and Kits

EDA Challenges for Low Power Design. Anand Iyer, Cadence Design Systems

Verification and Validation for Safety in Robots Kerstin Eder

FPGA Circuits. na A simple FPGA model. nfull-adder realization

Life Isn t Fair, So Use Formal by Roger Sabbagh, Mentor Graphics

The Need for Gate-Level CDC

DESIGN TECHNOLOGY FOR THE TRILLION-DEVICE FUTURE

Interconnect-Power Dissipation in a Microprocessor

ESE535: Electronic Design Automation. Previously. Today. Precedence. Conclude. Precedence Constrained

Mixed Signal Virtual Components COLINE, a case study

UT90nHBD Hardened-by-Design (HBD) Standard Cell Data Sheet February

CHAPTER 1 INTRODUCTION

A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder

Satellite Tuner Single Chip Simulation with Advanced Design System

Amkor s 2.5D Package and HDFO Advanced Heterogeneous Packaging Solutions

VLSI System Testing. Outline

Lessons Learned from Designing a 65 nm ASIC for Third Round SHA-3 Candidates

EECS 427 Lecture 21: Design for Test (DFT) Reminders

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Projects. Groups of 3 Proposals in two weeks (2/20) Topics: Lecture 5: Transistor Models

FUNCTIONAL VERIFICATION: APPROACHES AND CHALLENGES

Verification Futures The Next 5 Years

Modernised GNSS Receiver and Design Methodology

EDA Industry to Recognize Dr. Chenming Hu with the Phil Kaufman Award at DAC 2013

FPGA Design Process Checklist

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

ASIC Computer-Aided Design Flow ELEC 5250/6250

Welcome to FPGAworld Conference 2018

Advanced FPGA Design. Tinoosh Mohsenin CMPE 491/691 Spring 2012

Analog Mixed-Signal Verification at SOC level: A practical approach for the use of Verilog-AMS vs. SPICE views

Learning Outcomes. Spiral 2 8. Digital Design Overview LAYOUT

CHAPTER 5 NOVEL CARRIER FUNCTION FOR FUNDAMENTAL FORTIFICATION IN VSI

EDA for IC System Design, Verification, and Testing

Lecture 4&5 CMOS Circuits

NRC Workshop on NASA s Modeling, Simulation, and Information Systems and Processing Technology

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,

Processors Processing Processors. The meta-lecture

Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools

Keysight Technologies Understanding the SystemVue To ADS Simulation Bridge. Application Note

Giovanni Squillero

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time

Improving Test Coverage and Eliminating Test Escapes Using Analog Defect Analysis

Computer Aided Design of Electronics

24 Challenges in Deductive Software Verification

Power Management in modern-day SoC

VLSI. at IIT Delhi Placements Placement Brochure. Department of Electrical Engineering. Department of Computer Science and Engineering

Si Photonics Technology Platform for High Speed Optical Interconnect. Peter De Dobbelaere 9/17/2012

Static Power Intent Verification of Power State Switching Expressions Srobona Mitra Senior R&D Engineer, Synopsys India Pvt. Ltd.

2010 IRI Annual Meeting R&D in Transition

Static Power and the Importance of Realistic Junction Temperature Analysis

Lessons Learned from Designing a 65 nm ASIC for Third Round SHA-3 Candidates

Network Event Bulletin

Building IBIS-AMI Models From Datasheet Specifications

Recent Advances in Simulation Techniques and Tools

EECS 140/240A Final Project spec, version 1 Spring 17. FINAL DESIGN due Monday, 5/1/2017 9am

White Paper Stratix III Programmable Power

QUIZ. What do these bits represent?

Top-Down Design of Mixed-Signal Circuits

Lecture 0: Introduction

In 1951 William Shockley developed the world first junction transistor. One year later Geoffrey W. A. Dummer published the concept of the integrated

An EM-aware methodology for a high-speed multi-protocol 28Gbps SerDes design with TSMC 16FFC

Transcription:

Model checking in the cloud VIGYAN SINGHAL OSKI TECHNOLOGY

Views are biased by Oski experience Service provider, only doing model checking Using off-the-shelf tools (Cadence, Jasper, Mentor, OneSpin Synopsys) Have built in the past (UC Berkeley, Cadence, Jasper) 15+ full-time model checking users Customers like NVIDIA, AMD, Cisco, Huawei, Synopsys, Xilinx Most projects are set up as milestone-based Milestones have to show value in a simulation-based plan Have to fit in with the chip schedule Predicting the user and tool run-times is a requirement Hope (a.k.a bug hunting ) is not a strategy 2 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED

Types of post-silicon flaws 60% Verification is the still the largest problem Responses 50% 40% 30% 20% 2004 2007 2010 10% 0% 3 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED Wilson Research Group and Mentor Graphics 2010 Functional Verification Study. Used with permission.

Verification market size (2009)* Millions 450 400 350 300 250 200 150 100 50 0 Gate-level Simulation Formal Formal ($38.3M) $0.4M Simulation ($401.8M) Gate-level formal (equivalence checking) Then (1993): Chrysalis; Now: Cadence, Synopsys RTL formal (model checking) RTL * excluding analog Source: Gary Smith EDA, October 2010 Then (1994): Averant, IBM; Now: Cadence, Jasper, Mentor, OneSpin, Synopsys 4 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED

Motivation: exponential rise in bug-fix cost $10M $1M $100k $10k $1k $100 Tapeout Block-level design Block-level verification Chip-level verification 5 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED ECO phase Silicon is back

A model checking testbench Constraints Checkers (Scoreboard) Design Under Test (DUT) Coverage (code and functional) Abstraction Models 6 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED 10/28/2012

Cloud applicability depends on what you check Internal assertions, automatic checks Relate RTL internals, embedded in RTL E.g. sm[7:0] is one-hot Internal assertions X-propagation, clock gating checks Many, usually easier RTL Interface assertions Relate I/Os on one interface E.g. valid-ack, AMBA AXI4 AXI4 AVIP Interface assertions DDR2 AVIP Fewer, harder End-to-end checkers Models end-to-end functionality End-to-End Checker Replaces simulation Often requires manual abstractions 7 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED 10/28/2012

Where is the bar (for end-to-end formal)? Formal has to be more cost-effective than the alternative Usually bounded proofs are good enough (if bound is good enough!) Need to commit to what can be verified (and not), up front Backed by Coverage (measurable and/or argumentative) 8 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED 10/28/2012

Am I done with model checking? (three C s) Is my list of Checkers complete? Are my Constraints not over-constrained? Is my Complexity strategy complete? (are my proof bounds good enough) Coverage is the missing link 9 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED

Verification manager s dashboard Coverage tracking Bug tracking Runtime status 10 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED 10/28/2012

Model checking with coverage Implement Checkers and Constraints Add Abstractions and/or fix Constraints Run formal verification and collect Coverage Are Coverage goals met? 11 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED Design is formally verified

Cloud can help in later stages Early stages (user intensive, not parallelizable) Building constraints Build abstractions Debugging first checker failures Building multiple checkers Later stages (machine intensive, parallelizable) Running daily/weekly regressions Formal code coverage Thousands to hundreds of thousands of targets Hybrid formal: search from tons of user-specified far states Validate proof depths are good enough 12 Block-level verification Chip-level verification 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED ECO phase Tapeout Silicon is back

Non-technical challenges with cloud Perceived IP risk VP Engineering more conservative than CFO or VP Sales People use SalesForce, CRMs, in same companies Legal responsibility (vendor, cloud host, customer?) Licensing model Time-based-licensing or Pay-per-use First solve the most capital-intensive problems Emulators, costing $1M++ Vendor solutions exist Synopsys VCS in Amazon cloud Private vs public cloud 13 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED

Opportunities with the cloud Access to design and verification environment from anywhere in the world Vendors and customers monitor usage, and build business efficient pay-per-use models Manage peak usage Possible to have flexible architecture plug-in any engines Exploit latest engine advances Lower barrier for proof engine performance feedback back to EDA developers Cloud will happen, don t know when (after emulation?) 14 2011-12 OSKI TECHNOLOGY, INC. ALL RIGHTS RESERVED