Multiple Patterning for Immersion Extension and EUV Insertion Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group
Abstract Multiple Patterning for Immersion Extension and EUV Insertion: The lithography roadmap has been challenged in recent years as the projection wavelength scaling stalled relative to feature size since about 2008 corresponding to our 40nm nodes. While the EUV eco-system makes its closing push on commercialization, design-integration-eda teams have joined together to deploy double patterning techniques for building todays devices. Three nodes of spacer double patterning having kept memory scaling forward, and these memory devices now look to begin insertion of spacer quad patterning. The logic community will benefit from the nodes of experience as spacer double patterning works its way into their FinFET and gate patterning schemes. These efforts are a solid investment because sub-10nm nodes will require EUV combined with spacer double patterning and for their cut masks. New materials for traditional double exposure techniques also continue to be introduced which simplify process steps and lower cost. Multi-patterning now, supplemented with EUV in the future, can keep our technologies scaling thru the decade. P. 2
Roadmaps: I have no direct flight option to Taiwan I have no one-mask solution for DRAM Active Image Source: Applied Materials Internal So, I take 2 flights. So, I use 2 exposures. Airline still makes money, Fab still makes money, A little inconvenient. P. 3
The Many Forms of Double Patterning Double Exposure Illumination Splitting Exposure 1 Exposure 2 Combined Image in Resist Reference: Steven Hsu, ASML, SPIE 2003 Line + Cut, and / or Printed Assist Features + removal Reference: Paving the way to full chip level double patterning, Hening Haffner et al, IBM Pitch Division Sidewall Spacer Double Patterning Double Patterning (litho etch litho etch) Reference: 22nm Half-Pitch, Bencher, SPIE 2008 P. 5
The Many Forms of Double Patterning Double Exposure Illumination Splitting Exposure 1 Exposure 2 Combined Image in Resist Reference: Steven Hsu, ASML, SPIE 2003 Line + Cut, and / or Printed Assist Features + removal Reference: Paving the way to full chip level double patterning, Hening Haffner et al, IBM Pitch Division Sidewall Spacer Double Patterning Double Patterning (litho etch litho etch) P. 6
Double Dipole Lithography Decompose Design into Two mask Principal of Double Dipole Lithography Exposure Wafer Two Times w/ 2 Different Masks and Illumination Settings Design Target Combined Image Reference: Double-exposure mask synthesis using inverse lithography, Amyn Poonawala, J.Micro/Nanolith, Oct 2007 P. 7
Double Dipole Lithography This Illumination With This Mask Prints This Pattern Combined Aerial Image Produces This Pattern Y-Pole X-Pole Widely used starting at 32nm Reference: Steven Hsu, ASML, SPIE 2003 P. 8
Illumination Splitting for Contact Holes Original Reference: Ultimate contact hole resolution using immersion lithography with line / space imaging, V. Truffert, IMEC. P. 9
Illumination Splitting for Contact Holes Original Reference: Ultimate contact hole resolution using immersion lithography with line / space imaging, V. Truffert, IMEC. P. 10
Illumination Splitting for Contact Holes Original Reference: Ultimate contact hole resolution using immersion lithography with line / space imaging, V. Truffert, IMEC. P. 11
Illumination Splitting for Contact Holes P. 12
The Many Forms of Double Patterning Double Exposure Illumination Splitting Exposure 1 Exposure 2 Combined Image in Resist Reference: Steven Hsu, ASML, SPIE 2003 Line + Cut, and / or Printed Assist Features + removal Reference: Paving the way to full chip level double patterning, Hening Haffner et al, IBM Pitch Division Sidewall Spacer Double Patterning Double Patterning (litho etch litho etch) P. 13
Line and Cut Double Patterning Single Patterning Example Double Patterning Example Intel 65nm Poly in SRAM Cell Intel 45nm Poly in SRAM Cell and LOGIC core Litho Process Window Tip-Tip Bridging Line Lengthening Parallel Line Mask Trim Mask Line end control is difficult, Especially with dipole illumination Superior Line End Control Reference: a 45nm Logic Technology with High-K+Metal Gate Transistors, K. Mistry et al, Intel P. 14
Array and Cut for Holes Print Dense Holes or Dense Pillars Apply Block or Trim Mask Result = Mixed Pitch random pattern Yellow = Block / Trim Mask Using Array & Cut to Generate Line and Cut Original Reference: Ultimate contact hole resolution using immersion lithography with line / space imaging, V. Truffert, IMEC. P. 15
The Many Forms of Double Patterning Double Exposure Illumination Splitting Exposure 1 Exposure 2 Combined Image in Resist Line + Cut, and / or Printed Assist Features + removal Pitch Division Sidewall Spacer Double Patterning Double Patterning (litho etch litho etch) Reference: 22nm Half-Pitch, Bencher, SPIE 2008 P. 16
Sidewall Spacer Double Patterning 22nm Half-Pitch from ArF Immersion Litho 88nm pitch Etch Mandrel Deposit Spacer Etch Spacer Ash Mandrel Sidewall Spacer Image 22nm line and space 22nm Half-Pitch Typical Patterning Performance: CDU < 5% of ½ pitch LER / LWR < 5% of ½ pitch Reference: 22nm Half-Pitch Pitch Patterning by CVD Spacer Self Alignment Double Patterning, Bencher, SPIE 2008 P. 17
Sidewall Spacer Double Patterning Incredible Success for 5 Generations of NAND 3 levels (Active, Wordline, Bitline) 5 technology nodes (38nm-20nm) 29 million wafers (as of Sept 2013) Source: Semiconductor Silicon Demand Forecast (ver 1104) Scott Jones, IC Knowledge Source: Semiconductor Insights (Report: 0209-21425-O-5DM-10) P. 18
Sidewall Spacer Double Patterning Incredible Success for 5 Generations of NAND > 21,000 meters 3 levels (Active, Wordline, Bitline) 5 technology nodes (38nm-20nm) 29 million wafers (as of Sept 2013) Top of Mount Everest 29 million wafers Bottom of the Mariana Trench P. 19
The Many Forms of Double Patterning Double Exposure Illumination Splitting Exposure 1 Exposure 2 Combined Image in Resist Line + Cut, and / or Printed Assist Features + removal Reference: Paving the way to full chip level double patterning, Hening Haffner et al, IBM Pitch Division Sidewall Spacer Double Patterning Double Patterning (litho etch litho etch) Reference: 22nm Half-Pitch, Bencher, SPIE 2008 P. 20
SADP + Line & Cut Add Dielectric: Trench Cut Remove Conductor: Line Cut Resist Add additional mask content Trim away a segment of spacer Resist BARC BARC Ox HM M1, M2 Oxide Poly Gate Ox Oxide Trenches Shown after BARC etch to reveal spacers Poly Lines Reference: Gridded Design Rule Scaling: Taking the CPU toward the 16nm node, Bencher, SPIE 2009 P. 21
More examples of SADP + Line & Cut DRAM Active: Sidewall Spacer Pattern Trim Mask (BARC Etched) Transfer Etch 35nm Half-Pitch DRAM STI Logic Contacts: X-Pitch = 60nm Image Source: Applied Materials Internal Reference: Gridded Design Rule Scaling: Taking the CPU toward the 16nm node, Bencher, SPIE 2009 P. 22
The Many Forms of Double Patterning Double Exposure Illumination Splitting Exposure 1 Exposure 2 Combined Image in Resist Reference: Steven Hsu, ASML, SPIE 2003 Line + Cut, and / or Printed Assist Features + removal Reference: Paving the way to full chip level double patterning, Hening Haffner et al, IBM Pitch Division Sidewall Spacer Double Patterning Double Patterning (litho etch litho etch) Reference: 22nm Half-Pitch, Bencher, SPIE 2008 P. 23
SADP Interconnect Wiring SADP on Complex (Computer Solved) Mandrels Routing Target SADP Decomposition SADP Process Ready for Copper Feasible for Interconnect Wiring down to 50nm pitch Reference: Density Multiplication Techniques for 15nm nodes, Bencher, SPIE 2011 P. 24
SADP for 15nm Node Logic BEOL Even this becomes unfeasible < 50nm without EUV By 7nm Node, we will need EUV + SADP for BEOL Reference: Density Multiplication Techniques for 15nm nodes, Bencher, SPIE 2011 P. 25
The Many Forms of Double Patterning Double Exposure Illumination Splitting Exposure 1 Exposure 2 Combined Image in Resist Line + Cut, and / or Printed Assist Features + removal Pitch Division Sidewall Spacer Double Patterning Double Patterning (litho etch litho etch) P. 26
Litho-Etch Litho-Etch for Contact / Via P. 27
Litho-Etch Litho-Etch for Line / Trench CD control across stitching regions create design restrictions P. 28
What is the future? DDL & SMO will continue to drive litho process window expansion SADP + Cut will dominate for resolution scaling and CD/CDU/LWR Control The DDL & SMO Mask technologies will increase process windows on the complex SADP Mandrel and cut masks P. 29
Conclusion: SADP with DDL + Cut Mask When EUV arrives, we will combine them all with EUV Bencher, SPIE 2011 Line & Cut Trench & Cut Bencher, SPIE 2011 15nm ½ pitch zig-zag Bencher, SPIE 2009 Spacer DP Exposure 1 Exposure 2 DDL Image Bencher, SPIE 2008 Reference: Steven Hsu, ASML, SPIE 2003 P. 31