H Very High CMR, Wide Logic Gate Optocouplers Technical Data HCPL- HCPL- HCPL- HCPL- HCNW HCPL- HCPL- HCPL- HCPL- HCNW Features kv/µs Minimum Common Mode Rejection (CMR) at V CM = V (HCPL-///, HCNW) Wide Operating Range:. to Volts ns Propagation Delay Guaranteed over the Full Temperature Range Mbd Typical Signal Rate Low Input Current (. ma to. ma) Hysteresis Totem Pole Output (No Pullup Resistor Required) Available in -Pin DIP, SOIC-, Widebody Packages Guaranteed Performance from - C to C Safety Approval UL Recognized - V rms for minute ( V rms for minute for HCNWXX) per UL CSA Approved VDE Approved with V IORM = V peak (HCPL- / Option only) and V IORM = V peak (HCNWXX only) BSI Certified (HCNWXX only) MIL-STD- Version Available (HCPL-XX/XX) Applications Isolation of High Speed Logic Systems Computer-Peripheral Interfaces Microprocessor System Interfaces Ground Loop Elimination Pulse Transformer Replacement High Speed Line Receiver Power Control Systems Functional Diagram NC ANODE CATHODE ANODE CATHODE CATHODE HCPL-/ HCPL-/ HCNW/ NC SHIELD HCPL-/ V O NC V O V O Description The HCPL-XX, HCPL-XX, and HCNWXX are opticallycoupled logic gates. The HCPL-XX, and HCPL-XX contain a GaAsP LED while the HCNWXX contains an AlGaAs LED. The detectors have totem pole output stages and optical receiver input stages with built-in Schmitt triggers to provide logiccompatible waveforms, eliminating the need for additional waveshaping. A superior internal shield on the HCPL-/, HCPL-, NC ANODE CATHODE HCPL-/ NC SHIELD TRUTH TABLE (POSITIVE LOGIC) LED V O ON HIGH OFF LOW NC V O ANODE SHIELD A. µf bypass capacitor must be connected between pins and. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 9-9E -
HCPL- and HCNW The electrical and switching wide range allow compatibility guarantees common mode characteristics of the HCPLtransient with TTL, LSTTL, and CMOS immunity of kv/µs at XX, HCPL-XX and logic and result in lower power a common mode voltage of HCNWXX are guaranteed from consumption compared to other volts. - C to C and a from high speed couplers. Logic signals. volts to volts. Low I F and are transmitted with a typical Selection Guide propagation delay of ns. Small- Widebody Minimum CMR Input -Pin DIP ( Mil) Outline SO- ( Mil) Hermetic On- Single Dual Single Single Single and dv/dt Current Channel Channel Channel Channel Dual Channel (V/µs) V CM (V) (ma) Package Package Package Package Packages,. HCPL- [,] HCPL- HCNW HCPL- HCPL-. HCPL-,. HCPL-9 [,], [] []. HCPL- HCPL- HCNW HCPL-. HCPL-,. HCPL-XX [] HCPL-XX [] Notes:. HCPL-/9 devices include output enable/disable function.. Technical data for the HCPL-/9, HCPL-XX and HCPL-XX are on separate HP publications.. Minimum CMR of kv/µs with V CM = V can be achieved with input current, I F, of ma. Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-#XXX = VDE V IORM = V peak Option* = Gull Wing Surface Mount Option** = Tape and Reel Packaging Option Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information. *For HCPL-/ only. **Gull wing surface mount option applies to through hole parts only. Schematic I CC I F V F I CC I O V O V F I F SHIELD HCPL-/// HCPL-/ HCNW/ I O V O V F I F SHIELD SHIELD I O V O HCPL-/ -
UR Package Outline Drawings -Pin DIP Package (HCPL-/////) 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER HP XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW UL RECOGNITION.9 (.) MAX.. (.) MAX.. (.) MAX. TYP... -. (..) -.). ±. (. ±.).9 (.) MIN.. (.) MAX.. ±. (. ±.). (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS "V" = OPTION OPTION NUMBERS AND NOT MARKED. -Pin DIP Package with Gull Wing Surface Mount Option (HCPL-/////) PAD LOCATION (FOR REFERENCE ONLY) 9. ±. (. ±.). (.).9 (.). ±. (. ±.).TYP. (.9) 9.9 (.) 9.9 (.9).9 (.). (.). (.). (.).9 (.) MAX.. (.) MAX..9 (.) MAX. 9. ±. (. ±.). ±. (. ±.).. -. (..) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. -
Small-Outline SO- Package (HCPL-/).9 ±. (. ±.) XXX YWW. ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE. ±. (. ±.). (.) BSG. ±. (. ±.) X. (.). ±. (. ±.). (.). ±. (.9 ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. (.) MIN.. ±. (. ±.) -Pin Widebody DIP Package (HCNW/). ±. (. ±.). MAX. (.) HP HCNWXXXX YYWW TYPE NUMBER DATE CODE 9. ±. (. ±.). (.) MAX. TYP.. (.) MAX.. (.) TYP... -. (..) -.). (.).9 (.). (.) MIN.. (.) TYP.. ±. (. ±.). (.). (.) DIMENSIONS IN MILLIMETERS (INCHES). -
-Pin Widebody DIP Package with Gull Wing Surface Mount Option (HCNW/). ±. (. ±.) 9. ±. (. ±.) PAD LOCATION (FOR REFERENCE ONLY). (.) TYP.. ±. (. ±.). (.).9 (.). (.) MAX.. ±. (. ±.). MAX. (.). (.) MAX.. ±. (. ±.). (.) BSC. ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (.9 ±.) NOM... -. (..) -.) Solder Reflow Temperature Profile (HCPL-XX and Gull Wing Surface Mount Option Parts) TEMPERATURE C T = C, C/SEC T = C,. C/SEC T = C,. C/SEC 9 TIME MINUTES Note: Use of nonchlorine activated fluxes is highly recommended. -
Regulatory Information The HCPL-XX/XX and HCNWXX have been approved by the following organizations: UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. VDE Approved according to VDE /.9. (HCPL-/ Option and HCNWXX only) BSI Certification according to BS:99, (BS EN:99); BS EN9:99 (BS:99) and EN:99 for Class II applications. (HCNWXX only) Insulation and Safety Related Specifications -pin DIP Package -Pin DIP Widebody ( Mil) SO- ( Mil) Parameter Symbol Value Value Value Units Conditions Minimum External L()..9 9. mm Measured from input terminals Air Gap (External to output terminals, shortest Clearance) distance through air. Minimum External L()... mm Measured from input terminals Tracking (External to output terminals, shortest Creepage) distance path along body. Minimum Internal... mm Through insulation distance, Plastic Gap conductor to conductor, usually (Internal Clearance) the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Minimum Internal NA NA. mm Measured from input terminals Tracking (Internal to output terminals, along Creepage) internal cavity. Tracking Resistance CTI Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa IIIa Material Group (DIN VDE, /9, Table ) Option - surface mount classification is Class A in accordance with CECC. -
VDE Insulation Related Characteristics (HCPL-/ Option ONLY) Description Symbol Characteristic Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms for rated mains voltage V rms Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR V peak Partial Discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and sample test, V PR 9 V peak t m = sec, Partial Discharge < pc Highest Allowable Overvoltage* (Transient Overvoltage, t ini = sec) V IOTM V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature T S C Input Current I S,OUTPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 Ω I-IV I-III *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE ), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. -
VDE Insulation Related Characteristics (HCNWXX ONLY) Description Symbol Characteristic Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV for rated mains voltage V rms I-III Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR V peak Partial Discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and sample test, V PR V peak t m = sec, Partial Discharge < pc Highest Allowable Overvoltage* (Transient Overvoltage, t ini = sec) V IOTM V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature T S C Current (Input Current I F, P S = ) I S,INPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE ), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - C Average Forward Input Current I F(AVG) ma Peak Transient Input Current ( µs Pulse Width, pps) I F(TRAN). A ( µs Pulse Width, HCNWXX ma < % Duty Cycle) Reverse Input Voltage V R V HCNWXX Average Output Current I O ma Supply Voltage V Output Voltage V O -. V Total Package Power Dissipation P T mw HCPL-X 9 Output Power Dissipation P O See Figure Lead Solder Temperature (Through Hole Parts C for sec., Only). mm below seating plane HCNWXX C for sec., up to seating plane Solder Reflow Temperature Profile (Surface See Package Outline Drawings section Mount Parts Only) -
Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage. V Forward Input Current (ON) I F(ON).* ma HCPL-X. Forward Input Voltage (OFF) V F(OFF) -. V Operating Temperature T A - C Junction Temperature T J - C Fan Out N TTL Loads *The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % LED degradation guardband. The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % LED degradation guardband. Electrical Specifications - C T A C,. V V,. ma I F(ON) * ma, V V F(OFF). V, unless otherwise specified. All Typicals at T A = C. See Note. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Logic Low Output Voltage V OL. V I OL =. ma ( TTL Loads), Logic High Output Voltage V OH. ** V I OH = -. ma,,. I OH = -. ma Output Leakage Current I OHH µa V O =. V I F = ma (V OUT > ) V O = V Logic Low Supply I CCL.. ma =. V V F = V Current.. = V I O = Open HCPL-X.. =. V.. = V Logic High Supply I CCH.. ma =. V I F = ma Current.. = V I O = Open HCPL-X.. =. V.. = V Logic Low Short Circuit I OSL ma V O = =. V V F = V, Output Current V O = = V Logic High Short Circuit I OSH - ma =. V I F = ma, Output Current - = V V O = Input Forward Voltage V F.. V T A = C I F = ma. HCNWXX.. T A = C.9 Input Reverse Breakdown BV R V I R = µa Voltage HCNWXX I R = µa Input Diode Temperature V F -. mv/ C I F = ma Coefficient HCNWXX T A -. Input Capacitance C IN pf f = MHz, V F = V, HCNWXX *For HCPL-X,. ma I F(ON) ma. **Typical V OH = -. V. -9
Switching Specifications (AC) - C T A C,. V V,. ma I * F(ON) ma, V V F(OFF). V. All Typicals at T A = C, = V, I F(ON) = ma unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time t PHL ns Without Peaking Capacitor,, to Logic Low HCNWXX Output Level With Peaking Capacitor Propagation Delay Time t PLH ns Without Peaking Capacitor,, to Logic High HCNWXX Output Level 9 With Peaking Capacitor Output Rise Time (-9%) t r ns, 9 Output Fall Time (9-%) t f ns, 9 Parameter Sym. Device Min. Units Test Conditions Fig. Note Logic High CM H HCPL-/, V/µs V CM = V = V, Common Mode HCPL- I F =. ma T A = C Transient Immunity HCPL- HCNW HCPL-/, V/µs V CM = V HCPL- I F =. ma, V/µs V CM = kv I F =. ma Logic Low CM L HCPL-/, V/µs V CM = V V F = V, Common Mode HCPL- = V Transient HCPL- T A = C Immunity HCNW HCPL-/, V/µs V CM = kv HCPL- HCPL- HCNW *For HCPL-X,. ma I F(ON) ma. I F =. ma for HCPL-. I F =. ma for HCPL-. HCPL- HCNW -
Package Characteristics Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary V ISO V rms RH < %, t = min., Withstand HCNWXX T A = C, Voltage * Input-Output Resistance R I-O Ω V I-O = Vdc HCNWXX T A = C T A = C Input-Output Capacitance C I-O. pf f = MHz, HCNWXX.. T A = C V I-O = Vdc Input-Input Insulation I I-I. µa Relative Humidity = %, Leakage Current t = s, V I-I = V Resistance (Input-Input) R I-I Ω V I-I = V Capacitance (Input-Input) C I-I. pf f = MHz *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note entitled Optocoupler Input-Output Endurance Voltage, publication number 9-E. Notes:. Each channel.. Derate total package power dissipation, P T, linearly above C free-air temperature at a rate of. mw/ C.. Duration of output short circuit time should not exceed ms.. For single devices, input capacitance is measured between pin and pin.. Device considered a two-terminal device: pins,,, and shorted together and pins,,, and shorted together.. The t PLH propagation delay is measured from the % point on the leading edge of the input pulse to the. V point on the leading edge of the output pulse. The t PHL propagation delay is measured from the % point on the trailing edge of the input pulse to the. V point on the trailing edge of the output pulse.. CM H is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V O >. V. CM L is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V O <. V.. For HCPL-/, V O is on pin. 9. Use of a. µf bypass capacitor connected between pins and is recommended.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the VDE Insulation Characteristics Table, if applicable.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the VDE Insulation Characteristics Table.. For HCPL-/ only. Measured between pins and, shorted together, and pins and, shorted together. -
V OL LOW LEVEL OUTPUT VOLTAGE V..9........ - =. V V F = V I O =. ma - - T A TEMPERATURE C I OH HIGH LEVEL OUTPUT CURRENT ma - - - - - - - - - V O =. V V O =. V =. V I F = ma - - T A TEMPERATURE C V O OUTPUT VOLTAGE V I O =. ma =. V T A = C. I O = -. ma. I F INPUT CURRENT ma. Figure. Typical Logic Low Output Voltage vs. Temperature. Figure. Typical Logic High Output Current vs. Temperature. Figure. Typical Output Voltage vs. Forward Input Current. I F FORWARD CURRENT ma... I F V F HCPL-XX HCPL-XX T A = C I F FORWARD CURRENT ma... HCNWXX T A = C I F V F............. V F FORWARD VOLTAGE V V F FORWARD VOLTAGE V Figure. Typical Input Diode Forward Characteristic. PULSE GEN. t r = t f = ns f = khz % DUTY CYCLE V O = V Z O = HCPL-/ HCPL-XX HCNWXX * OUTPUT V O MONITORING NODE D V 9 Ω PULSE GEN. t r = t f = ns f = khz % DUTY CYCLE V O = V Z O = HCPL-X OUTPUT V O MONITORING NODE V INPUT MONITORING NODE R C = pf C = pf THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. kω D D D INPUT MONITORING NODE R C = pf * C = pf D kω 9 Ω D D D R. kω. kω I F (ON). ma ma Ω ma ALL DIODES ARE N9 OR N. THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. R.9 kω. kω I F (ON). ma ma Ω ma INPUT I F I F (ON) % I F (ON) ma ALL DIODES ARE N9 OR N. OUTPUT V O PLH t PHL V OH. V VOL Figure. Circuit for t PLH, t PHL, t r,t f. *. µf BYPASS SEE NOTE 9. -
t P PROPAGATION DELAY ns t PHL HCPL-XX HCPL-XX =. V, V C ( pf) PEAKING CAPACITOR IS USED. SEE FIGURE. *I F =. ma FOR HCPL-X DEVICES. I F (ma).*.* - t PLH - - - t P PROPAGATION DELAY ns t PHL - HCNWXX =. V, V C ( pf) PEAKING CAPACITOR IS USED. SEE FIGURE. I F (ma) t PLH - -.., P O MAXIMUM OUTPUT POWER PER CHANNEL (mw) T A = C T A = C T A = C T A TEMPERATURE C T A TEMPERATURE C SUPPLY VOLTAGE V Figure. Typical Propagation Delays vs. Temperature. Figure. Maximum Output Power per Channel vs. Supply Voltage. V OH HIGH LEVEL OUTPUT VOLTAGE V TYPICAL V OH vs. AT I O = -. ma T A = C t r, t f RISE, FALL TIME ns - = V t r t f - - SUPPLY VOLTAGE V T A TEMPERATURE C Figure. Typical Logic High Output Voltage vs. Supply Voltage. Figure 9. Typical Rise, Fall Time vs. Temperature. B R IN V FF A HCPL-/ HCPL-XX HCNWXX. µf BYPASS OUTPUT V O MONITORING NODE V FF R B A HCPL-/. µf BYPASS OUTPUT V O MONITORING NODE PULSE GENERATOR V CM PULSE GENERATOR V CM V CM V V OH OUTPUT V O V OL V CM (PEAK) SWITCH AT A: I F =. ma** V O (MIN.)* SWITCH AT B: V F = V V O (MAX.)* * SEE NOTE, 9. ** I F =. ma FOR HCPL-/ DEVICES. Figure. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. -
INPUT CURRENT THRESHOLD ma..9.. I F (ON) I F (OFF) HCPL-XX HCPL-XX =. V = V. I F (ON) I F (OFF). - - - INPUT CURRENT THRESHOLD ma..9. I F (ON). I F (OFF). I F (ON) I F (OFF). - HCNWXX =. V = V - - T A TEMPERATURE C T A TEMPERATURE C Figure. Typical Input Threshold Current vs. Temperature. OUTPUT POWER P S, INPUT CURRENT I S HCPL-/ OPTION P S (mw) I S (ma) T S CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S 9 HCNWXX P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE. HCPL-/ HCPL-XX HCNWXX ( V) ( V). kω DATA OUTPUT DATA INPUT TTL OR LSTTL * UP TO LSTTL LOADS OR TTL LOADS *. µf BYPASS Figure a. Recommended LSTTL to LSTTL Circuit where ns Propagation Delay is Sufficient. -
( V) Ω. kω pf HCPL-/ HCPL-XX HCNWXX ( V) DATA OUTPUT DATA INPUT TTL OR LSTTL * UP TO LSTTL LOADS OR TTL LOADS *. µf BYPASS Figure b. Recommended LSTTL to LSTTL Circuit for Applications Requiring a Maximum Allowable Propagation Delay of ns. ( V) DATA INPUT TOTEM POLE OUTPUT GATE Ω*. kω TTL OR LSTTL pf* V V V V HCPL-/ HCPL-XX HCNWXX R L. kω. kω. kω. kω ** (. TO V) R L CMOS **. µf BYPASS DATA OUTPUT * pf PEAKING CAPACITOR MAY BE OMITTED AND Ω RESISTOR MAY BE SHORTED WHERE ns PROPAGATION DELAY IS SUFFICIENT. ( V) DATA INPUT TTL or LSTTL. kω D HCPL-/ HCPL-XX HCNWXX D (N) REQUIRED FOR ACTIVE PULL-UP DRIVER. Figure. LSTTL to CMOS Interface Circuit. Figure. Alternative LED Drive Circuit. ( V) DATA INPUT Ω*. kω pf*. kω TTL OR LSTTL HCPL-/ HCPL-XX HCNWXX OPEN COLLECTOR GATE * pf PEAKING CAPACITOR MAY BE OMITTED AND Ω RESISTOR MAY BE SHORTED WHERE ns PROPAGATION DELAY IS SUFFICIENT. Figure. Series LED Drive with Open Collector Gate (. k Resistor Shunts I OH from the LED). -