TVS Diode Arrays The SP73 is an array of SCR/Diode bipolar structures for ESD and over-voltage protection of sensitive input circuits. The SP73 has protection SCR/Diode device structures per input. There are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. Over-voltage protection is from the (Pins - 3 and Pins - 7) to or. The SCR structures are designed for fast triggering at a threshold of one +V BE diode threshold above (Pin ) or a -V BE diode threshold below (Pin ). From an input, a clamp to is activated if a transient pulse causes the input to be increased to a voltage level greater than one V BE above. A similar clamp to is activated if a negative pulse, one V BE less than, is applied to an input. Refer to Fig and Table for further details. Refer to Application Note AN930 and AN96 for further detail. Ordering Information PART NO. TEMP. RANGE ( o C) PACKAGE ENVIRONMENTAL FORMATON MARKG Min. Order SP73APP -0 to 0 Ld PDIP Lead-free 73APP 000 SP73ABG -0 to 0 Ld SOIC Green 73AG 960 SP73ABTG -0 to 0 Ld SOIC Tape and Reel Green 73AG 00 Features ESD Interface per HBM Standards - IEC 6000--, Direct Discharge................. kv (Level ) - IEC 6000--, Air Discharge.................. kv (Level ) - MIL-STD-30.7.................................... kv Peak Current Capability - IEC 6000-- /0µs Peak Pulse Current................. ±7A - Single Transient Pulse, 00s Pulse Width.................. ±A Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to........................ +30V - Differential Voltage Range to........................... ±V Fast Switching.................................. ns Risetime Functional Diagram Low Input Leakages........................ na at o C Typical Low Input Capacitance............................. pf Typical An Array of 6 SCR/Diode Pairs Operating Temperature Range.................... -0 o C to 0 o C Applications 3, -7 Microprocessor/Logic Input Protection Data Bus Protection Analog Device Input Protection Voltage Clamp Pinout SP73 (PDIP, SOIC) TOP VIEW 7 3 6
Absolute Maximum Ratings Continuous Supply Voltage, () - ().... +3V Forward Peak Current, I to V CC, I to GND (Refer to Figure 6)....±A, 00µs Peak Pulse Current, /0µs... ±7A ESD Ratings and Capability (Figure, Table ) Load Dump and Reverse Battery (Note ) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specification T A =0 o C to 0 o C, V = 0.V CC, Unless Otherwise Specified Thermal Information Thermal Resistance (Typical, Note ) JA ( o C/W) PDIP Package....60 SOIC Package.... 70 Storage Temperature Range....-6 o C to 0 o C Maximum Junction Temperature...0 o C Lead Temperature (Soldering 0s).... 300 o C (SOIC - Lead Tips Only) TVS DIODE ARRAYS ESD Capability ESD capability is dependent on the application and defined test standard.the evaluation results for various test standards and methods based on Figure are shown in Table. The SP73 has a Level HBM capability when tested as a device to the IEC 6000-- standard. Level specifies a required capability greater than kv for direct discharge and greater than kv for air discharge. For the Modified MIL-STD-30.7 condition that is defined as an incircuit method of ESD testing, the and pins have a return path to ground and the SP73 ESD capability is typically greater than kv from 00pF through.kω. By strict definition of MIL-STD-30.7 using pinto-pin device testing, the ESD voltage capability is greater than 0kV. For the SP73 EIAJ IC Machine Model (MM) standard, the ESD capability is typically greater than kv from 00pF with no series resistance. STANDARD TYPE/MODE R D C D ±V D IEC 000-- (Level ) HBM, Air Discharge 330Ω 0pF kv HBM, Direct Discharge 330Ω 0pF kv MIL-STD-30.7 Modified HBM.kΩ 00pF kv Standard HBM.kΩ 00pF 0kV EIAJ IC Machine Model 0kΩ 00pF kv H.V. SUPPLY ±V D TABLE. ESD TEST CONDITIONS CHARGE SWITCH R C D R D IEC 000--: R 0 to 00MΩ MIL-STD-30.7: R to 0MΩ DISCHARGE SWITCH DUT FIGURE. ELECTROSTATIC DISCHARGE TEST
TVS Diode Arrays 00 T A = o C SGLE PULSE T A = o C SGLE PULSE 60 FORWARD SCR CURRENT (ma) 0 0 0 FORWARD SCR CURRENT (A) 3 EQUIV. SAT. ON THRESHOLD ~.V V FWD I FWD 0 600 00 000 00 FORWARD SCR VOLTAGE DROP (mv) 0 0 3 FORWARD SCR VOLTAGE DROP (V) FIGURE. LOW CURRENT SCR FORWARD VOLTAGE DROP CURVE +V CC FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP CURVE +V CC PUT DRIVERS OR SIGNAL SOURCES LEAR OR DIGITAL IC TERFACE - 3-7 TO +V CC SP73 SP73 PUT PROTECTION CIRCUIT ( OF 6 SHOWN) FIGURE. TYPICAL APPLICATION OF THE SP73 AS AN PUT CLAMP FOR OVER-VOLTAGE, GREATER THAN V BE ABOVE OR LESS THAN -V BE BELOW 6
Peak Transient Current Capability of the SP73 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP73 s ability to withstand a wide range of peak current pulses vs time. The circuit used to generate current pulses is shown in Figure. The test circuit of Figure is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP73 input pin and the (+) current pulse input goes to the SP73 pin. The to supply of the SP73 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 6 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of o C and 0 o C and a V power supply condition. The safe operating range of the transient peak current should be limited to no more than 7% of the measured overstress level for any given pulse width as shown in the curves of Figure 6. Note that adjacent input pins of the SP73 may be paralleled to improve current (and ESD) capability. The sustained peak current capability is increased to nearly twice that of a single pin. + V X - R VOLTAGE PROBE R ~ 0Ω TYPICAL V X ADJ. 0V/A TYPICAL C ~ 00µF (+) VARIABLE TIME DURATION CURRENT PULSE GENERATOR CURRENT SENSE 3 (-) 7 + SP73 6 C - FIGURE. TYPICAL SP73 PEAK CURRENT TEST CIRCUIT WITH A VARIABLE PULSE WIDTH PUT PEAK CURRENT (A) 0 6 T A = 0 o C T A = o C CAUTION: SAFE OPERATG CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 7% OF THE VALUES SHOWN ON EACH CURVE. TO SUPPLY = V TVS DIODE ARRAYS 0 0.00 0.0 0. PULSE WIDTH TIME (ms) 0 00 000 FIGURE 6. SP73 TYPICAL SGLE PULSE PEAK CURRENT CURVES SHOWG THE MEASURED POT OF OVERSTRESS AMPERES vs PULSE WIDTH TIME MILLISECONDS 7
TVS Diode Arrays Dual-In-Line Plastic Packages (PDIP) E.3 (JEDEC MS-00-BA ISSUE D) DEX AREA BASE PLANE SEATG PLANE D B -C- -A- N 3 N/ B D e D E -B- A 0.00 (0.) M C A A L B S NOTES:. Controlling Dimensions: CH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-9. 3. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-3.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E.3, E6.3, E.3, E.3, E.6 will have a B dimension of 0.030-0.0 inch (0.76 -.mm). A e C E C L e A C e B LEAD DUAL--LE PLASTIC PACKAGE CHES MILLIMETERS SYMBOL M MAX M MAX NOTES A - 0.0 -.33 A 0.0-0.39 - A 0. 0.9.93.9 - B 0.0 0.0 0.36 0. - B 0.0 0.070..77, 0 C 0.00 0.0 0.0 0.3 - D 0.3 0.00 9.0 0.6 D 0.00-0.3 - E 0.300 0.3 7.6. 6 E 0.0 0.0 6.0 7. e 0.00 BSC. BSC - e A 0.300 BSC 7.6 BSC 6 e B - 0.30-0.9 7 L 0. 0.0.93 3. N 9
Small Outline Plastic Packages (SOIC) M. (JEDEC MS-0-AA ISSUE C) N DEX AREA 3 e D B 0.(0.00) M C A M E -B- -A- -C- SEATG PLANE A B S H A µ 0.(0.00) M B 0.0(0.00) L M h x o NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M-9. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.006 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.0 inch). 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C LEAD NARROW BODY SMALL OUTLE PLASTIC PACKAGE CHES MILLIMETERS SYMBOL M MAX M MAX NOTES A 0.03 0.06.3.7 - A 0.000 0.009 0.0 0. - B 0.03 0.00 0.33 0. 9 C 0.007 0.009 0.9 0. - D 0.90 0.96.0.00 3 E 0.97 0.7 3.0.00 e 0.00 BSC.7 BSC - H 0. 0.0.0 6.0 - h 0.0099 0.096 0. 0.0 L 0.06 0.00 0.0.7 6 N 7 µ 0 o o 0 o o - TVS DIODE ARRAYS 9
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