Analog and Telecommunication Electronics

Similar documents
Analog and Telecommunication Electronics

Analog and Telecommunication Electronics

Telecommunication Electronics

Analog and Telecommunication Electronics

Telecommunication Electronics

Fundamentals of Data Converters. DAVID KRESS Director of Technical Marketing

Page 1. Telecommunication Electronics TLCE - C4 27/10/ DDC 1. Politecnico di Torino ICT School. Lesson C4: signal conditioning

Lecture #6: Analog-to-Digital Converter

APPLICATION NOTE 3942 Optimize the Buffer Amplifier/ADC Connection

SECTION 4 HIGH SPEED SAMPLING AND HIGH SPEED ADCs, Walt Kester

ADC and DAC Standards Update

Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999

Enhancing Analog Signal Generation by Digital Channel Using Pulse-Width Modulation

Pipeline vs. Sigma Delta ADC for Communications Applications

High Speed ADC Analog Input Interface Considerations by the Applications Engineering Group Analog Devices, Inc.

Reference Clock Distribution for a 325MHz IF Sampling System with over 30MHz Bandwidth, 64dB SNR and 80dB SFDR

MSP430 Teaching Materials

Analog and Telecommunication Electronics

Understanding AWG70000A Series Frequency Response and DAC Performance

New Features of IEEE Std Digitizing Waveform Recorders

Telecommunication Electronics

The Case for Oversampling

In The Name of Almighty. Lec. 2: Sampling

National Instruments Flex II ADC Technology The Flexible Resolution Technology inside the NI PXI-5922 Digitizer

Modern communication and measurement system designs are

Analog and Telecommunication Electronics

Appendix A Comparison of ADC Architectures

Analog and Telecommunication Electronics

DC-Coupled, Fully-Differential Amplifier Reference Design

Summary Last Lecture

Analog and Telecommunication Electronics

ELT Receiver Architectures and Signal Processing Exam Requirements and Model Questions 2018

The need for Data Converters

A 12 bit 125 MHz ADC USING DIRECT INTERPOLATION

Choosing the Best ADC Architecture for Your Application Part 3:

Hideo Okawara s Mixed Signal Lecture Series. DSP-Based Testing Fundamentals 6 Spectrum Analysis -- FFT

Data Converters. Specifications for Data Converters. Overview. Testing and characterization. Conditions of operation

Telecommunication Electronics

Lecture 10, ANIK. Data converters 2

Digital Waveform Recorders

2.4 A/D Converter Survey Linearity

Testing A/D Converters A Practical Approach

Dynamic Specifications for Sampling A D Converters

Lecture 9, ANIK. Data converters 1

Laboratory Manual 2, MSPS. High-Level System Design

Rohde & Schwarz EMI/EMC debugging with modern oscilloscope. Ing. Leonardo Nanetti Rohde&Schwarz

Maximizing GSPS ADC SFDR Performance: Sources of Spurs and Methods of Mitigation

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2015 Lecture #5

Considerations for digital readouts for a submillimeter MKID array camera

Relationship Between ADC Performance and Requirements of Digital-IF Receiver for WCDMA Base-Station

Clock signal requirement for high-frequency, high dynamic range acquisition systems

DATASHEET HI5805. Features. Applications. Ordering Information. Pinout. 12-Bit, 5MSPS A/D Converter. FN3984 Rev 7.00 Page 1 of 12.

Summary Last Lecture

Data Converters. Springer FRANCO MALOBERTI. Pavia University, Italy

Oversampling Data Converters Tuesday, March 15th, 9:15 11:40

Analog & Telecommunication Electronics

Lab.3. Tutorial : (draft) Introduction to CODECs

Why/When I need a Spectrum Analyzer. Jan 12, 2017

Section 4. Applying Undersampling Converters High-Speed ADC Systems

Receiver Architecture

Electronics A/D and D/A converters

Direct Digital Down/Up Conversion for RF Control of Accelerating Cavities

FMC ADC 125M 14b 1ch DAC 600M 14b 1ch Technical Specification

Digital Time-Interleaved ADC Mismatch Error Correction Embedded into High-Performance Digitizers

EE 230 Lecture 39. Data Converters. Time and Amplitude Quantization

Multirate DSP, part 3: ADC oversampling

Workshop ESSCIRC. Low-Power Data Acquisition System For Very Small Signals At Low Frequencies With12-Bit- SAR-ADC. 17. September 2010.

ERROR CORRECTION TECHNIQUES IN HIGH-SPEED A/D AND D/A CONVERTERS

Fundamentals of Arbitrary. Waveform Generation

The Fundamentals of Mixed Signal Testing

PXIe Contents SPECIFICATIONS. 14 GHz and 26.5 GHz Vector Signal Analyzer

Data Conversion Techniques (DAT115)

ENGINEERING FOR RURAL DEVELOPMENT Jelgava, EDUCATION METHODS OF ANALOGUE TO DIGITAL CONVERTERS TESTING AT FE CULS

CLC Bit, 52 MSPS A/D Converter

Discrete Fourier Transform

CHAPTER. delta-sigma modulators 1.0

670 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 19, NO. 3, JUNE /$ IEEE

The Battle for Data Fidelity:Understanding the SFDR Spec

How to turn an ADC into a DAC: A 110dB THD, 18mW DAC using sampling of the output and feedback to reduce distortion

Using High Speed Differential Amplifiers to Drive Analog to Digital Converters

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2017 Lecture #5

Analog and Digital Signals

RF Receiver Hardware Design

Analog & Telecommunication Electronics

Satellite Communications: Part 4 Signal Distortions & Errors and their Relation to Communication Channel Specifications. Howard Hausman April 1, 2010

24-Bit, 312 ksps, 109 db Sigma-Delta ADC with On-Chip Buffers and Serial Interface AD7764

SBAS303C DECEMBER 2003 REVISED MARCH 2004 SPECIFIED TEMPERATURE RANGE

CMOS Analog to Digital Converters : State-of-the-Art and Perspectives in Digital Communications ADC

System on a Chip. Prof. Dr. Michael Kraft

AN-502 APPLICATION NOTE Designing a Superheterodyne Receiver Using an IF Sampling Diversity Chipset by Brad Brannon

For the system to have the high accuracy needed for many measurements,

TLCE - A3 08/09/ /09/ TLCE - A DDC. IF channel Zc. - Low noise, wide dynamic Ie Vo 08/09/ TLCE - A DDC

781/ /

TESTING DIGITAL RECEIVER PERFORMANCE THROUGH AN HF ENVIRONMENT SIMULATOR. Wayne Phillip Pennington

01/26/2015 DIGITAL INTERLEAVED PWM FOR ENVELOPE TRACKING CONVERTERS. Pallab Midya, Ph.D.

ADC07D1520. Low Power, 7-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter. General Description. Features. Key Specifications.

EE 421L Digital Electronics Laboratory. Laboratory Exercise #9 ADC and DAC

The best radio for worst events. Over HF links. Hana Rafi - CEO Eder Yehuda - VP R&D

EE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K.

Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling Track-And-Hold Circuit

Transcription:

Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D6 - High speed A/D converters» Spectral performance analysis» Undersampling techniques» Sampling jitter» Interleaving ADC» Dithering AY 2015-16 04/05/2016-1 ATLCE - D6-2012 DDC 2012 DDC 1

Lesson D6: high speed ADC Spectral performance analysis Undersampling techniques Sampling jitter Interleaving ADC Dithering References: Application Report SLAA510 January 2011 ADC Input Noise: Is No Noise Good Noise? Analog Dialogue, - Febr 2006 04/05/2016-2 ATLCE - D6-2012 DDC 2012 DDC 2

SNR t and ENOB Each unit in the ADC chain introduces errors and noise Aliasing, quantization, sampling jitter Other errors (amplifier, mux, ) Actual accuracy depends from all these elements Key parameter: total Signal/Noise ratio: SNR t Not just the bit number N of the A/D ENOB = (SNR t - 1,76)/6 = SNR/6-0,3 Represents the number of actually useful bits of the ADC (sys) ENOB is always less then N ENOB = N-1, N-2.. good system design ENOB < N-3.. bad system design 04/05/2016-3 ATLCE - D6-2012 DDC 2012 DDC 3

AD systems glossary (similar to ampl.) SNR: Signal-to-Noise Ratio. Ps/Pn, excluding DC and first five harmonics (sometime first 9). SFDR: Spurious Free Dynamic Range. Ps/Ph (Ph is the highest spur). THD: Total Harmonic Distortion. Ps/Pd (Pd is the power of the first five (or 9) harmonics) SINAD: SIgnal to Noise And Distortion (SNR T for ADC). Ps/(Pn+Pd) (no DC) Can be specified in dbc(db to carrier, reference is the fundamental), or dbfs(db to full scale, fundamental extrapolated to full-scale). 04/05/2016-4 ATLCE - D6-2012 DDC 2012 DDC 4

Aliasing: Spectrum folding 04/05/2016-5 ATLCE - D6-2012 DDC 2012 DDC 5

Folding of harmonics SFDR Fundamental Largest spurious (Ph) Folded harmonics spurious Harm 2 Harm 3 Harm 6 04/05/2016-6 ATLCE - D6-2012 DDC 2012 DDC 6

Spectral view of ADC parameters 04/05/2016-7 ATLCE - D6-2012 DDC 2012 DDC 7

Spectral view of SFDR Fundamental 3 H2 3 4 5 6 Fs/2 Fs SFDR Fundamental Largest spurious Folded harmonics Spurious Harm 2 Harm 3 Harm 6 04/05/2016-8 ATLCE - D6-2012 DDC 2012 DDC 8

Oversampling Sampling at a rate far higher than the Nyquist limit Example: 3 khz audio signal (Nyquist = 6 ks/s) 8 ks/s Nyquist sampling; 1 MS/s Oversampling Oversampling sends aliased spectra far from baseband Reduced aliasing noise, folded from first alias Relaxed specifications on the anti-alias input filter Quantization noise is spread over a wider band (0 - Fs) Reduced spectral density of quantization noise Higher bit rate (more samples/s) Can be reduced with digital filtering Move complexity from analog digital domain 04/05/2016-9 ATLCE - D6-2012 DDC 2012 DDC 9

Oversampling vs. Nyquist Nyquist Main spectrum (baseband) First alias Second alias X(ω) f 0 F S1 2F S1 Quantization noise (0-Fs1 band) Oversampling X(ω) First alias f 0 Quantization noise (0-Fs2 band) F S2 04/05/2016-10 ATLCE - D6-2012 DDC 2012 DDC 10

Oversampling vs. Nyquist filtering Nyquist X(ω) Steep filter f Oversampling F S1 0 2F S1 Different filters: same quantization noise power (after reconstruction filter) X(ω) Smooth filter 0 F S2 f 04/05/2016-11 ATLCE - D6-2012 DDC 2012 DDC 11

Oversampling vs. Nyquist noise Nyquist X(ω) Steep filter f F S1 0 2F S1 Oversampling X(ω) Steep filter Same filter: reduced quantization noise power (after reconstruction filter) Removed quantization noise 0 F S2 f 04/05/2016-12 ATLCE - D6-2012 DDC 2012 DDC 12

Which is the actual limit? Actual Nyquist rule: A signal must be sampled at least twice the signal BANDWIDTH Example: a 1 GHz carrier, 100 khz BW signal can be safely sampled at Fs > 200 ks/s Spectrum is folded around K Fs/2 Less stringent specs for RF A/D converters Sampling rate related with bandwidth, not carrier Tight specs for the S/H sampling jitter related with carrier, not bandwidth 04/05/2016-13 ATLCE - D6-2012 DDC 2012 DDC 13

Filter for Nyquist sampling NYQUIST X(ω) Steep antialias filter, to limit aliasing noise Spectrum segment folded to baseband (aliasing noise) f F S 0 2F S F S /2 A/D Complex analog LP filter 04/05/2016-14 ATLCE - D6-2012 DDC 2012 DDC 14

Oversampling: more simple filter Complex, steep digital filter: - reduce noise - reduce bit rate (decimation) Alias is far away; antialias analog filter can be simple X( ) f 0 F S2 04/05/2016-15 ATLCE - D6-2012 DDC 2012 DDC 15

Filters with oversampling NYQUIST Complex analog LP filter A/D OVERSAMPLING Simple analog filter A/D Move complexity from the analog to the digital domain Complex digital filter Can reduce the bit rate (decimation) 04/05/2016-16 ATLCE - D6-2012 DDC 2012 DDC 16

Oversampling: noise shaping Oversampling X(ω) Reconstruction filter Flat quantization noise 0 F S2 f Noise shaping X(ω) Shaped quantization noise 0 In ΣΔ ADC noise power is moved to HF, with lower power density in baseband F S2 f 04/05/2016-17 ATLCE - D6-2012 DDC 2012 DDC 17

Standard sampling Sample at (at least) 2 x signal frequency Keeps aliases out of useful band Standard technique: signal rebuilt with low-pass filter 04/05/2016-18 ATLCE - D6-2012 DDC 2012 DDC 18

Undersampling Sample at 2 x signal bandwidth (can be far less than signal frequency) Aliases arise, but out of useful band Signal can be rebuilt with bandpass filter; no informatin loss 04/05/2016-19 ATLCE - D6-2012 DDC 2012 DDC 19

Undersampling - correct 04/05/2016-20 ATLCE - D6-2012 DDC 2012 DDC 20

Undersampling not correct 04/05/2016-21 ATLCE - D6-2012 DDC 2012 DDC 21

ADC example 04/05/2016-22 ATLCE - D6-2012 DDC 2012 DDC 22

Block diagram 04/05/2016-23 ATLCE - D6-2012 DDC 2012 DDC 23

Electrical characteristic 04/05/2016-24 ATLCE - D6-2012 DDC 2012 DDC 24

Output signal spectrum Sampling rate 500 Ms/s (MSPS) SFDR 04/05/2016-25 ATLCE - D6-2012 DDC 2012 DDC 25

Undersampling Sampling: 500 Ms/s < Nyquist In-band Alias (500-300) 04/05/2016-26 ATLCE - D6-2012 DDC 2012 DDC 26

Intermodulation Input signal: Fin1: 65,1 MHz Fin2: 70,1 MHz Sideband at 65,1 5 70,1 + 5 Higher sideband at 65,1 10 70,1 + 10 04/05/2016-27 ATLCE - D6-2012 DDC 2012 DDC 27

Differential and integral nonlinearity 04/05/2016-28 ATLCE - D6-2012 DDC 2012 DDC 28

Spurious Free Dynamic Range dbfullscale: error referred to full scale (SNR independent from signal level) dbcarrier: error referred to carrier (SNR depends on signal level) 04/05/2016-29 ATLCE - D6-2012 DDC 2012 DDC 29

Clock jitter High speed ADC need precise sampling low clock jitter differential clock Effect of clock jitter: SNRj = -20 log 10 2π Fin Tj 04/05/2016-30 ATLCE - D6-2012 DDC 2012 DDC 30

Aperture jitter specification 04/05/2016-31 ATLCE - D6-2012 DDC 2012 DDC 31

Interleaving ADCs 04/05/2016-32 ATLCE - D6-2012 DDC 2012 DDC 32

Spectrum folding with interleaved ADC 04/05/2016-33 ATLCE - D6-2012 DDC 2012 DDC 33

Averaging ADCs 04/05/2016-34 ATLCE - D6-2012 DDC 2012 DDC 34

Averaging ADC benefits 04/05/2016-35 ATLCE - D6-2012 DDC 2012 DDC 35

Dithering 04/05/2016-36 ATLCE - D6-2012 DDC 2012 DDC 36

Adding sampling jitter (dither) 04/05/2016-37 ATLCE - D6-2012 DDC 2012 DDC 37

Dither effect 04/05/2016-38 ATLCE - D6-2012 DDC 2012 DDC 38

Lesson D6 final test Describe the limits of undersampling techniques. Plot spectrum of undersampled sinewave, with no distortion and with some distortion. Which parameters contribute to total sampling jitter? Describe the interleaving ADC technique and related benefits. Describe the averaging ADC technique and related benefits. Why dithering can improve ADC performance? 04/05/2016-39 ATLCE - D6-2012 DDC 2012 DDC 39