30V N-Channel Enhancement Mode MOSFET DESCRIPTION The UP8404 is the N-Channel logic enhancement mode power field effect transistor is produced using high cell density advanced trench technology.. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application, and low in-line power loss are needed in a very small outline surface mount package. FEATURE 30V/5.7A, RDS(ON)=19mΩ (typ.)@vgs=10v 30V/5.0A, RDS(ON)=25mΩ (typ.)@vgs=4.5v Super high design for extremely low RDS(ON) Exceptional on-resistance and Maximum DC current capability Full RoHS compliance SOT23 package design APPLICATIONS Power Management Portable Equipment DC/DC Converter Load Switch DSC LCD Display inverter PIN CONFIGURATION Copyright UNIVERSALPARTS(HK)CO.,LTD 1 / 8 www.uphks.com
PART NUMBER INFORMATION UP8404AA-BB C A= Package Code S: SOT BB=Handing Code TR: Tape&Reel C=Lead Plating Code G: Green Product ORDERING INFROMATION Part Number Package Code Package Shipping UP8404AS-TRG S SOT 3000EA / T&R Year Code : 0~9 Week Code : A~Z(1-26); a~z(27~52) G : Green Product. This product is RoHS compliant. ABSOLUTE MAXIMUM RATINGS ( TA = 25 Unless otherwise noted ) Symbol Parameter Typical Unit VDSS Drain-Source Voltage 30 V VGSS Gate-Source Voltage ±20 V ID Continuous Drain Current (TJ=150 ) VGS=10V 5.8 A IDM Pulsed Drain Current 64 A IS Continuous Source Current (Diode Conduction) 1.7 A PD Power Dissipation TA=25 1.40 W TA=70 0.9 TJ Operation Junction Temperature 150 TSTG Storage Temperature Range -55~+150 RθJA Thermal Resistance Junction to Ambient 90 /W Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress rating only and functional device operation is not implied Copyright UNIVERSALPARTS(HK)CO.,LTD 2 / 8 www.uphks.com
ELECTRICAL CHARACTERISTICS(TA=25 Unless otherwise noted) Symbol Parameter Condition Min Typ Max Unit Static Parameters V(BR)DSS Drain-Source Breakdown Voltage VGS=0V, ID=250uA 20 V VGS(th) Gate Threshold Voltage VDS=VGS, ID=250uA 1.3 2.5 V IGSS Gate Leakage Current VDS=0V, VGS=±20V ±100 na VDS=24V, VGS=0-1 IDSS Zero Gate Voltage Drain Current VDS=24V, VGS=0 ua -30 TJ=55 VGS=10V, ID=5.7A 19 25 RDS(ON) Drain-Source On-Resistance VGS=4.5V, ID=5.0A 25 35 mω Source-Drain Diode VSD Diode Forward Voltage IS=-1.0A, VGS=0V 0.7 1.0 V Dynamic Parameters Qg Total Gate Charge VDS=15V 10 19 Qgs Gate-Source Charge VGS=10V 1.7 nc Qgd Gate-Drain Charge ID=5.6A 3.2 Ciss Input Capacitance VDS=15V 416 Coss Output Capacitance VGS=0V 62 pf Crss Reverse Transfer Capacitance f=1mhz 40 VDS=15V 7 15 Turn-On Time Tr RL=10Ω 10 20 Td(on) ID=-1A 20 40 Tf Turn-Off Time VGEN=10V RG=6Ω 11 20 Td(off) Note: 1. Pulse test: pulse width<=300us, duty cycle<=2% 2.Static parameters are based on package level with recommended wire bonding ns Copyright UNIVERSALPARTS(HK)CO.,LTD 3 / 8 www.uphks.com
SOT23 PACKAGE OUTLINE DIMENSIONS Copyright UNIVERSALPARTS(HK)CO.,LTD 4 / 8 www.uphks.com
SOLDERING METHODS FOR UNIVERCHIP Storage environment Temperature=10 ~35 Humidity=65%±15% Reflow soldering of surface mount device Profile Feature Sn-Pb Eutectic Assembly Pb free Assembly Average ramp-up rate (TL to TP) <3 /sec <3 /sec Preheat -Temperature Min (Tsmin) -Temperature Max (Tsmax) -Time (min to max) (ts) 100 150 60~120 sec 150 200 60~180 sec Tsmax to TL <3 /sec <3 /sec -Ramp-up Rate Time maintained above -Temperature (TL) -Time (tl) 183 60~150 sec 217 60~150 sec Peak Temperature (TP) 240 +0/-5 260 +0/-5 Time within 5 of actual Peak 10~30 sec 20~40 sec Temperature (tp) Ramp-down Rate <6 /sec <6 /sec Time 25 to Peak Temperature <6 minutes <6 minutes Copyright UNIVERSALPARTS(HK)CO.,LTD 5 / 8 www.uphks.com
Flow (wave) soldering (solder dipping) Product Peak Temperature Dipping Time Pb device 245 ±5 5sec±1sec Pb-Free device 260 +0/-5 5sec±1sec This integrated circuit can be damaged by ESD UniverChip Corporation recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedure can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Copyright UNIVERSALPARTS(HK)CO.,LTD 6 / 8 www.uphks.com