Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted from Hennessy & Patterson / 2003 Elsevier

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Transcription:

Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted from Hennessy & Patterson / 2003 Elsevier Science

!!! Basic MIPS integer pipeline Branches with one delay cycle Functional units are fully pipelined or replicated (as many times as the pipeline depth)! An operation of any type can be issued on every clock cycle and there are no structural hazard Instruction producing result Instruction using results Latency in clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store Double 2 Load Double FP ALU op 1 Load Double Store Double 0

! Determining how one instruction depends on another is critical not only to the scheduling process but also to determining how much parallelism exists! If two instructions are parallel they can execute simultaneously in the pipeline without causing stalls (assuming there is not structural hazard)! Two instructions that are dependent are not parallel and their execution cannot be reordered

! Data dependence (RAW)! Transitive: i! j! k = i! k! Easy to determine for registers, hard for memory! Does 100(R4) = 20(R6)?! From different loop iterations, does 20(R6) = 20(R6)?! Name dependence (register/memory reuse)! Anti-dependence (WAR): Instruction j writes a register or memory location that instruction i reads from and instruction i is executed first! Output dependence (WAW): Instructions i and j write the same register or memory location; instruction ordering must be preserved! Control dependence, caused by conditional branching

Loop:!LD!F0,x(R1)!!ADDD!F4,F0,F2!!SD!x(R1),F4!!LD!F0,x-8(R1)!!ADDD!F4,F0,F2!!SD!x-8(R1),F4!!LD!F0,x-16(R1)!!ADDD!F4,F0,F2!!SD!x-16(R1),F4!!LD!F0,x-24(R1)!!ADDD!F4,F0,F2!!SD!x-24(R1),F4!!SUBI!R1,R1,#32!!BNEZ!R1,Loop! Register renaming Loop:!LD!F0,x(R1)!!ADDD!F4,F0,F2!!SD!x(R1),F4!!LD!F6,x-8(R1)!!ADDD!F8,F6,F2!!SD!x-8(R1),F8!!LD!F10,x-16(R1)!!ADDD!F12,F10,F2!!SD!x-16(R1),F12!!LD!F14,x-24(R1)!!ADDD!F16,F14,F2!!SD!x-24(R1),F16!!SUBI!R1,R1,#32!!BNEZ!R1,Loop!! Again Name Dependencies are Hard for Memory Accesses!Does 100(R4) = 20(R6)?!From different loop iterations, does 20(R6) = 20(R6)?! Compiler needs to know that R1 does not change! 0(R1)! -8(R1)! -16(R1)! -24(R1) and thus no dependencies between some loads and stores so they could be moved

! Why in HW at run time?! Works when can t know real dependence at compile time! Compiler simpler! Code for one machine runs well on another! Key idea: Allow instructions behind stall to proceed DIVD F0,F2,F4 ADDD F10,F0,F8 SUBD F12,F8,F14! Enables out-of-order execution => out-of-order completion! ID stage checks for structural and data hazards

! Out-of-order execution divides ID stage: 1.! Issue decode instructions, check for structural hazards 2.! Read operands wait until no data hazards, then read operands! Scoreboards allow instruction to execute whenever 1 & 2 hold, not waiting for prior instructions! CDC 6600: In order issue, out of order execution, out of order commit / completion

! Out-of-order completion! WAR, WAW hazards Example: DIVID F0, F2, F4 ADDD F10, F0, F8 SUBD F8, F8, F8! Solutions for WAR! Queue both the operation and copies of its operands! Read registers only during Read Operands stage! For WAW, must detect hazard: stall until other completes! Scoreboard keeps track of dependencies, state or operations! Replace ID, EX, WB with 4 stages

1.! Issue decode instructions & check for structural hazards (ID1).! If a functional unit for the instruction is free and no other active instruction has the same destination register (WAW), the scoreboard issues the instruction to the functional unit and updates its internal data structure.! If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared. 2.! Read operands wait until no data hazards, then read operands (ID2).! A source operand is available if no earlier issued active instruction is going to write it, or if the register containing the operand is being written by a currently active functional unit.! When the source operands are available, the scoreboard tells the functional unit to proceed to read the operands from the registers and begin execution.! The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order. 3.! Execution operate on operands (EX)! The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. 4.! Write result finish execution (WB)! Once the scoreboard is aware that the functional unit has completed execution, the scoreboard checks for WAR hazards. If none, it writes results, otherwise it stalls

MIPS Processor with Scoreboard! Given the small latency of integer operations, it is not worth the scoreboard complexity! 2 Multiplier, 1 divider, 1 adder and one integer unit! Major cost driven by data buses! The scoreboard control function units! The scoreboard enables out-of-order execution to maximize parallelism

1.! Instruction status which of 4 steps for instruction 2.! Functional unit status Indicates the state of the functional unit (FU). 9 fields for each functional unit! Busy Indicates whether the unit is busy or not! Op Operation to perform in the unit (e.g., + or )! Fi Destination register! Fj, Fk Source-register numbers! Qj, Qk Functional units producing source registers Fj, Fk! Rj, Rk Flags indicating when Fj, Fk are ready 3.! Indicates which functional unit will write each register, if any. Blank when no pending instructions will write that register

! Speedup 1.7 from compiler; 2.5 by hand BUT slow memory (no cache)! Limitations of 6600 scoreboard:!no forwarding hardware!limited to instructions in basic block (small window)!small number of functional units (causes structural hazards)!do not issue on structural hazards!wait for WAR hazards and prevent WAW hazards

LD F6 34+ R2 LD F2 45+ R3 MULT F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer No Mult1 No Add No Divide No FU

LD F6 34+ R2 1 LD F2 45+ R3 MULT F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 No Add No Divide No 1 FU Integer

LD F6 34+ R2 1 2 LD F2 45+ R3 MULT F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 No Add No Divide No 2 FU Integer! Issue 2nd LD?

LD F6 34+ R2 1 2 3 LD F2 45+ R3 MULT F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 No Add No Divide No 3 FU Integer

LD F2 45+ R3 MULT F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 No Add No Divide No 4 FU Integer

LD F2 45+ R3 5 MULT F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 No Add No Divide No 5 FU Integer

LD F2 45+ R3 5 6 MULT F0 F2 F4 6 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer No Yes Add No Divide No 6 FU Mult1 Integer

LD F2 45+ R3 5 6 7 MULT F0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer No Yes Add Yes Sub F8 F6 F2 Integer Yes No Divide No 7 FU Mult1 Integer Add! Read multiply operands?

LD F2 45+ R3 5 6 7 MULT F0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer No Yes Add Yes Sub F8 F6 F2 Integer Yes No Divide Yes Div F10 F0 F6 Mult1 No Yes 8 FU Mult1 Integer Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer No Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 8 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer No 10 Mult1 Yes Mult F0 F2 F4 Yes Yes 2 Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 9 FU Mult1 Add Divide! Read operands for MULT & SUBD?! Issue ADDD?

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer No 8 Mult1 Yes Mult F0 F2 F4 Yes Yes 0 Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 11 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer No 7 Mult1 Yes Mult F0 F2 F4 Yes Yes Add No Divide Yes Div F10 F0 F6 Mult1 No Yes 12 FU Mult1 Divide! Read operands for DIVD?

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 Integer No 6 Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 13 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 14 Integer No 5 Mult1 Yes Mult F0 F2 F4 Yes Yes 2 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 14 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 14 Integer No 4 Mult1 Yes Mult F0 F2 F4 Yes Yes 1 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 15 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 14 16 Integer No 3 Mult1 Yes Mult F0 F2 F4 Yes Yes 0 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 16 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 14 16 Integer No 2 Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 17 FU Mult1 Add Divide! Write result of ADDD?

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 14 16 Integer No 1 Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 18 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 19 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 14 16 Integer No 0 Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 19 FU Mult1 Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 19 20 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 14 16 Integer No Mult1 No Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Yes Yes 20 FU Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 19 20 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 21 ADDD F6 F8 F2 13 14 16 Integer No Mult1 No Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Yes Yes 21 FU Add Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 19 20 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 21 ADDD F6 F8 F2 13 14 16 22 Integer No Mult1 No Add No 40 Divide Yes Div F10 F0 F6 Yes Yes 22 FU Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 19 20 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 21 61 ADDD F6 F8 F2 13 14 16 22 Integer No Mult1 No Add No 0 Divide Yes Div F10 F0 F6 Yes Yes 61 FU Divide

LD F2 45+ R3 5 6 7 8 MULT F0 F2 F4 6 9 19 20 SUBD F8 F6 F2 7 9 11 12 DIVD F10 F0 F6 8 21 61 62 ADDD F6 F8 F2 13 14 16 22 Integer No Mult1 No Add No 0 Divide No 62 FU

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