EECS 470 Lecture 8. P6 µarchitecture. Fall 2018 Jon Beaumont Core 2 Microarchitecture

Transcription

1 P6 µarchitecture Fall 2018 Jon Beaumont Core 2 Microarchitecture Many thanks to Prof. Martin and Roth of University of Pennsylvania for most of these slides. Portions developed in part by Profs. Austin, Brehob, Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, yson, Vijaykumar, and Wenisch of Carnegie Mellon University, Purdue University, University of Michigan, and University of Wisconsin. Slide 1

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3 HW # 2 due yesterday Announcements Verilog assignment #3 due next uesday (10/9) Get moving!! Lab #4 due hursday Project handout today Finalize groups Proposal due next Wednesday (10/10) Slide 3

4 Last ime Finished omasulo s Algorithm case study alked about precise state, interrupts and exceptions Slide 4

5 How to ensure precise state? oday P6 case study Slide 5

6 Precise Interrupts Sequential Code Semantics Overlapped Execution i1: xxxx i1 i2: xxxx i2 i1: i2: i3: i3: xxxx i3 Precise interrupt appears to happen between two instructions Lecture 7 Slide 6

7 Speculation and Precise Interrupts Why are we discussing these together? Sequential (vn) semantics for interrupts All insns before interrupt should be complete All insns after interrupt should look as if never started (abort) Basically want same thing for mis-predicted branch What makes precise interrupts difficult? OoO completion must undo post-interrupt writebacks Same thing for branches In-order branches complete before younger insns writeback OoO not necessarily Precise interrupts, mis-speculation recovery: same problem Same problem same solution Lecture 7 Slide 7

8 Speculative execution requires Precise State (Ability to) abort & restart at every branch Abort & restart at every load useful for load speculation (later) And for shared memory multiprocessing (much later) Precise synchronous (program-internal) interrupts require Abort & restart at every load, store,?? Precise asynchronous (external) interrupts require Abort & restart at every?? Bite the bullet Implement abort & restart at every insn Called precise state Lecture 7 Slide 8

9 Precise State Options Imprecise state: ignore the problem! Makes page faults (any restartable exceptions) difficult Makes speculative execution almost impossible IEEE standard strongly suggests precise state Compromise: Alpha implemented precise state only for integer ops Force in-order completion (W): stall pipe if necessary Slow Precise state in software: trap to recovery routine Implementation dependent rap on every mis-predicted branch (you must be joking) Precise state in hardware + Everything is better in hardware (except policy) Lecture 7 Slide 9

10 he Problem with Precise State insn buffer regfile I$ B P D S D$ Problem: writeback combines two separate functions Forwards values to younger insns: OK for this to be out-of-order Write values to registers: would like this to be in-order Similar problem (decode) for OoO execution: solution? Split decode (D) in-order dispatch (D) + out-of-order issue (S) Separate using insn buffer: scoreboard or reservation station Lecture 7 Slide 10

11 Re-Order Buffer () Reorder buffer () regfile I$ B P D$ W1 W2 Insn buffer re-order buffer () Buffers completed results en route to register file May be combined with RS or separate Combined in picture: register-update unit RUU (Sohi s method) Separate (more common today): P6-style Split writeback (W) into two stages Why is there no latch between W1 and W2? Lecture 7 Slide 11

12 Complete and Retire Reorder buffer () regfile I$ B P D$ C R Complete (C): Completed insns write results into + Out-of-order: wait doesn t back-propagate to younger insns Retire (R): aka commit, graduate writes results to register file In order: stall back-propagates to younger insns Lecture 7 Slide 12

13 Load/Store Queue (LSQ) makes register writes in-order, but what about stores? As usual, i.e., to D$ in X stage? Not even close, imprecise memory worse than imprecise registers Load/store queue (LSQ) Completed stores write to LSQ When store retires, head of LSQ written to D$ When loads execute, access LSQ and D$ in parallel Forward from LSQ if older store with matching address More modern design: loads and stores in separate queues More on this later Lecture 7 Slide 13

14 + LSQ regfile I$ B P C R load/store store data LSQ load data addr D$ Modulo gross simplifications, this picture is almost realistic! Lecture 7 Slide 14

15 P6 P6: Start with omasulo s algorithm add Separate and RS Simple-P6 Our old RS organization: 1 ALU, 1 load, 1 store, 2 3-cycle FP Lecture 7 Slide 15

16 P6 Data Structures Reservation Stations are same as before head, tail: pointers maintain sequential order R: insn output register, V: insn output value ags are different omasulo: RS# P6: # Map able is different +: tag + ready-in- bit ==0 Value is ready in regfile!=0 Value is not ready!=0+ Value is ready in the Lecture 7 Slide 16

17 CDB. CDB.V P6 Data Structures Map able + Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch Insn fields and status bits ags Values Lecture 7 Slide 17

18 P6 Data Structures ht # Insn R V S X C 1 ldf X(r1),f1 2 mulf f0,f1,f2 3 stf f2,z(r1) 4 addi r1,4,r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S no 4 FP1 no 5 FP2 no Lecture 7 Slide 18

19 P6 Pipeline New pipeline structure: F, D, S, X, C, R D (dispatch) Structural hazard (/LSQ/RS)? Stall Allocate /LSQ/RS Set RS tag to # Set Map able entry to # and clear ready-in- bit Read ready registers into RS (from either or Regfile) X (execute) Free RS entry Use to be at W, can be earlier because RS# are not tags Lecture 7 Slide 19

20 P6 Pipeline C (complete) Structural hazard (CDB)? wait Write value into entry indicated by RS tag Mark entry as complete If not overwritten, mark Map able entry ready-in- bit (+) R (retire) Insn at head not complete? stall Handle any exceptions Write head value to register file If store, write LSQ head to D$ Free /LSQ entries Lecture 7 Slide 20

21 CDB. CDB.V P6 Dispatch (D): Part I Map able + Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch RS/ full? stall Allocate RS/ entries, assign # to RS output tag Set output register Map able entry to #, clear ready-in- Slide 21

22 CDB. CDB.V P6 Dispatch (D): Part II Map able + Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch Read tags for register inputs from Map able ag==0 copy value from Regfile (not shown) ag!=0 copy Map able tag to RS ag!=0+ copy value from Slide 22

23 CDB. CDB.V P6 Complete (C) Map able + Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch Structural hazard (CDB)? Stall : broadcast <value,tag> on CDB Write result into, if still valid clear Mapable ready-in- bit Match tags, write CDB.V into RS slots of dependent insns Slide 23

24 CDB. CDB.V P6 Retire (R) Map able Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch head not complete? stall : free entry Write head result to Regfile If still valid, clear Map able entry Slide 24

25 P6 Data Structures ht # Insn R V S X C 1 ldf X(r1),f1 2 mulf f0,f1,f2 3 stf f2,z(r1) 4 addi r1,4,r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S no 4 FP1 no 5 FP2 no Slide 25

26 P6: Cycle 1 ht # Insn R V S X C ht 1 ldf X(r1),f1 2 mulf f0,f1,f2 3 stf f2,z(r1) 4 addi r1,4,r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) f1 Map able Reg + f0 f1 f2 r1 #1 CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD yes ldf #1 [r1] 3 S no 4 FP1 no 5 FP2 no set # tag allocate Slide 26

27 P6: Cycle 2 ht # Insn R V S X C h 1 ldf X(r1),f1 f1 c2 t 2 mulf f0,f1,f2 f2 3 stf f2,z(r1) 4 addi r1,4,r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #1 #2 CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD yes ldf #1 [r1] 3 S no 4 FP1 yes mulf #2 #1 [f0] 5 FP2 no set # tag allocate Slide 27

28 P6: Cycle 3 ht # Insn R V S X C h 1 ldf X(r1),f1 f1 c2 c3 t 2 mulf f0,f1,f2 f2 3 stf f2,z(r1) 4 addi r1,4,r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #1 #2 CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S yes stf #3 #2 [r1] 4 FP1 yes mulf #2 #1 [f0] 5 FP2 no free allocate Slide 28

29 P6: Cycle 4 ht # Insn R V S X C h 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 c4 3 stf f2,z(r1) t 4 addi r1,4,r1 r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + Reservation Stations # FU busy op 1 2 V1 V2 1 ALU yes add #4 [r1] 2 LD no 3 S yes stf #3 #2 [r1] 4 FP1 yes mulf #2 #1 [f0] CDB.V 5 FP2 no f0 f1 f2 r1 CDB V #1 [f1] #1+ #2 #4 ldf finished 1. set ready-in- bit 2. write result to 3. CDB broadcast allocate #1 ready grab CDB.V Slide 29

30 P6: Cycle 5 ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 h 2 mulf f0,f1,f2 f2 c4 c5 3 stf f2,z(r1) 4 addi r1,4,r1 r1 c5 t 5 ldf X(r1),f1 f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #5 #2 #4 CDB V ldf retires 1. write result to regfile Reservation Stations # FU busy op 1 2 V1 V2 1 ALU yes add #4 [r1] 2 LD yes ldf #5 #4 3 S yes stf #3 #2 [r1] 4 FP1 no 5 FP2 no allocate free Slide 30

31 P6: Cycle 6 ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 h 2 mulf f0,f1,f2 f2 c4 c5+ 3 stf f2,z(r1) 4 addi r1,4,r1 r1 c5 c6 5 ldf X(r1),f1 f1 t 6 mulf f0,f1,f2 f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #5 #6 #4 CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD yes ldf #5 #4 3 S yes stf #3 #2 [r1] 4 FP1 yes mulf #6 #5 [f0] 5 FP2 no free allocate Slide 31

32 P6: Cycle 7 ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 h 2 mulf f0,f1,f2 f2 c4 c5+ 3 stf f2,z(r1) 4 addi r1,4,r1 r1 [r1] c5 c6 c7 5 ldf X(r1),f1 f1 c7 t 6 mulf f0,f1,f2 f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #5 #6 #4+ CDB stall D (no free S RS) V #4 [r1] Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD yes ldf #5 #4 CDB.V 3 S yes stf #3 #2 [r1] 4 FP1 yes mulf #6 #5 [f0] 5 FP2 no #4 ready grab CDB.V Slide 32

33 P6: Cycle 8 ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 h 2 mulf f0,f1,f2 f2 [f2] c4 c5+ c8 3 stf f2,z(r1) c8 4 addi r1,4,r1 r1 [r1] c5 c6 c7 5 ldf X(r1),f1 f1 c7 c8 t 6 mulf f0,f1,f2 f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S yes stf #3 #2 [f2] [r1] 4 FP1 yes mulf #6 #5 [f0] 5 FP2 no #5 #6 #4+ CDB V #2 [f2] stall R for addi (in-order) #2 invalid in Mapable don t set ready-in- #2 ready grab CDB.V Slide 33

34 P6: Cycle 9 ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 [f2] c4 c5+ c8 h 3 stf f2,z(r1) c8 c9 4 addi r1,4,r1 r1 [r1] c5 c6 c7 5 ldf X(r1),f1 f1 [f1] c7 c8 c9 t 6 mulf f0,f1,f2 f2 c9 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 retire mulf #5+ #6 #4+ CDB V #5 [f1] all pipe stages active at once! Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S yes stf #7 #6 #4.V 4 FP1 yes mulf #6 #5 [f0] CDB.V 5 FP2 no free, re-allocate #5 ready grab CDB.V Slide 34

35 P6: Cycle 10 ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 [f2] c4 c5+ c8 h 3 stf f2,z(r1) c8 c9 c10 4 addi r1,4,r1 r1 [r1] c5 c6 c7 5 ldf X(r1),f1 f1 [f1] c7 c8 c9 t 6 mulf f0,f1,f2 f2 c9 c10 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #5+ #6 #4+ CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S yes stf #7 #6 #4.V 4 FP1 no 5 FP2 no free Slide 35

36 P6: Cycle 11 ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 [f2] c4 c5 c8 3 stf f2,z(r1) c8 c9 c10 h 4 addi r1,4,r1 r1 [r1] c5 c6 c7 5 ldf X(r1),f1 f1 [f1] c7 c8 c9 t 6 mulf f0,f1,f2 f2 c9 c10 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 retire stf #5+ #6 #4+ CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S yes stf #7 #6 #4.V 4 FP1 no 5 FP2 no Slide 36

37 Precise State in P6 Point of is maintaining precise state How does that work? Easy as 1,2,3 1. Wait until last good insn retires, first bad insn at head 2. Clear contents of, RS, and Map able 3. Start over Works because zero (0) means the right thing 0 in /RS entry is empty ag == 0 in Map able register is in regfile and because regfile and D$ writes take place at R Example: page fault in first stf Slide 37

38 P6: Cycle 9 (with precise state) ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 [f2] c4 c5+ c8 h 3 stf f2,z(r1) c8 c9 4 addi r1,4,r1 r1 [r1] c5 c6 c7 5 ldf X(r1),f1 f1 [f1] c7 c8 c9 t 6 mulf f0,f1,f2 f2 c9 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #5+ #6 #4+ CDB PAGE FAUL V #5 [f1] Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S yes stf #7 #6 #4.V 4 FP1 yes mulf #6 #5 [f0] CDB.V 5 FP2 no Slide 38

39 P6: Cycle 10 (with precise state) ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 [f2] c4 c5+ c8 3 stf f2,z(r1) 4 addi r1,4,r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 CDB V faulting insn at head? CLEAR EVERYHING Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S no 4 FP1 no 5 FP2 no Slide 39

40 P6: Cycle 11 (with precise state) ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 [f2] c4 c5+ c8 ht 3 stf f2,z(r1) 4 addi r1,4,r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 CDB V SAR OVER (after OS fixes page fault) Reservation Stations # FU busy op 1 2 V1 V2 1 ALU no 2 LD no 3 S yes stf #3 [f4] [r1] 4 FP1 no 5 FP2 no Slide 40

41 P6: Cycle 12 (with precise state) ht # Insn R V S X C 1 ldf X(r1),f1 f1 [f1] c2 c3 c4 2 mulf f0,f1,f2 f2 [f2] c4 c5+ c8 h 3 stf f2,z(r1) c12 t 4 addi r1,4,r1 r1 5 ldf X(r1),f1 6 mulf f0,f1,f2 7 stf f2,z(r1) Map able Reg + f0 f1 f2 r1 #4 CDB V Reservation Stations # FU busy op 1 2 V1 V2 1 ALU yes addi #4 [r1] 2 LD no 3 S yes stf #3 [f4] [r1] 4 FP1 no 5 FP2 no Slide 41

42 P6 Performance In other words: what is the cost of precise state? + In general: same performance as plain omasulo is not a performance device Maybe a little better (RS freed earlier fewer struct hazards) Unless is too small In which case struct hazards become a problem Rules of thumb for size At least N (width) * number of pipe stages between D and R At least N * t hit-l2 Can add a factor of 2 to both if you want What is the rationale behind these? Slide 42

43 P6 (omasulo+) Redux Popular design for a while (Relatively) easy to implement correctly Anything goes wrong (mispredicted branch, fault, interrupt)? Just clear everything and start again Examples: Intel PentiumPro, IBM/Motorola PowerPC, AMD K6 Actually making a comeback Examples: Intel PentiumM But went away for a while, why? Slide 43

44 CDB. CDB.V he Problem with P6 Map able + Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch Problem for high performance implementations oo much value movement (regfile/ RS regfile) Multi-input muxes, long buses complicate routing and slow clock Slide 44