EN164: Design of Computing Systems Lecture 22: Processor / ILP 3

Transcription

1 EN164: Design of Computing Systems Lecture 22: Processor / ILP 3 Professor Sherief Reda Electrical Sciences and Computer Engineering School of Engineering Brown University Spring 2011 S. Reda EN164 Sp 11 [ material from Patterson & Hennessy, 4 th ed] 1

2 Difference between superscalar and VLIW [from Fisher et al.] S. Reda EN164 Sp 11 2

3 Dynamic superscalar CPU decides whether to issue 0, 1, 2, each cycle Avoiding structural and data hazards Avoids the need for compiler scheduling Though it may still help Code semantics ensured by the CPU need to re-compile existing code Dynamic scheduling require dedicate HW unit for book keeping: Scoreboarding Tomasulo s algorithm S. Reda EN164 Sp 11 3

4 Extending MIPS pipeline with multiple EX units S. Reda EN164 Sp 11 4

5 Ramifications of deep pipelines Large stall penalties for RAW hazards Increased stalls from: Structural: more than one register write per cycle WAR/WAW hazards because different instructions take different number of cycles S. Reda EN164 Sp 11 5

6 Bookkeeping using scoreboarding Named after the CDC 6600 scoreboard. Used to orchestrate parallel instruction execution among functional units We will illustrate the technique using a simpler RISC machine Scoreboard: Keeps track of instruction and machine status, permitting the instruction to execute as soon as its operands are available Instructions can execute out-of-order Implications: WAW hazard: Detect and stall issue WAR hazard: Detect before writing back to the register files and stall Scoreboard does not take advantage of forwarding, since it waits until results are written back to the register file S. Reda EN164 Sp 11 6

7 Scoreboard with simple RISC architecture 10 cycles Registers FP Mult FP Mult 40 cycles FP Divide 2 cycles FP Add 1 cycles Integer Functional Units SCOREBOARD Memory S. Reda EN164 Sp 11 7

8 Four stages of scoreboard control Issue (ID1) decode instructions check for structural and WAW hazards stall until structural and WAW hazards are resolved Read operands (ID2) wait until no RAW hazards then read operands Execution (EX) operate on operands may be multiple cycles - notify scoreboard when done Write result (WB) finish execution stall if WAR hazard S. Reda EN164 Sp 11 8

9 Three parts of scoreboard Which of 4 steps the instruction is in Functional unit status: Indicates the state of the functional unit (FU). 9 fields for each functional unit Busy: Indicates whether the unit is busy or not Op: Operation to perform in the unit (e.g., + or ) Fi: Destination register Fj,Fk: Source-register numbers Qj,Qk: Functional units producing source registers Fj, Fk Rj,Rk: Flags indicating when Fj, Fk are ready Register result status Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register S. Reda EN164 Sp 11 9

10 Scoreboard LD F6 34+ R2 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Mult1 Mult2 Add Divide FU S. Reda EN164 Sp 11 10

11 Cycle 1 LD F6 34+ R2 1 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 Add Divide 1 FU Integer S. Reda EN164 Sp 11 11

12 Cycle 2 LD F6 34+ R2 1 2 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Yes Mult1 Add Divide 2 FU Integer Issue 2nd LD? S. Reda EN164 Sp 11 12

13 Cycle 3 LD F6 34+ R LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F6 R2 Mult1 Add Divide 3 FU Integer Issue MULT? S. Reda EN164 Sp 11 13

14 Cycle 4 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Mult1 Mult2 Add Divide 4 FU Integer S. Reda EN164 Sp 11 14

15 Cycle 5 LD F2 45+ R3 5 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Add Divide 5 FU Integer S. Reda EN164 Sp 11 15

16 Cycle 6 LD F2 45+ R3 5 6 MULTD F0 F2 F4 6 SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer Yes Add Divide 6 FU Mult1 Integer S. Reda EN164 Sp 11 16

17 Cycle 7 LD F2 45+ R MULTD F0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 ADDD F6 F8 F2 Integer Yes Load F2 R3 Mult1 Yes Mult F0 F2 F4 Integer Yes Add Yes Sub F8 F6 F2 Integer Yes Divide 7 FU Mult1 Integer Add Read multiply operands? S. Reda EN164 Sp 11 17

18 Cycle 8 LD F2 45+ R MULTD F0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 8 FU Mult1 Add Divide S. Reda EN164 Sp 11 18

19 Cycle 9 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 DIVD F10 F0 F6 8 ADDD F6 F8 F2 te Remaining Integer 10 Mult1 Yes Mult F0 F2 F4 Yes Yes 2 Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 9 FU Mult1 Add Divide Read operands for MULT & SUB? Issue ADDD? S. Reda EN164 Sp 11 19

20 Cycle 10 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F2 7 9 DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer 9 Mult1 Yes Mult F0 F2 F4 1 Add Yes Sub F8 F6 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 10 FU Mult1 Add Divide S. Reda EN164 Sp 11 20

21 Cycle 11 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer 8 Mult1 Yes Mult F0 F2 F4 0 Add Yes Sub F8 F6 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 11 FU Mult1 Add Divide S. Reda EN164 Sp 11 21

22 Cycle 12 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F2 Integer 7 Mult1 Yes Mult F0 F2 F4 Add Divide Yes Div F10 F0 F6 Mult1 Yes 12 FU Mult1 Divide Read operands for DIVD? S. Reda EN164 Sp 11 22

23 Cycle 13 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F2 13 Integer 6 Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 13 FU Mult1 Add Divide S. Reda EN164 Sp 11 23

24 Cycle 14 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 5 Mult1 Yes Mult F0 F2 F4 2 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 14 FU Mult1 Add Divide S. Reda EN164 Sp 11 24

25 Cycle 15 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 4 Mult1 Yes Mult F0 F2 F4 1 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 15 FU Mult1 Add Divide S. Reda EN164 Sp 11 25

26 Cycle 16 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 3 Mult1 Yes Mult F0 F2 F4 0 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 16 FU Mult1 Add Divide S. Reda EN164 Sp 11 26

27 Cycle 17 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F WAR Hazard! Integer 2 Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 17 FU Mult1 Add Divide Why not write result of ADD??? S. Reda EN164 Sp 11 27

28 Cycle 18 LD F2 45+ R MULTD F0 F2 F4 6 9 SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 1 Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 18 FU Mult1 Add Divide S. Reda EN164 Sp 11 28

29 Cycle 19 LD F2 45+ R MULTD F0 F2 F SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer 0 Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 19 FU Mult1 Add Divide S. Reda EN164 Sp 11 29

30 Cycle 20 LD F2 45+ R MULTD F0 F2 F SUBD F8 F6 F DIVD F10 F0 F6 8 ADDD F6 F8 F Integer Mult1 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Yes Yes 20 FU Add Divide S. Reda EN164 Sp 11 30

31 Cycle 21 LD F2 45+ R MULTD F0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Yes Yes 21 FU Add Divide WAR Hazard is now gone... S. Reda EN164 Sp 11 31

32 Cycle 22 LD F2 45+ R MULTD F0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Add 40 Divide Yes Div F10 F0 F6 22 FU Divide S. Reda EN164 Sp 11 32

33 . Cycle 61 LD F2 45+ R MULTD F0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Add 0 Divide Yes Div F10 F0 F6 61 FU Divide S. Reda EN164 Sp 11 33

34 Cycle 62 LD F2 45+ R MULTD F0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Mult2 Add Divide 62 FU S. Reda EN164 Sp 11 34

35 Cycle 62 LD F2 45+ R MULTD F0 F2 F SUBD F8 F6 F DIVD F10 F0 F ADDD F6 F8 F Integer Mult1 Mult2 Add Divide 62 FU In-order issue; out-of-order execute & commit S. Reda EN164 Sp 11 35

36 Summary of scoreboard-based dynamic scheduling Limitations of scoreboard: forwarding hardware Limited to instructions in basic block (i.e., no branching speculation is possible because commit is out of order) Do not issue on structural hazards Wait for WAR hazards Stall for WAW hazards S. Reda EN164 Sp 11 36