Dr. D. M. Akbar Hussain

Transcription

1 Course Objectives: To enable the students to learn some more practical facts about DSP architectures. Objective is that they can apply this knowledge to map any digital filtering algorithm and related similar processing algorithms on a digital signal processing hardware. To provide students with a global view of embedded microarchitecture implementation options and design methodologies for signal processing. The interaction between the algorithm formulation and the underlying architecture that implements the algorithm will be focused. Achievement Through These Objectives: This course is to compliment your ability to understand both hardware and software for a particular DSP architecture, which hopefully will help you in doing your project in the digital signal processing domain. By the end of this course you will have more clear picture about various filtering algorithms, how they can be designed and implemented and also the hardware architecture insight for a DSP system. Hopefully, students are expected do well with their project development. 2 2 Material and Books Used for the Course: Course Outline & Structure The DSP Handbook: Algorithms, Applications and Design Techniques. By: Andrew Bateman & Ian Paterson-Stephens Computer Organization & Design: The Hardware/Software Interface. By: David A. Patterson & John L. Hennessy High Performance Computing. By: Kevin Dowd & Charles Severance Computer Architecture Software and Hardware. By: Richard Y. Kain Books can be used for background reading. Books can also be used for your personal lecture preparation. Further reading/learning must be accomplished using the sources description provided on the course web page Total 8 lectures (.6 Module Course). Each class consists of two 45 minute lecture sessions & are Organized as Study Groups. This course will cover the following topics in General: Description of a General DSP System, DSK TMS320C646 detailed discussion. Complete discussion on McBSP, including all registers, A real sinewave sampled by TMS320C646 DSK at various sampling rate. Generation of a corrupted signal using both MATLAB and Code Composer and filtering it. How do we design a filter for a random signal which may be corrupted with noise. Designing an FIR/IIR Filter for Implementation, Magnitude Response to determine attenuation. Designing of filters using SPTOOL and FDATOOL. Fixed and Floating Point Processing, Random Signals, Quantization and Word Length, Rounding, Saturation Mathematics. Designing the Kalman Filter for a random signal. 4 4 Some Useful Books & Resources used for preparing these lectures:. Teaching Material From Texas Instruments. 2. Multiple Processing: A System Overview By: A. John Anderson. 3. DSP System Design By: Nasser Kehtarnavaz & Mansour Keramat McBSP as High Speed Communication Port 8. McBSP Initialization 9. McBSP Used as Digital Controller with Codec 0. McBSP IO2M Interface. McBSP Reference Guide What is a SIGNAL? Lecture (DE6, 2007)

2 A SIGNAL is a measurement of a physical quantity of certain medium. Examples of signals: Visual patterns (written documents, picture, video, gesture, facial expression) Audio patterns (voice, speech, music) Change patterns of other physical quantities: temperature, EM wave, etc. Importantly Signal Contains INFORMATION! Medium and Modality Medium: Physical materials that carry the signal. Examples: paper (visual patterns, handwriting, etc.), Air (sound pressure, music, voice), various video displays (CRT, LCD). Modality: Different modes of signals over the same or different media. Examples: voice, facial expression and gesture What is Signal Processing? Ways to manipulate signal in its original medium or an abstract representation. Signal can be abstracted as functions of time or spatial coordinates. Types of processing: Transformation Filtering Detection Estimation Recognition and classification Coding (compression) Synthesis and reproduction Recording, archiving Analyzing, modeling Communications: Modulation/Demodulation (modem) Channel estimation, equalization, coding Source coding: compression Imaging: Digital camera scanner HDTV, DVD Audio 3D sound Speech Coding Recognition Synthesis Translation Virtual reality, animation Control Hard drive Motor Signal Processing Applications Digital Signal Processing Signal Processing Systems Signals generated via physical phenomenon are analog in that: Their amplitudes are defined over the range of real/complex numbers. Their domains are continuous in time or space. Processing analog signal requires dedicated, special hardware. Digital signal processing concerns processing signals using digital computers. A/D Digital Signal Processing D/A A continuous time/space signal must be sampled to yield countable signal samples. The real-(complex) valued samples must be quantized to fit into internal word length. The task of digital signal processing (DSP) is to process sampled signals (from A/D analog to digital converter), and provide its output to the D/A (digital to analog converter) to be transformed back to physical signals. 2 2 Lecture (DE6, 2007) 2

3 Implementation of DSP Systems Platforms: Native signal processing (NSP) with general purpose processors (GPP) Multimedia extension (MMX) instructions Programmable digital signal processors (PDSP) Media processors Application-Specific Integrated Circuits (ASIC) Re-configurable computing with field-programmable gate array (FPGA) Requirements: Real time Processing must be done before a pre-specified deadline. Streamed numerical data Sequential processing Fast arithmetic processing High throughput Fast data input/output Fast manipulation of data It depends! Real time requirements: Example: data capture speed must match sampling rate. Otherwise, data will be lost. Example: in verbal conversation, delay of response can not exceed 50ms end-to-end. Processing must be done by a specific deadline. A constraint on throughput. How Fast is Enough for DSP? Different throughput rates for processing different signals Throughput sampling rate CD music: 44. khz Speech: 8-22 khz Video (depends on frame rate, frame size, etc.) range from 00s khz to MHz Early Signal Processing Systems Computing Fourier Transform Discrete Fourier Transform Implemented with either main frame computer or special purpose computers. Batch processing rather than real time, streamed data processing. Accelerated processing speed is of main concern. Key approach: Faster hardware Faster algorithms Faster algorithms Reduce the number of arithmetic operations Reduce the number of bits to represent each data Most important example: Fast Fourier Transform X x ( ( n k ) ) = = N n N = To compute the N frequencies {X(k); 0 k N } requires N 2 complex multiplications 0 N k = x 0 ( n X ) ( exp[ k ) exp[ 2 π nk N 2 π nk N ] ] Fast Fourier Transform Reduce the computation to O(N log 2 N) complex multiplications Makes it practical to process large amount of digital data. Many computations can be Speedup using FFT Dawn of modern digital signal processing Evolution of Micro-Processor Native Signal Processing Micro-processors implemented a central processing unit on a single chip. Performance improved from MFLOP (983) to + GFLOP. Word length (# bits for register, data bus, addr. Space, etc) increases from 4 bits to 64 bits today. Clock frequency increases from 00KHz to over + 2GHz. Number of transistors increases from K to 50M. Power consumption increases much slower with the use of lower supply voltage: 5 V drops to.5v. Use GPP to perform signal processing task with no additional hardware. Example: soft-modem, soft DVD player, soft MPEG player. Reduce hardware cost! May not be feasible for extremely high throughput tasks. Interfering with other tasks as GPP is tied up with NSP tasks. MMX (multimedia extension instructions): special instructions for accelerating multimedia tasks. May share same data-path with other instructions, or work on special hardware modules. Make use sub-word parallelism to improve numerical calculation speed. Implement DSP-specific arithmetic operations, eg. Saturation arithmetic ops Lecture (DE6, 2007) 3

4 ASIC: Application Specific Integrated Circuits Custom or semi-custom IC chip or chip sets developed for specific functions. Suitable for high volume, low cost productions. Example: MPEG codec, 3D graphic chip, etc. ASIC becomes popular due to availability of IC foundry services. Fab-less design houses turn innovative design into profitable chip sets using CAD tools. Design automation is a key enabling technology to facilitate fast design cycle and shorter time to market delay. Programmable Digital Signal Processors (PDSPs) Micro-processors designed for signal processing applications. Special hardware support for: Multiply-and-Accumulate (MAC) ops Saturation arithmetic ops Zero-overhead loop ops Dedicated data I/O ports Complex address calculation and memory access Real time clock and other embedded processing supports. PDSPs were developed to fill a market segment between GPP and ASIC: GPP flexible, but slow ASIC fast, but inflexible As VLSI technology improves, role of PDSP changed over time. Cost: design, sales, maintenance/upgrade Performance Multimedia Signal Processors Re-configurable Computing using FPGA Specialized PDSPs designed for multimedia applications Features: Multi-processing system with a GPP core plus multiple function modules VLIW-like instructions to promote instruction level parallelism (ILP) Dedicated I/O and memory management units. Main applications: Video signal processing, MPEG, H.324, H.263, etc. 3D surround sound Graphic engine for 3D rendering FPGA (Field programmable gate array) is a derivative of PLD (programmable logic devices). They are hardware configurable to behave differently for different configurations. Slower than ASIC, but faster than PDSP. Once configured, it behaves like an ASIC module. Use of FPGA Rapid prototyping: run fractional ASIC speed without fabrication delay. Hardware accelerator: using the same hardware to realize different function modules to save hardware Low quantity system deployment The term VLSI, Very Large Scale Integration was emerged in late 970s. Usage of VLSI: Micro-processor General purpose Programmable DSP Embedded μ-controller Application-specific ICs Field-Programmable Gate Array (FPGA) Impacts: Design methodology Performance Power VLSI Characteristics High density: Reduced feature size: 0.25µm -> 0.6 µm % of wire/routing area increases Low power/high speed: Decreased operating voltage:.8v -> V Increased clock frequency: 500 MHz-> 2 GH. High complexity: Increased transistor count: 0M transistors and higher Shortened time-to-market delay: 6-2 months Design Issues Given a DSP application, which implementation option should be chosen? For a particular implementation option, how to achieve optimal design? Optimal in terms of what criteria? Software design: NSP/MMX, PDSP/MSP Algorithms are implemented as programs. Often still require programming in assembly level manually Hardware design: ASIC, FPGA Algorithms are directly implemented in hardware modules. S/H Co-design: System level design methodology Lecture (DE6, 2007) 4

5 Design Process Model Design is the process that links algorithm to implementation Algorithm Operations Dependency between operations determines a partial ordering of execution Can be specified as a dependence graph Implementation Assignment: Each operation can be realized with One or more instructions (software) One or more function modules (hardware) Scheduling: Dependence relations and resource constraints leads to a schedule. Design Example n y = a( k) x( k) Operations: k= Multiplication Addition Dependency y(k) depends on y(k-) * Dependence Graph: Program: y(0) = 0 for k = to n do y(k) = y(k-)+ a(k)*x(k) end y = y(n) y(0) + a() x() a(2) x(2) y() * + y(2) a(n) x(n) * + y(n) Software Implementation: Map each * op. to a MUL instruction, and each + op. to a ADD instruction. Allocate memory space for {a(k)}, {x(k)}, and {y(k)} Schedule the operation by sequentially execute y()=a()*x(), y(2)=y() + a(2)*x(2), etc. Note that each instruction is still to be implemented in hardware. Hardware Implementation: Map each * op. to a multiplier, and each + op. to an adder. Interconnect them according to the dependence graph: Reality Implementation is realized with a hardware. However, by using the same hardware to realize different operations at different time (scheduling), we have a software program! Bottom line Hardware/ software co-design. There is a continuation between hardware and software implementation. A design must explore both simultaneously to achieve best performance/cost trade-off Matching hardware to algorithm Hardware architecture must match the characteristics of the algorithm. Example: ASIC architecture is designed to implement a specific algorithm, and hence can achieve superior performance. Formulate algorithm to match hardware Algorithm must be formulated so that they can best exploit the potential of architecture. Example: GPP, PDSP architectures are fixed. One must formulate the algorithm properly to achieve best performance e.g., to minimize number of operations. Algorithm Reformulation Matching algorithm to architectural features Similar to optimizing assembly code Exploiting equivalence between different operations Reformulation methods Equivalent ordering of execution: (a+b)+c = a+(b+c) Equivalent operation with a particular representation: a*2 is the same as left-shift a by bit in binary representation Algorithmic level equivalence Different filter structures implementing the same specification! Exploiting parallelism Regular iterative algorithms and loop reformulation Well studied in parallel compiler technology Signal flow/data flow representation Suitable for specification of pipelined parallelism Lecture (DE6, 2007) 5

6 Mapping Algorithm to Architecture Hardware & Software (TMS320C646) Scheduling and Assignment Problem Resources: hardware modules, and time slots Demands: operations (algorithm), and throughput Constrained optimization problem Minimize resources (objective function) to meet demands (constraints) For regular iterative algorithms and regular processor arrays -> algebraic mapping. Irregular multi-processor architecture: Heuristic methods Algorithm reformulation for recursions. Instruction level parallelism MMX instruction programming Related to optimizing compilation. 600 MHz C646 DSP AIC23 Stereo Codec External Memory 6M Bytes SDRAM 52K Bytes Flash ROM 4 user accessible LED s and DIP Switches Daughter card expansion Software Board Configuration through registers implemented in CPLD JTAG Emulation through on-board JTAG emulator with USB host interface or external emulator Power Supply & Parallel Port Cable Lecture (DE6, 2007) 6

7 Units means DSP can issue/execute 8, 32 bit instruction per clock cycle. This also means that if the clock frequency is 200 MHz, it can perform 600 MIPS. TMS320C646 also have XOR, AND-NOT logical operations. Modified Harvard Architecture. Inside a Bus of 256 bits is constructed to hold 8, 32 bit instructions Lecture (DE6, 2007) 7

8 Pipelining of TMS320C646: Pipelining of TMS320C646: Fetch: PG, PS, PW & PR. Decode: DP & DC. Execute: E, E2, E3, E4 & E PG: Program address generation phase computes the next sequential fetch-packet address or branch instruction. PS: Program address send phase sends the program address to memory. PW: Program address ready wait phase waits until either a memory access or a tag compare is completed. DP: The instruction dispatch phase separates fetch packets into execute packets. DC: The instruction decode phase decodes source registers destination registers and associated paths. PR: Program fetch packet receive phase receives the fetch packet from memory Lecture (DE6, 2007) 8

9 E to E5: The execute stage is divided into 5 phases (stage 7 to in the pipeline. Different types of instructions require various number of clock cycles to complete the operation. Most instruction are completed in phase E and do not require any delay. However, multiply instruction for example requires two stages, therefore, latency of two instruction cycles and a delay of one instruction cycle are introduced. Critical Factors Determining the Program Execution on a DSP are: Sampling Rate Complexity of the Algorithm Quantization: DSP Product Design Constraints: Cost of the product. Cost of the design. Upgradeability. A process to represent a sampled value by the nearest value which corresponds to an integer scale. This process introduce quantization, greater is the gap between discrete true value and the value represented, greater will be the quantized noise. System integration. Power consumption Sampling & Quantization: Sampling: Converting a continuous time signal into discrete time signal (still having continuous amplitude at discrete time intervals). DSP systems only have Digital Signal (Sampling & Quantization is performed by ADC). Amplitude values are converted into digital values by given word length (N) of the DSP (which introduces quantization). Shannon Sampling Theorem Sampling period is dependent on the input signal frequency. To accurately construct a given signal the sampling frequency must be at-least twice the bandwidth. f s 2 f m If Shannon theorem is violated Aliasing will occur Lecture (DE6, 2007) 9

10 Aliasing: Example: Music sampled at 44. KHz. Voice sampled at 8 KHz. The above figure illustrates what happens if a signal is sampled at regular time intervals that are slightly less often than once per period of the original signal. The blue curve is the original signal, and the red dots indicate the sampled values SQNR (Signal to Quantization Noise Ratio): SQNR = 6 db = V FS / 2 N V FS = 2 V, N = 3 = 0.25 V CODEC: Actually includes an Anti-Aliasing filter. Which could be a switched capacitor filter (it can be programmable with different frequencies). μ law A law Lecture (DE6, 2007) 0