Si CMOS Technical Working Group CTR, Spring 2008 meeting Markets Interconnects TWG Breakouts Reception TWG reports Si CMOS: photonic integration E-P synergy - Integration - Standardization - Cross-market Platforms Power - Bandwidth - Latency - Footprint communications - Package technology - roadmap Cost
CMOS Device focused Si will do everything it can III-V will be an ever smaller tip of the pyramid Assumes Interconnect-Packaging-Integration TWG will solve those problems Focus is on the transceiver as the fundamental block necessarily heavily dependent on packaging implementations Provides an implementation roadmap for the IPI TWG and external research groups Provides device implications to the applications in the Xmarket TWG
CMOS: Working Conclusions The transceiver is the driver for a silicon microphotonics platform roadmap. The relevant attributes of a transceiver are aggregate data rate, power consumption, size, and cost. Silicon is the only material platform capable of supporting a standard cross-market, high-volume transceiver in the long term. Optical interconnects will be single mode. Initial optical cabling applications will be multimode, but board-to-board or chip-to-chip will be single mode. WDM will be necessary for aggregate data rates >40Gb/s. A monolithically integrated, stable light source for silicon has no known solution, and an independent optical power supply will be the dominant architecture in the near term. Increasing system parallelism will require roadmap coordination with interconnection from intra-chip to the box-to-box level.
Si CMOS: Questions Key questions: What are the main components/elements? What are the key intermediate product (set) plateaus? What core technologies look promising? What appear to be the hardest problems? Key answer The silicon platform is not about cost, it is about high performance.
The Optical Power Supply Silicon Platform Architecture photon power supply 3dB amplifier waveguides (Si, Si 3 N 4 ) splitters, bends modulators, photodetectors (Ge) monolithic multi-λ electrical injection small footprint process integrated integrated driver circuit
Large Scale Photonic Integration Tool Box Waveguide (VHIC): capacity/ (loss x volume) Amplifier: gain/(power x area x noise) Modulator: speed/ (power x area) Photodetector: (speed x QE)/area Optical power supply: multi-λ (CW); low jitter (pulsed) Couplers/Splitters: board, devices, impedance matching Thermal Stability: pm/ 0 C Package: pluggable, minimum optical pin count E-P circuit theory: time, energy, analog, digital
HIC Amplifier Scaling Law 10 5 FOM (db/mw/cm 2 ) 10 4 10 3 10 2 10 1 slope=2.6 P p =1mW G=3dB A=1mm 2 Physics of Optical Scaling 10 0 10-1 0.1 1 Index Difference!n Performance = gain / (noise x pump power x area) Saini and Michel, MIT
Fiber-Waveguide Coupling Size mismatch of optical modes Index mismatch of materials Alignment of optical fiber Silicon Waveguide (0.2 x 0.5 µm) SiO 2 Cladding MIT Coupling Solutions Staged Mode Transformers Inverted Taper Planar GRIN Lens Optical Fiber Core (8 µm )
Photodetectors (Bandwidth) x (Quantum efficiency) (GHz) 80 70 60 50 40 30 20 10 0 5µm 20µm Q.E: 90% Transit time limit d=0.5µm Waveguide-integrated Photodetector RC time limit 10 2 10 3 10 4 Detector Size (µm 2 ) Broadband, highly efficiency IR Low voltage operation CMOS process flow Waveguide-detector integration photon Discrete, free-space Photodetectors d=2.0µm PD1 (L = 160 µm) PD2 (L = 80 µm) Photocurrent measurement output D. Ahn, J.F. Liu, MIT
Modulators Compact, integrated, Si-compatible Highest power consumption of active devices Modulation efficiency: large EO effect Modulation Depth (% 70 60 50 40 30 20 10!=1550 nm 0 0 1 2 3 4 5 6 7 Reverse Bias (V) SiGe EAM CMOS mask intergration w PD Low voltage 20nm spectral BW 50fJ/bit J. Liu, S. Jongthammanurak, D. Pan, J. Michel and L.C. Kimerling
Thermal Stability Athermal Waveguide Devices: polymer cladding Two parameters to determine athermal conditions: (i) Mode confinement factor Γ: index contrast, geometry & dimension (ii) Materials properties (dn/dt, n) Filter then Detect to Winnie Ye, MIT and Dupont Photonics
CMOS Fabrication Si CMOS FEOL BEOL SiGe <450 <550 750* 900 SiGe CMOS FET & Integration Scenarios
Monolithic DH Si-Ge-Si Laser Design Design Principles Double Heterojunction tensile strain n + Ge doping carrier confinement 10 20 /cm 3 electrons E g _ n + carrier confinement layer n + Ge p + Si n + Ge p + SiGe buffer layers p + Si J th = 3.3 ka/cm 2 η d = 0.15 P o (50mA) = 5.5 mw J.F. Liu et al., Optics Express 15, 11272 (2007) AFOSR MURI, Gernot Pomrenke
Conquering the Last Centimeter the philosophy Integration creates a circuit function. not customized perfect devices A microphotonic circuit contains replicated circuit elements on a standard platform. materials, processes, design and fab tools Silicon Microphotonics is the only option for continued exponential increase in chip performance. Has potential to provide the majority of low-cost photonic interconnects in the medium to long term
CMOS SWOT: EA modulators Strengths Weaknesses Opportunities Threats
CMOS Issues: Transceiver Urgent Not urgent important Not important
Microphotonic Components Device Metric now target waveguide loss/size 1.0 db/cm 10-3 db/cm coupler/splitter loss/size/uniformity 20µm / 0.1dB resonator/filter precision/stability 0.1pm/K modulator speed x extinction 6x10 7 (fj) -1 power x loss photodetector speed x A/W 10 7 GHz A/Wcm 2 footprint optical power supply power efficiency 0.5 amplifier speed x power footprint package BW density E-P circuit theory compatibility
CTR: Phase 2 Technology Targets Materials large area wafers; component integration compatibility Processes tool standardization, common processes, process control, process integration Packaging Infrastructure Test Design an optical chip carrier without a permanent fiber attach chips; boards; backplanes; interbox; LAN; FTTH; MAN; WAN common test platform; wafer level testing; global standard test common design tools; common form factors; reduce complexity; focus on functionality methodology for electronic/photonic partitioning photonic circuit theory to support appropriate simulation tools