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HCPL-5, HCPL-5, HCPL-454 HCPL-5, HCPL-5, HCPL-54 Dual Channel, High Speed Optocouplers Data Sheet Description These dual channel optocouplers contain a pair of light emitting diodes and integrated photo-detectors with electrical insulation between input and output. Separate connection for the photodiode bias and output transistor collectors increase the speed up to a hundred times that of a conventional phototransistor coupler by reducing the base-collector capacitance. These dual channel optocouplers are available in an Pin DIP and in an industry standard SO- package. The following is a cross reference table listing the Pin DIP part number and the electrically equivalent SO- part number. SO- Pin DIP Package HCPL-5 HCPL-5 HCPL-5 HCPL-5 HCPL-454 HCPL-54 Features 5 kv/µs minimum common mode transient immunity at V CM = 5 V (HCPL-454/54) TTL compatible Available in pin DIP, SO-, and pin DIP gull wing surface mount (option ) packages High density packaging MHz bandwidth Open collector outputs Guaranteed performance from C to C Safety approval UL Recognized 5 V rms for minute (5 V rms for minute for Option ) per UL5 CSA Approved IEC/EN/DIN EN 4-5- V IORM = Vpeak for HCPL-5/5/454 ption V IORM = 5 Vpeak for HCPL-5/5/54 ption Single channel version available (45/, 45/) MIL-PRF-54 hermetic version available (55XX/5XX/4N55) Functional Diagram ANODE CATHODE CATHODE ANODE 4 5 A. µf bypass capacitor between pins 5 and is recommended. V CC V O V O GND TRUTH TABLE (POSITIVE LOGIC) LED V O ON LOW OFF HIGH Applications Line receivers high common mode transient immunity (> V/µs) and low input-output capacitance (. pf) High speed logic ground isolation TTL/TTL, TTL/LTTL, TTL/CMOS, TTL/LSTTL Replace pulse transformers save board space and weight Analog signal ground isolation integrated photon detector provides improved linearity over phototransistor type Polarity sensing Isolated analog amplifier dual channel packaging enhances thermal tracking CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

The SO- does not require through holes in a PCB. This package occupies approximately one-third the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-5/5 is for use in TTL/CMOS, TTL/LSTTL or wide bandwidth analog applications. Current transfer ratio (CTR) for the HCPL-5/5 is % minimum at I F = ma. The HCPL-5/5 is designed for high speed TTL/TTL applications. A standard ma TTL sink current through the input LED will provide enough output current for TTL load and a 5. kω pull-up resistor. CTR of the HCPL-5/5 is 9% minimum at I F = ma. The HCPL-454/54 is an HCPL- 5/5 with increased common mode transient immunity of 5, V/µs minimum at V CM = 5 V guaranteed. Selection Guide Widebody Minimum CMR -pin DIP ( Mil) Small-Outline SO- (4 Mil) Hermetic Current Dual Single Dual Single Single Single and dv/dt V CM Transfer Channel Channel Channel Channel Channel Dual Channel (V/µs) (V) Ratio (%) Package Package* Package Package* Package* Packages*, HCPL-5 N5 HCPL-5 HCPL-5 HCNW5 9 HCPL-5 N HCPL-5 HCPL-5 HCNW HCPL-45 HCPL-45 HCNW45 5, 5 9 HCPL-454 HCPL-45 HCPL-54 HCPL-45 HCNW45, 9 HCPL-55XX HCPL-5XX 4N55 *Technical data for these products are on separate Avago publications.

Ordering Information HCPL-5, HCPL-5, HCPL-454, HCPL-5, HCPL-5 and HCPL-54 are UL Recognized with 5 V rms for minute per UL5 and are approved under CSA Component Acceptance Notice #5, File CA 4. Option Part RoHS Non RoHS Surface Gull Tape UL 5 V rms / IEC/EN/DIN Number Compliant Compliant Package Mount Wing & Reel Minute Rating EN 4-5- Quantity -E No option 5 per tube -E - X X 5 per tube -5E -5 X X X per reel HCPL-5 -E - X 5 per tube mil HCPL-5 -E - X X X 5 per tube DIP-x HCPL-454-5E -5 X X X X per reel HCPL-5 HCPL-5 HCPL-54 -E - X 5 per tube -E - X X X 5 per tube -5E -5 X X X X per reel -E No option per tube SO- -5E -5 X X X 5 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL-5-5E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 4-5- Safety Approval in RoHS compliant. Example : HCPL-5 to order product of mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since 5 th July and RoHS compliant option will use -XXXE.

UR Schematic + I F I CC V CC V F I O V O I F I O V F V O + 4 5 GND HCPL-454/54 SHIELD USE OF A. µf BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND IS RECOMMENDED. Package Outline Drawings -Pin DIP Package (HCPL-5/5/454) 9.5 ±.5 (. ±.). ±.5 (. ±.) TYPE NUMBER A XXXXZ 5 OPTION CODE* DATE CODE.5 ±.5 (.5 ±.) YYWW 4 UL RECOGNITION.9 (.4) MAX..5 ±. (.4 ±.5). (.) MAX. 4. (.5) MAX. 5 TYP..54 +. -.5 (. +.) -.). ±. (.4 ±.).5 (.) MIN..9 (.5) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION OPTION NUMBERS AND 5 NOT MARKED..5 (.5) MAX. NOTE: FLOATING LEAD PROTRUSION IS.5 mm ( mils) MAX..54 ±.5 (. ±.) 4

Package Outline Drawings, continued -Pin DIP Package with Gull Wing Surface Mount Option (HCPL-5/5/454) LAND PATTERN RECOMMENDATION 9.5 ±.5 (. ±.). (.4) 5.5 ±.5 (.5 ±.).9 (.4) 4. (.5). (.).9 (.4) MAX.. (.) MAX..5 ±. (.4 ±.5) 9.5 ±.5 (. ±.). ±.5 (. ±.).54 +. -.5 (. +.) -.). ±. (.4 ±.).54.5 ±. (.) (.5 ±.5) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (.4 INCHES)..5 ±.5 (.5 ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS.5 mm ( mils) MAX. Small Outline SO- Package (HCPL-5/5/54) LAND PATTERN RECOMMENDATION.9 ±. (.55 ±.5) 5 XXX YWW.4 ±. (. ±.). (.5) BSC 4 5.994 ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE.4 (.5).9 (.5).49 (.95) * 5. ±. (. ±.5) 45 X.4 (.).5 ±. (.5 ±.5).54 (.). ±.5 (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5. ±.54 (.5 ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (.4 INCHES) MAX..5 (.) MIN.. ±. (. ±.4) NOTE: FLOATING LEAD PROTRUSION IS.5 mm ( mils) MAX. 5

Solder Reflow Thermal Profile TEMPERATURE ( C) PREHEATING RATE C + C/.5 C/SEC. REFLOW HEATING RATE.5 C ±.5 C/SEC. C 5 C 4 C C + C/.5 C.5 C ±.5 C/SEC. PREHEATING TIME 5 C, 9 + SEC. PEAK TEMP. 45 C SEC. SEC. 5 SEC. PEAK TEMP. 4 C SOLDERING TIME C PEAK TEMP. C ROOM TEMPERATURE TIGHT TYPICAL LOOSE 5 5 5 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile TEMPERATURE T p +/-5 C T L C RAMP-UP C/SEC. MAX. T smax 5 - C T smin t s PREHEAT to SEC. t p t L TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE -4 SEC. RAMP-DOWN C/SEC. MAX. to 5 SEC. 5 t 5 C to PEAK TIME NOTES: THE TIME FROM 5 C to PEAK TEMPERATURE = MINUTES MAX. T smax = C, T smin = 5 C Note: Non-halide flux should be used. Regulatory Information The devices contained in this data sheet have been approved by the following organizations: UL Recognized under UL 5, Component Recognition Program, File E55. CSA Approved under CSA Component Acceptance Notice #5, File CA 4. IEC/EN/DIN EN 4-5- Approved under: IEC 4-5-:99 + A: EN 4-5-: + A: DIN EN 4-5- (VDE 4 Teil ):-. (Option only)

Insulation and Safety Related Specifications -Pin DIP ( Mil) SO- Parameter Symbol Value Value Units Conditions Minimum External L(). 4.9 mm Measured from input terminals to output to Air Gap (External to output terminals, shortest distance through air. Clearance) Minimum External L().4 4. mm Measured from input terminals to output Tracking (External terminals, shortest distance path along body. Creepage) Minimum Internal.. mm Through insulation distance, conductor to Plastic Gap (Internal Clearance) conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Minimum Internal NA NA mm Measured from input terminals to output Tracking (Internal terminals, along internal cavity. Creepage) Tracking Resistance CTI Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /9, Table ) Option - surface mount classification is Class A in accordance with CECC.

IEC/EN/DIN EN 4-5- Insulation Characteristics (Option ) Characteristic HCPL- HCPL- Description Symbol 5/5/454 5/5/54 Unit Installation classification per DIN VDE /.9, Table for rated mains voltage 5 V rms I-IV for rated mains voltage V rms I-IV I-III for rated mains voltage V rms I-III I-II Climatic Classification 55// 55// Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM 5 V peak Input to Output Test Voltage, Method b* V IORM x.5 = V PR, % Production Test V PR 5 V peak with t m = sec, Partial Discharge < 5 pc Input to Output Test Voltage, Method a* V IORM x.5 = V PR, Type and Sample Test, V PR 945 4 V peak t m = sec, Partial Discharge < 5 pc Highest Allowable Overvoltage V IOTM 4 V peak (Transient Overvoltage, t ini = sec) Safety Limiting Values (Maximum values allowed in the event of a failure.) Case Temperature T S 5 5 C Input Current** I S,INPUT ma Output Power** P S,OUTPUT mw Insulation Resistance at T S, V IO = 5 V R S > 9 > 9 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer's Catalog, under Product Safety Regulations section, IEC/EN/DIN EN 4-5-, for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of P S and I S on ambient temperature. Note: Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application. OUTPUT POWER P S, INPUT CURRENT I S 5 4 5 P S (mw) I S (ma) 5 5 5 5 5 T S CASE TEMPERATURE C

Absolute Maximum Ratings Parameter Symbol Device Min. Max. Units Note Storage Temperature T S -55 5 C Operating Temperature T A -55 C Average Forward Input Current I F(AVG) 5 ma (each channel) Peak Forward Input Current (each channel) I F(PEAK) 5 ma (5% duty cycle, ms pulse width) Peak Transient Input Current (each channel) I F(TRANS) A ( µs pulse width, pps) Reverse LED Input Voltage (each channel) V R 5 V Input Power Dissipation (each channel) P IN 45 mw Average Output Current (each channel) I O(AVG) ma Peak Output Current I O(PEAK) ma Supply Voltage (Pin -5) V CC -.5 V Output Voltage (Pins -5, -5) V O -.5 V Output Power Dissipation (each channel) P O 5 mw Lead Solder Temperature T LS Pin DIP C (Through-Hole Parts Only). mm below seating plane, seconds Reflow Temperature Profile T RP SO- and see Package Outline Drawings Option section 9

Electrical Specifications (DC) Over recommended temperature (T A = C to C) unless otherwise specified. See note 9. Parameter Sym. Device Min. Typ.* Max. Units Test Conditions Fig. Note Current CTR HCPL-5/ 5 % T A = 5 C I F = ma,,, Transfer 5 V CC = 4.5 V 4 Ratio 5 V O =.5 V HCPL-5/ 9 4 5 % T A = 5 C 5 HCPL-454/ 5 54 Logic Low V OL HCPL-5/..5 V T A = 5 C I O =. ma I F = ma, Output 5 V CC = 4.5 V Voltage.5 I O =. ma HCPL-5/..5 V T A = 5 C I O =. ma 5 HCPL-454/.5 I O =.4 ma 54 Logic High I OH..5 µa T A = 5 C V CC = V O = 5.5V, I F = ma Output I F = ma Current 5 T A = 5 C V CC = V O = 5V, I F = ma Logic Low I CCL 4 µa I F = ma, V O = Open, Supply V CC = 5 V Current Logic High I CCH.5 4 µa I F = ma, V O = Open, Supply V CC = 5 V Current Input V F.5. V T A = 5 C Forward I F = ma Voltage. Input BV R 5 V I R = µa Reverse Breakdown Voltage Temperature V F -. mv/ I F = ma Coefficient T A C of Forward Voltage Input C IN pf f = MHz, V F = V Capacitance *All typicals at T A = 5 C.

Switching Specifications (AC) Over recommended temperature (T A = C to C), V CC = 5 V, I F = ma unless otherwise specified. Device Parameter Sym. HCPL- Min. Typ.* Max. Units Test Conditions Fig. Note Propagation t PHL 5/5..5 µs T A = 5 C R L = 4. kω 5, 9,, Delay Time. to Logic Low 5/5/.. T A = 5 C R L =.9 kω at Output 454/54. Propagation t PLH 5/5..5 µs T A = 5 C R L = 4. kω 5, 9,, Delay Time. High to Logic 5/5/.. T A = 5 C R L =.9 kω at Output 454/54. Common CM H 5/5 kv/µs R L = 4. kω I F = ma, 5,, Mode Transient 5/5 R L =.9 kω T A = 5 C, Immunity at 454/54 5 R L =.9 kω V CM = V p-p Logic High Level Output Common CM L 5/5 kv/µs R L = 4. kω I F = ma, 5,, Mode Transient 5/5 R L =.9 kω T A = 5 C, Immunity at 454/54 5 R L =.9 kω V CM = V p-p Logic Low Level Output Bandwidth BW MHz R L = kω, *All typicals at T A = 5 C. Package Characteristics Parameter Sym. Device Min. Typ.* Max. Units Test Conditions Fig. Note Input-Output V ISO 5 V rms RH < 5%,, Momentary With- HCPL-5/ 5 t = min.,, stand Voltage** Resistance R I-O 5/454 Option Ω RH 45% (Input-Output) V I-O = 5 Vdc, t = 5 s Capacitance C I-O. pf f = MHz, (Input-Output) T A = 5 C Input-Input I I-I.5 µa RH 45%, 4 Insulation t = 5 s, Leakage Current V I-I = 5 Vdc Resistance R I-I Ω 4 (Input-Input) Capacitance C I-I HCPL-5/. pf f = MHz 4 (Input-Input) 5/454 HCPL-5/.5 5/54 *All typicals at T A = 5 C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 4-5- Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note 4 entitled Optocoupler Input-Output Endurance Voltage, publication number 59-E.

Notes:. Each channel.. CURRENT TRANSFER RATIO is defined as the ratio of output collector current, I O, to the forward LED input current, I F, times %.. Device considered a two-terminal device: pins,,, and 4 shorted together and pins 5,,, and shorted together. 4. Measured between pins and shorted together, and pins and 4 shorted together. 5. Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dv CM /dt on the rising edge of the common mode pulse, V CM, to assure that the output will remain in a Logic High state (i.e., V O >. V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dv CM /dt on the falling edge of the common mode pulse signal, V CM, to assure that the output will remain in a Logic Low state (i.e., V O <. V).. The.9 kω load represents TTL unit load of. ma and the 5. kω pull-up resistor.. The 4. kω load represents LSTTL unit load of. ma and the. kω pull-up resistor.. The frequency at which the ac output voltage is db below the low frequency asymptote. 9. Use of a. µf bypass capacitor connected between pins 5 and is recommended.. In accordance with UL 5, each optocoupler is proof tested by applying an insulation test voltage 45 V rms for second (leakage detection current limit, I I-O 5 µa).. In accordance with UL 5, each optocoupler is proof tested by applying an insulation test voltage V rms for second (leakage detection current limit, I I-O 5 µa).. Measured between the LED anode and cathode shorted together and pins 5 through shorted together.. Derate linearly above 9 C free-air temperature at a rate of. mw/ C for the SOIC- package. I O OUTPUT CURRENT ma 5 T A = 5 C V CC = 5. V 4 ma 5 ma ma 5 ma ma 5 ma ma I F = 5 ma NORMALIZED CURRENT TRANSFER RATIO.5. HCPL-5/5 HCPL-5/5/454/54.5 NORMALIZED I F = ma V O =.5 V V CC = 5 V T A = 5 C. I F FORWARD CURRENT ma... + V F I F.....4 T = 5 C A.5. V O OUTPUT VOLTAGE V I F INPUT CURRENT ma V F FORWARD VOLTAGE VOLTS Figure. DC and pulsed transfer characteristics. Figure. Current transfer ratio vs. input current. Figure. Input current vs. forward voltage. NORMALIZED CURRENT TRANSFER RATIO...9.. NORMALIZED I F = ma V O =.5 V V CC = 5 V T A = 5 C HCPL-5/5 HCPL-5/5/454/54. - -4-4 t P PROPAGATION DELAY ns 5 5 I F = ma, V CC = 5. V HCPL-5/5 (R L = 4. kω) HCPL-5/5/454/54 (R L =.9 kω) t PLH t PHL - - I OH LOGIC HIGH OUTPUT CURRENT na +4 + + + - I F = V O = V CC = 5. V - -5-5 +5 +5 +5 + T A TEMPERATURE C T A TEMPERATURE C T A TEMPERATURE C Figure 4. Current transfer ratio vs. temperature. Figure 5. Propagation delay vs. temperature. Figure. Logic high output current vs. temperature.

IO SMALL SIGNAL CURRENT TRANSFER RATIO IF... T A = 5 C, R L = Ω, V CC = 5 V 4 I F QUIESCENT INPUT CURRENT ma Figure. Small-signal current transfer ratio vs. quiescent input current. 4 AC INPUT NORMALIZED RESPONSE db +5 V -5 - -5 - -5 T A = 5 C I F = ma -.. SET I F. µf 5 Ω R L = Ω R L = Ω R L = 4 Ω R L = kω. f FREQUENCY MHz kω N5 Ω 4 5. µf R L +5 V V O. V dc.5 Vp-p ac Figure. Frequency response. I F V O.5 V 5 V.5 V V OL PULSE GEN. Z O = 5 Ω t r = 5 ns % DUTY CYCLE /f < µs I F MONITOR I F 4 5.µF R L +5 V V O C L = 5 pf t PHL t PLH R M Figure 9. Switching test circuit. R L V CM % 9% 9% % V V O V t r t FF f. µf VO V O SWITCH AT A: I = ma F SWITCH AT B: I = ma F 5 V V OL I F A B 4 5 V CM + PULSE GEN. +5 V t P PROPAGATION DELAY µs. I F = ma I F = ma. V CC = 5. V T A = 5 C....4.. 4 t PLH t PHL 5 9 R L LOAD RESISTANCE kω Figure. Test circuit for transient immunity and typical waveforms. Figure. Propagation delay time vs. load resistance.

For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright Avago Technologies Limited. All rights reserved. Obsoletes 599-5EN AV-EN June 9,