N- and P-Channel Enhancement-Mode Dual MOSFET TC2320 Features Low threshold Low on-resistance Low input capacitance Fast switching speeds Freedom from secondary breakdown Low input and output leakage Independent, electrically isolated N- and P-channels pplications Medical ultrasound transmitters High voltage pulsers mplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Logic level interface General Description The Supertex TC2320 consists of a high voltage, low threshold N- and P-channel MOSFET in an 8-Lead SOIC package. This low threshold enhancement-mode (normallyoff) transistor utilizes an advanced vertical DMOS structure and Supertex s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Ordering Information Device 8-Lead SOIC (Narrow Body) 4.90x3.90mm body, 75mm height (max) 27mm pitch BS /BV DGS (V) (max) (Ω) N-Channel P-Channel N-Channel P-Channel TC2320 TC2320TG-G 200-200 7.0 12 -G indicates package is RoHS compliant ( Green ) Pin Configuration DP DP DN DN bsolute Maximum Ratings Parameter Drain-to-source voltage Drain-to-gate voltage Value BS BV DGS Gate-to-source voltage ±2 Operating and storage temperature Soldering temperature* -55 C to +150 C +300 C bsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. ll voltages are referenced to device ground. Product Marking YYWW C2320 L L L L GP SP GN SN 8-Lead SOIC (TG) YY = Year Sealed WW = Week Sealed L = Lot Number = Green Packaging Package may or may not include the following marks: Si or 8-Lead SOIC (TG) * Distance of 6mm from case for 10 seconds. 1235 Bordeaux Drive, Sunnyvale, C 94089 Tel: 408-222-8888 www.supertex.com
TC2320 N-Channel Electrical Characteristics (T = 25 C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage 200 - - V = = 100µ (th) Gate threshold voltage 0.6-2.0 V = = 0m Δ(th) Change in (th) with temperature - - -4.5 mv/ O C = = 0m I GSS Gate body leakage - - 100 n = ±2, = I DSS I D(ON) Zero gate voltage drain current On-state drain current Static drain-to-source on-state resistance - - 0 µ =, = 10 - - 10.0 µ - - 0 m =, = Max rating =, T = 125 O C = 0.8 Max Rating 0.6 - - = 4.5V, = 25V 2 - - = 1, = 25V - - 8.0 = 4.5V = 150m Ω - - 7.0 = 1 = 0 Δ Change in with temperature - - 0 %/ O C = 4.5V =150m G FS Forward transconductance 150 - - mmho = 25V = 200m C ISS Input capacitance - - 110 C OSS Common source output capacitance - - 60 C RSS Reverse transfer capacitance - - 23 Turn-on delay time - - 20 Rise time - - 15 Turn-off delay time - - 25 t f Fall time - - 25 pf ns =, = 25V, f = 0MHz =25V, I D = 150m, = 25Ω V SD Diode forward voltage drop - - 8 V =, I SD = 200m Notes: 2. r Reverse recovery time - 300 - ns =, I SD = 200m ll D.C. parameters 100% tested at 25 O C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) ll.c. parameters sample tested. N-Channel Switching Waveforms and Test Circuit 1 t (ON) 90% t (OFF) PULSE GENERTOR R L t F D.U.T. 90% 90% 1235 Bordeaux Drive, Sunnyvale, C 94089 Tel: 408-222-8888 www.supertex.com 2
TC2320 P-Channel Electrical Characteristics (T = 25 C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage -200 - - V = = -2.0m (th) Gate threshold voltage -0 - -2.4 V = = -0m Δ(th) Change in (th) with temperature - - 4.5 mv/ O C = = -0m I GSS Gate body leakage - - -100 n = ±2, = I DSS I D(ON) Zero gate voltage drain current On-state drain current Static drain-to-source on-state resistance - - -10 µ =, = Max rating - - -0 m =, T = 125 O C, = 0.8 Max Rating -0.25-0.7 - = -4.5V, = -25V -0.75-2.1 - = -1, = -25V - 10 15 = -4.5V = -100m Ω - 8.0 12 = -1 = -200m Δ Change in with temperature - - 7 %/ O C = -1 =-200m G FS Forward transconductance 100 250 - mmho = -25V = -200m C ISS Input capacitance - 75 125 C OSS Common source output capacitance - 20 85 C RSS Reverse transfer capacitance - 10 35 Turn-on delay time - - 10 Rise time - - 15 Turn-on delay time - - 20 t f Fall time - - 15 pf ns =, = -25V, f = 0MHz = -25V, I D = -0.75, = 25Ω V SD Diode forward voltage drop - - -8 V =, I SD = -0.5 Notes: 2. r Reverse recovery time - 300 - ns =, I SD = -0.5 ll D.C. parameters 100% tested at 25 O C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) ll.c. parameters sample tested. P-Channel Switching Waveforms and Test Circuit PULSE GENERTOR -1 90% t (ON) t (OFF) t F D.U.T. 90% 90% R L Output 1235 Bordeaux Drive, Sunnyvale, C 94089 Tel: 408-222-8888 www.supertex.com 3
TC2320 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90x3.90mm body, 75mm height (max), 27mm pitch D θ1 8 E Note 1 (Index rea D/2 x E1/2) E1 L2 Gauge 1 L1 L θ Seating 2 Top View Seating Note 1 h h View B View B 1 e b Side View View - Note: This chamfer feature is optional. Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Dimension (mm) Symbol 1 2 b D E E1 e h L L1 L2 θ θ1 MIN 35* 0.10 25 0.31 4.80* 5.80* 3.80* 0.25 0.40 0 O 5 O 27 04 0.25 NOM - - - - 4.90 6.00 3.90 - - - - BSC REF BSC MX 75 0.25 65* 0.51 5.00* 6.20* 4.00* 0.50 27 8 O 15 O JEDEC Registration MS-012, Variation, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version H101708. (The package drawing(s) in this data sheet may noeflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does noecommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless ieceives an adequate product liability indemnification insurance agreement. Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. 2008 ll rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TC2320 B122208 4 1235 Bordeaux Drive, Sunnyvale, C 94089 Tel: 408-222-8888 www.supertex.com
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