ACNVE mm DTI, MBd Digital Optocoupler Data Sheet Description The new ACNVE is an optically coupled gate that combines a AlGaAs light emitting diode and an integrated photo detector housed in a widebody package. ACNVE is designed and manufactured to comply with EN9- ATEX and IECEx. The distance-throughinsulation (DTI) between the emitting diode and photodetector is at mm. The output of the detector IC is an open collector Schottky clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of, V/μs at V cm = V This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The new ACNVE is suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments. Functional Diagram Anode Cathode SHIELD Vcc 9 Ve 8 Vo GND Truth Table (Positive Logic) LED ENABLE OUTPUT On H L Off H H On L H Off L H On L Off H Features Compliant to EN9- ATEX and IECEx (V) mm DTI mm creepage and clearance kv/μs Minimum Common Mode Rejection (CMR) at VCM = V High Speed: MBd Typical TTL Compatible Guaranteed ac and dc performance over temperature: - C to + C Available in -Pin widebody packages Safety Approval Approval at Vrms for minute per UL CSA Applications High Voltage insulation Intrinsic safety circuit PCB Board Power System Isolation Industrial Equipment Power Isolation A. μf bypass capacitor must be connected between pins V CC and GND. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information ACNVE is UL Recognized with Vrms for minute per UL. Part number Option RoHS Compliant Package Surface Mount Gull Wing Tape & Reel UL V rms / Minute rating Quantity ACNVE -E mil X per tube -E DIP- X X X per tube -E X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACNVE-E to order product of mil DIP- Widebody with Gull Wing Surface Mount package in Tape and Reel packaging with UL Vrms/min Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Schematic + I F I CC V CC I O 8 V O V F SHIELD I E 9 V E GND Use of a.µf bypass capacitor connected between pins of and is recommended (see note ).
-Pin Widebody (mils) DIP Package [. ±.]. ±. [. ±.]. ±. [.]. TYP [.]. MIN [.]. [. ±.]. ±. [. ±.]. ±. [.]. [.]. [.9]. [.998].8 [.]. [.8 ±.]. ±. [.]. TYP [.8 ±.8].9 ±. TYP [. ]. +.8 -. +. -. Dimensions in Inches [Millimeters] -Pin Widebody (mils) DIP Package with Gull Wing Surface Mount Option [. ±.]. ±. LAND PATTERN RECOMMENDATION [. ±.]. ±. [. ±.]. ±. [. ±.]. ±. [.9 ±.].9 ±. [.9 ±.].9 ±. [.]. TYP [.9 ±.].8 ±. [. ±.]. ±. [.8 ±.]. ±. [.]. MAX [. ±.]. ±. [. ±.].9 ±. [. ]. NOM +. -. +. -. Dimension in Inches [Millimeter]
Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-Halide Flux should be used. Insulation and Safety Related Specifications Parameter Symbol ACNVE Units Conditions Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) Maximum Working Insulation Voltage L() mm Measured from input terminals to output terminals, shortest distance through air. L() mm Measured from input terminals to output terminals, shortest distance path along body.. mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector.. mm Measured from input terminals to output terminals, along internal cavity. CTI V DIN IEC /VDE Part. V IORM V peak Per IEC 9-. Safety-limiting values maximum values allowed in the event of a failure. Case Temperature T S C Input Current** I S, INPUT ma Output Power** P S, OUTPUT W Isolation Group IIIa Material Group (DIN VDE, /89, Table ). Note: ** Refer to Figure for dependence of PS and IS on ambient temperature. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S - C Operating Temperature T A - C Average Input Current I F(AVG) ma Reverse Input Voltage V R V Input Power Dissipation P I mw Supply Voltage ( Minute Maximum) V CC V Enable Input Voltage (Not to Exceed V CC by more than mv) V E V CC +. V Enable Input Current I E ma Output Collector Current I O ma Output Collector Voltage V O V Output Collector Power Dissipation P O 8 mw Lead Solder Temperature T LS C for sec, up to seat plane Solder Reflow Temperature Profile See Package Outline Drawings section
Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Input Current, Low Level I FL * µa Input Current, High Level I FH ** 9 ma Power Supply Voltage V CC.. V Low Level Enable Voltage V EL.8 V High Level Enable Voltage V EH. V CC V Operating Temperature T A - C Fan Out (at R L = k Ω) N TTL Loads Output Pull-up Resistor R L k Ω * The off condition can also be guaranteed by ensuring that V FL.8volts. ** The initial switching threshold is 8mA or less. It is recommended that 9mA to ma be used for best performance and to permit at least a % LED degradation guardband. Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. All typicals at V CC = V, T A = C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note High Level Output Current I OH. µa V CC =. V, V E =.V V O =. V, I FL = µa Input Threshold Current I TH. 8 ma V CC =. V, V E =.V, V O =. V, I OL > ma Low Level Output Voltage V OL.. V V CC =. V, V E =.V, I F = 8 ma, I OL(Sinking) = ma High Level Supply Current I CCH. ma V E =.V V CC =. V,. V E = V CC I F = ma Low Level Supply Current I CCL 9. ma V E =.V V CC =. V, 8. V E = V CC I F = ma High Level Enable Current I EH -. ma V CC =. V, V E =.V Low Level Enable Current I EL -.9 ma V CC =. V, V E =.V, High Level Enable Voltage V EH. ma V CC =. V, V E =.V Low Level Enable Voltage V EL.8 ma V CC =. V, V E =.V Input Forward Voltage V F...8 V T A = C I F = ma Input Reverse Breakdown Voltage.. BV R V I R = µa, T A = C Input Capacitance C IN pf f = MHz, V F = V Input Diode Temperature Coefficient ΔV F /ΔT A -.9 mv/ C I F = ma,,,
Switching Specifications (AC) Over recommended temperature (T A = - C to C), V CC = V, I F = ma unless otherwise specified. All typicals are at T A = C, V CC = V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level t PLH 8 ns T A = C R L = Ω, C L = pf,, 8, t PHL 8 ns T A = C, Pulse Width Distortion t PHL - t PLH ns R L = Ω, C L = pf Propagation Delay Skew t psk ns,, Output Rise Time (%-9%) T r ns Output Fall Time (%-9%) T f ns Propagation Delay Time of t ELH ns R L = Ω, C L = pf, Enable from V EH to V EL V EL = V, V EH = V Propagation Delay Time of t EHL ns R L = Ω, C L = pf, Enable from V EL to V EH V EL = V, V EH = V Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity Package Characteristics All typicals at T A = C. CM H kv/µs V CC = V, I F = ma, V O(MIN) = V, R L = Ω, T A = C, V CM = V CM L kv/µs V CC = V, I F = ma, V O(MAX) =.8 V, R L = Ω, T A = C, V CM = V,, 8, 9,, 8, 9,, Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Insulation V ISO V rms RH < % for min. T A = C Input-Output Resistance R I-O Ω V I-O = V Input-Output Capacitance C I-O.. pf f = MHz, T A = C,, Notes:. Peaking circuits may produce transient input currents up to ma, ns maximum pulse width, provided average current does not exceed ma.. By passing of power supply line is required, with a.µf ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure. Total lead length between both ends of the capacitor and the isolator pins should ot exceed mm.. The t PLH propagation delay is measured from the ma point on the falling edge of the input pulse to the. V point on the rising edge of the output pulse.. The t PHL propagation delay is measured from the ma point on the rising edge of the input pulse to the. V point on the falling edge of the output pulse.. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature and specified test conditions.. See application section titled Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew for more information.. The t ELH enable propagation delay is measured from the. V point on the falling edge of the enable input pulse to the. V point on the rising edge of the output pulse. 8. The t EHL enable propagation delay is measured from the. V point on the rising edge of the enable input pulse to the. V point on the falling edge of the output pulse. 9. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V O >. V).. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V O <.8 V).. For sinusoidal voltages, ( dv CM / dt) max = πf CM V CM(p-p).. No external pull up is required for a high logic state on the enable input. If the V E pin is not used, tying V E to V CC will result in improved CM R performance.. Device considered a two-terminal device: pins,,, and shorted together, and pins,, 8, 9 and shorted together.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O μa).,
IF - FORWARD CURRENT - ma VOL - Low Level Output Voltage - V VO - OUTPUT VOLTAGE - V Figure. Typical output voltage vs. forward input voltage current..8....... I F - FORWARD INPUT VOLTAGE - ma - - - 8 Figure. Typical low level output voltage vs. temperature........ I = ma I = 9. ma R L = Ω R L = k Ω R L = k Ω Figure. Typical input diode forward characteristic. I = ma I =. ma V CC = V T A = C V CC =. V V E =. V I F = 8. ma T A = C.......8 V F - FORWARD VOLTAGE - V ITH - INPUT THRESHOLD CURRENT - ma - - - 8 Figure. Typical input threshold current vs. temperature. IOL - LOW LEVEL OUTPUT CURRENT - ma I F = ma R L = Ω, k Ω, k Ω I F = 8 ma - - - 8 Figure. Typical low level output current vs. temperature. V CC =. V V E =. V V CC =. V V E =. V V OL =. V I F = - ma
+ V PULSE GEN. Z O = Ω t f = t r = ns INPUT MONITORING NODE R M I F SHIELD 9 8.µF BYPASS *C L R L OUTPUT V O MONITORING NODE INPUT I F OUTPUT V O *C L IS APPROXIMATELY pf WHICH ILUDES PROBE AND STRAY WIRING CAPACITAE. t PHL t PLH I F = ma I F = ma. V Figure. Test circuit for t PHL and t PLH tp - PROPAGATION DELAY - ns 9 8 V CC =. V T A = C t PLH, R L = kω t PLH, R L = Ω t PLH, R L = kω t PHL, R L = Ω t PHL, R L = kω kω - - - 8 Figure. Typical propagation delay vs. temperature. tp - PROPAGATION DELAY - ns 9 8 t PHL, R L = Ω t PHL, R L = kω t PHL, R L = kω t PLH, R L = kω Figure 8. Typical propagation delay vs. pulse input current. V CC =. V T A = C t PLH, R L = Ω t PLH, R L = kω 8 9 I F - PULSE INPUT CURRENT - ma PWD - PULSE WIDTH DISTORTION - ns - - R L = Ω R L = kω R L = kω - - - 8 Figure 9. Typical pulse width distortion vs. temperature. V CC =. V I F =. ma tr, tf - RISE,FALL TIME - ns V CC =. V I F =. ma R L = Ω R L = kω R L = kω - - - 8 Figure. Typical rise and fall time vs. temperature. t RISE t FALL R L = Ω, kω, kω 8
PULSE GEN. Z O = Ω t f = t r = ns INPUT V E MONITORING NODE + V ma I F SHIELD 9 8.µF BYPASS *C L R L OUTPUT V O MONITORING NODE INPUT V E OUTPUT V O t EHL t ELH. V. V. V *C L IS APPROXIMATELY pf WHICH ILUDES PROBE AND STRAY WIRING CAPACITAE. Figure. Test circuit for t EHL and t ELH. te - ENABLE PROPAGATION DELAY - ns 8 V CC =. V V EH =. V V EL =. V I F =. ma t ELH, R L = kω t ELH, R L = kω t ELH, R L = Ω, kω, kω - - - 8 Figure. Typical enable propagation delay vs. temperature. t ELH, R L = Ω 9
I F V FF B A SINGLE CHANNEL SHIELD V CM + PULSE GENERATOR Z O = Ω. µf BYPASS + V RL OUTPUT V O MONITORING NODE Figure. Test circuit for common mode transient immunity and typical waveforms. 9 8 V CM V O V V V O. V V CM (PEAK) SWITCH AT A: I F = ma V O (MIN.) SWITCH AT B: I F = ma V O (MAX.) CM H CM L OUTPUT POWER - PS, INPUT CURRENT - IS 9 8 P S (mw) I S (ma) T s - CASE TEMPERATURE - C Figure. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN--. V CC BUS (FRONT) GND BUS (BACK) Figure. Recommended printed circuit board layout.. µf mm MAX. (SEE NOTE ) ENABLE OUTPUT SINGLE CHANNEL DEVICE ILLUSTRATED. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. AV-EN - September,