RTU1D-2 LAICS A 1.6-to-3.2/4.8 GHz Dual Modulus Injection-Locked Frequency Multiplier in 0.18µm CMOS L. Zhang, D. Karasiewicz, B. Ciftcioglu and H. Wu Laboratory for Advanced Integrated Circuits and Systems Department of Electrical and Computer Engineering University of Rochester RFIC Atlanta June 15-17, 2008
Motivation Outline Injection-locked frequency multiplier (ILFM) Prototype design Measurement results Conclusion
Frequency Multiplier Applications LO Generation in TRx Local Clock Scaling in SoC PA N f 0 VCO IF f 0 N 1 N 1 f 0 f 0 LCD LCD N f 0 N2 N 2 f 0 LCD LO generation in RF and microwave transceivers Avoid VCO pulling Reach higher frequency than VCO Frequency scaling in local clock generation Multi-clock domain (MCD)
Effects of Undesired Harmonics for LO Signal Desired signal RF Interferer ω LNA Undesired harmonics LO IF Desired signal Interferer with undesired LO harmonics Interferer w/o undesired LO harmonics ω Exacerbate the nonlinear effects of mixer, increasing noise figure ω
Effects of Undesired Harmonics for Clock Generation Ideal clock waveform Clock waveform with second sub harmonics Time Periodic jitter that may causes logic error
Effects of Undesired Harmonics for Clock Generation Clock waveform with strong second harmonics Ideal clock waveform Time Periodic jitter that may causes logic error
Conventional Frequency Multipliers Band Pass Filter 3 f 0 f 0 Low Q Lossy Inductor in CMOS Harmonic generation followed by filtering Undesired harmonics suppressed Output power direct proportional to harmonic generator power
Harmonic Suppression vs. Q Harmonic suppressions of a parallel LC filter (db) 30 25 20 15 Fundamental suppression 2 nd order suppression 2 f 0 f 0 3 f 0 4 f 0 5 f 0 10 5 2 3 4 5 6 7 8 9 10 Q Suppression of undesired harmonics proportional to the quality factor of the filter network For CMOS implementations, low Q passive devices means poor undesired harmonics suppression
Injection-Locked Frequency Multiplier (ILFM) f 0 Band Pass Filter Low Q ILO 3 f 0 Harmonic Generator ILO act as a high-q, high-gain band pass amplifier after the harmonic generator Achieves good undesired harmonic suppression with low Q passive devices Decouples output power and harmonic generator power
Harmonic Suppression in ILFM Resonator spectrum res ω Line width compression Oscillator spectrum osc ω 0 res ~ ω Q 1 k T ω B 0 osc ~ 2 v0 C QL Harmonics suppression improves when replace the resonator with an ILO Donhee Ham, IEEE JSSC, March 2003.
Pros & Cons Better suppression of undesired harmonics Capable of multi-modulus operation Decouples output power with harmonic generator power Capable of implementation on lossy processes like CMOS without performance degradation
Dual-Modulus ILFM L 1 Buffer Modulus Control C s1 V out M M 2 3 V in R 1 Harmonic Generator M 1 C t1 C s2 T 1 ILO M tail V bias Multiply by 2/3 by modulus control
Chip Photo Ou utput Osc M 1 T 1 Input 100um Core circuitry occupies only 0.4 by 0.1 mm 2
Doubler Output Spectrum Spect trum (dbm) -10-20 -30-40 -50-60 -70-80 42dB -90 0 1 2 3 4 5 Frequency (GHz) -10-50 -100 3.195 3.205 Measured at 5% locking range.
Tripler Output Spectrum Spec ctrum (dbm) -10-20 -30-40 -50-60 -70-80 40dB 32dB -90 0 1 2 3 4 5 Frequency (GHz) -10-50 -100 4.795 4.805 Measured at 5% locking range.
Output Harmonics vs. Input Output Harmon nics Power (dbm) -10-20 -30-40 -50-60 -70-80 Doubler -10-20 1 st (input) 2 nd (output) 3 rd -30 4 th 5 th -40 0.4 0.5 0.6 0.7 0.8 0.9 1 Input Amplitude (V) -50-60 -70-80 1 st (input) 2 nd 3 rd (output) 4 th 5 th Tripler 0.4 0.5 0.6 0.7 0.8 0.9 1 Input Amplitude (V) Output harmonics strength increases as the input increases
Harmonic Suppression (db) 70 60 50 40 30 Harmonic Suppression vs. Input Doubler 70 1 st 3 rd 4 th 60 5 th 50 40 30 Tripler 1 st 2 nd 4 th 5 th 20 0.4 0.5 0.6 0.7 0.8 0.9 1 Input Amplitude (V) 20 0.4 0.5 0.6 0.7 0.8 0.9 1 Input Amplitude (V) Harmonic suppressions reduce as input increases
Locking Range Bounds of Loc cking Range (GHz) 5.2 5 4.8 4.6 4.4 4.2 3.8 3.6 3.4 3.2 3 Upper Bound Lower Bound Locking Range Upper Bound Lower Bound Locking Range Tripler Doubler 14 12 10 8 6 4 2 0 35 30 25 20 15 10 Locking Range (%) 2.8 5 2.6 0 0.4 0.5 0.6 0.7 0.8 0.9 1 Input Amplitude (V) Locking ranges increase with input
Power & Locking Range Tradeoff 35 30 Doubler Tripler Range (%) Locking 25 20 15 10 5 0 1 2 3 4 5 6 7 8 9 Power Consumption (mw) Locking range and power consumption both proportional to injection level.
-40-50 -60-70 Phase Noise Measured input Doubler Tripler Doubler freerun Tripler freerun Phase Noi ise (dbc) -80-90 -100-110 -120-130 60dB Noise floor of spectrum analyzer -140-150 Ideal phase noise of signal source from the manual -160 10 3 10 4 10 5 10 6 10 7 Offset Frequency (Hz)
Performance Comparison Ref Process xn f out (GHz) BW Pdc (mw) V 1 /V 2,3 (db) V 2 /V 3 (db) Chip size * (mm 2 ) This work* 1 CMOS x2 3.2 5 2.2 42 NA 0.1 0.4 This work* 2 CMOS x3 4.8 5 3.7 40 32 0.1 0.4 [7] CMOS x2 5 NA 12.6 20 NA 0.6 0.6 [8] SOI CMOS x2 5.2 7.4 10 11 NA 0.29 0.13 [1] SiGe x3 60 NA 54 25 NA NA [5] SiGe HBT x2 16 27 22 25 NA 0.7 0.35 [5] SiGe HBT x2 36 13 95 35 NA 0.7 0.5 [6] InGaAs PHEMT x3 36 NA 18.9 21.4 22.3 2 2.5 [11] InGaP HBT x2 16 46 200 25 NA 0.7 0.4 [12] SiGe HBT x2 30 51 185 22 NA 0.45 0.55 [13] [14] GaAs PHEMT GaAs HEMT x2 56 19 70 29 NA 1.4 0.64 x2 56 21 275 23 NA 1.6 1.2 * without pads
Conclusion A dual modulus injection-locked frequency multiplier (ILFM) topology proposed; The new topology achieves good suppression on undesired harmonics on lossy CMOS process; A circuit prototype for 1.6-to-3.2/4.8 GHz operation fabricated and measured to demonstrate the new ILFM topology.
Acknowledgement National Semiconductor Bijoy Chatterjee, Peter Holloway, Babatunde Akinpelu, Peter Misich, Carlos Hinojosa, Jun Wan, Sonnet Software LAICS members Yunliang Zhu, Jianyun Hu, Shang Wang
RTU1D-2 LAICS Thank you! www.ece.rochester.edu/research/laics/