HEXFET Power MOSFET PD - 9.23 IRFP450LC Ultra Low Gate Charge Reduced Gate Drive Requirement Enhanced 30V V gs Rating Reduced C iss, C oss, C rss Isolated Central Mounting Hole Dynamic dv/dt Rated Repetitive valanche Rated V DSS = 500V R DS(on) = 0.40Ω I D = 4 Description This new series of Low Charge HEXFET Power MOSFETs achieve significantly lower gate charge over conventional MOSFETs. Utilizing advanced Hexfet technology the device improvements allow for reduced gate drive requirements, faster switching speeds and increased total system savings. These device improvements combined with the proven ruggedness and reliability of HEXFETs offer the designer a new standard in power transistors for switching applications. The TO-247 package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220 devices. The TO-247 is similar but superior to the earlier TO-28 package because of its isolated mounting hole. bsolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 4 I D @ T C = 00 C Continuous Drain Current, V GS @ 0V 8.6 I DM Pulsed Drain Current 56 P D @T C = 25 C Power Dissipation 90 W Linear Derating Factor.5 W/ C V GS Gate-to-Source Voltage ±30 V E S Single Pulse valanche Energy 760 mj I R valanche Current 4 E R Repetitive valanche Energy 9 mj dv/dt Peak Diode Recovery dv/dt 3.5 V/ns T J Operating Junction and -55 to + 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case) Mounting torque, 6-32 or M3 screw. 0 lbf in (.N m) Thermal Resistance Parameter Min. Typ. Max. Units R θjc Junction-to-Case 0.65 R θcs Case-to-Sink, Flat, Greased Surface 0.24 C/W R θj Junction-to-mbient 40 Revision 0
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 500 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.59 V/ C Reference to 25 C, I D = m R DS(ON) Static Drain-to-Source On-Resistance 0.40 Ω V GS = 0V, I D = 8.4 V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 8.7 S V DS = 50V, I D = 8.4 25 V DS = 500V, V GS = 0V I DSS Drain-to-Source Leakage Current µ 250 V DS = 400V, V GS = 0V, T J = 25 C Gate-to-Source Forward Leakage 00 V GS = 20V I GSS n Gate-to-Source Reverse Leakage -00 V GS = -20V Q g Total Gate Charge 74 I D = 4 Q gs Gate-to-Source Charge 9 nc V DS = 400V Q gd Gate-to-Drain ("Miller") Charge 35 V GS = 0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 4 V DD = 250V t r Rise Time 49 I D = 4 ns t d(off) Turn-Off Delay Time 30 R G = 6.2Ω t f Fall Time 30 R D = 7Ω, See Fig. 0 Between lead, L D Internal Drain Inductance 5.0 6mm (0.25in.) nh from package L S Internal Source Inductance 3 and center of die contact C iss Input Capacitance 2200 V GS = 0V C oss Output Capacitance 320 pf V DS = 25V C rss Reverse Transfer Capacitance 28 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol 4 (Body Diode) showing the I SM Pulsed Source Current integral reverse 56 (Body Diode) p-n junction diode. V SD Diode Forward Voltage.4 V T J = 25 C, I S = 4, V GS = 0V t rr Reverse Recovery Time 580 870 ns T J = 25 C, I F = 4 Q rr Reverse Recovery Charge 5. 7.7 µc di/dt = 00/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) I SD 4, di/dt 30/µs, V DD V (BR)DSS, T J 50 C V DD = 25V, starting T J = 25 C, L = 7.0mH R G = 25Ω, I S = 4. (See Figure 2) Pulse width 300µs; duty cycle 2%.
I, Drain-to-Source Current () D 00 0 0. VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I, Drain-to-Source Current () D 00 0 0. VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0.0 T C = 25 C 0.0 0. 0 00 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH 0.0 T C = 50 C 0.0 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics, T C = 25 o C Fig 2. Typical Output Characteristics, T C = 50 o C I D, Drain-to-Source Current () 00 0 0. T J= 50 C T J = 25 C R DS(on), Drain-to-Source On Resistance (Normalized) V DS = 50V 20µs PULSE WIDTH V 0.0 GS = 0V 0.0 4 5 6 7 8 9 0-60 -40-20 0 20 40 60 80 00 20 40 60 V GS, Gate-to-Source Voltage (V) 3.0 2.5 2.0.5.0 0.5 I D = 4 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature
C, Capacitance (pf) 4000 3000 2000 000 V GS = 0V, f = MHz C iss = C gs + C gd, C ds SHORTED C rss = Cgd C oss = C ds + C gd C iss C oss C rss 0 0 00 V DS, Drain-to-Source Voltage (V) V, Gate-to-Source Voltage (V) GS 20 6 2 8 4 0 I D = 4 V = 400V DS V = 250V DS V DS = 00V FOR TEST CIRCUIT SEE FIGURE 3 0 20 40 60 80 Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () 00 000 OPERTION IN THIS RE LIMITED BY RDS(on) 00 0 0µs T J = 50 C 0 00µs T J = 25 C ms 0ms T C = 25 C T J = 50 C V GS = 0V Single Pulse 0. 0. 0.0 0.4 0.8.2.6 2.0 0 00 000 V SD, Source-to-Drain Voltage (V) I D, Drain Current () V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea
V DS R D 4 2 R G V GS D.U.T. V DD I D, Drain Current (mps) 0 8 6 4 0 V Pulse Width µs Duty Factor 0. % Fig 0a. Switching Time Test Circuit 2 0 25 50 75 00 25 50 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 0b. Switching Time Waveforms Thermal Response (Z thjc ) 0. 0.0 D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) 2. P e ak T J = P D M x Z th JC + T C 0.00 0.0000 0.000 0.00 0.0 0. 0 t, Rectangular Pulse Duration (sec) N o tes :. D u ty fa c tor D = t / t 2 PDM t t 2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0 V Fig 2a. Unclamped Inductive Test Circuit Fig 2b. Unclamped Inductive Waveforms E S, Single Pulse valanche Energy (mj) 600 200 800 400 ID TOP 6.3 8.9 BOTTOM 4 V DD = 50V 0 25 50 75 00 25 50 Starting T J, Juntion Temperature ( C) Fig 2c. Maximum valanche Energy Vs. Drain Current 0 V Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit
Peak Diode Recovery dv/dt Test Circuit D.U.T Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD * * VGS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS
IRF450LC Package Outline TO-247C Part Marking Information TO-247C EXMPLE : THIS IS N IRFPE30 WITH SSEMBLY LOT CODE 3Q INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFPE30 3Q 9302 PRT NUMBER DTE CODE (YYWW) YY = YER WW WEEK WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (30) 322 333 EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: (44) 0883 7325 IR CND: 732 Victoria Park ve., Suite 20, Markham, Ontario L3R 3L, Tel: (905) 475 897 IR GERMNY: Saalburgstrasse 57, 6350 Bad Homburg Tel: 672 37066 IR ITLY: Via Liguria 49, 007 Borgaro, Torino Tel: (39) 45 0 IR FR EST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo 7 Tel: (03)3983 064 IR SOUTHEST SI: 35 Outram Road, #0-02 Tan Boon Liat Building, 036 Tel: 65 22 837 Data and specifications subject to change without notice.