SMP4 SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ = +. V, = DGND = V, R L = No Load, T A = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Units Linearity Error. % Buffer Offset Voltage V OS V IN = 6 V ±.5 + mv Hold Step V HS V IN = 6 V, T A = +5 C to +85 C.5 4 mv V IN = 6 V, T A = 4 C 5 mv Droop Rate V/ t V IN = 6 V, T A = +5 C 5 mv/s Output Source Current I SOURCE V IN = 6 V. ma Output Sink Current I SINK V IN = 6 V.5 ma Output Voltage Range OVR R L = kω.6. V R L = kω.6 9.5 V LOGIC CHARACTERISTICS Logic Input High Voltage V INH.4 V Logic Input Low Voltage V INL.8 V Logic Input Current I IN.5 µa DYNAMIC PERFORMANCE Acquisition Time t AQ T A = +5 C, V to V Step to.%.5 4.5 µs 4 C T A +85 C.75 5.5 µs Acquisition Time t AQ T A = +5 C, V to V Step to.% 9 µs Hold Mode Settling Time t H To mv µs Slew Rate 4 SR R L = kω 4 V/µs Capacitive Load Stability C L <% Overshoot 5 pf Analog Crosstalk V to V Step 8 db SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR.8 V. V 6 75 db Supply Current I DD 4 7 ma Power Dissipation P DIS 84 mw ELECTRICAL CHARACTERISTICS (@ = +5. V, = 5. V, DGND =. V, R L = No Load, T A = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Units Linearity Error. % Buffer Offset Voltage V OS V IN = V ±.5 + mv Hold Step V HS V IN = V, T A = +5 C to +85 C.5 4 mv V IN = V, T A = 4 C 5 mv Droop Rate V/ t V IN = V, T A = +5 C 5 mv/s Output Resistance R OUT Ω Output Source Current I SOURCE V IN = V. ma Output Sink Current I SINK V IN = V.5 ma Output Voltage Range OVR R L = kω. +. V LOGIC CHARACTERISTICS Logic Input High Voltage V INH.4 V Logic Input Low Voltage V INL.8 V Logic Input Current I IN.5 µa DYNAMIC PERFORMANCE Acquisition Time t AQ V to + V Step to.%.6 µs Acquisition Time t AQ V to + V Step to.% 9 µs Hold Mode Settling Time t H To mv µs Slew Rate 5 SR R L = kω V/µs Capacitive Load Stability C L <% Overshoot 5 pf SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR ± 5 V ± 6 V 6 75 db Supply Current I DD.5 5.5 ma Power Dissipation P DIS 55 mw NOTES Outputs are capable of sinking and sourcing over ma, but linearity and offset are guaranteed at specified load levels. All input control signals are specified with t R = t F = 5 ns (% to 9% of +5 V) and timed from a voltage level of.6 V. This parameter is guaranteed without test. 4 Slew rate is measured in the sample mode with a V to V step from % to 8%. 5 Slew rate is measured in the sample mode with a V to + V step from % to 8%. Specifications are subject to change without notice.
SMP4 ABSOLUTE MAXIMUM RATINGS (T A = +5 C unless otherwise noted) to DGND............................ V, 7 V to..............................7 V, 7 V V LOGIC to DGND......................... V, V IN to DGND.............................., V OUT to DGND............................., Analog Output Current....................... ± ma (Not Short-Circuit Protected) Digital Input Voltage to DGND........ V, +. V Operating Temperature Range EQ, EP, ES........................ 4 C to +85 C Junction Temperature.........................+5 C Storage Temperature.................. 65 C to +5 C Lead Temperature (Soldering, 6 sec)............+ C PIN CONNECTIONS 6-Lead Cerdip 6-Lead Plastic DIP 6-Lead SO V OUT V OUT 6 5 V OUT V IN NC 4 SMP4 4 V OUT4 V IN S/H 5 6 TOP VIEW (Not to Scale) V IN4 V IN S/H 7 S/H 4 DGND 8 9 S/H Package Type JA * JC Units 6-Lead Cerdip 94 C/W 6-Lead Plastic DIP 76 C/W 6-Lead SO 9 7 C/W * JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and plastic DIP packages; JA is specified for device soldered to printed circuit board for SO package. CAUTION. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; function operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability.. Digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures.. Remove power before inserting or removing units from their sockets. ORDERING GUIDE Temperature Package Package Model Range Description Options* SMP4EQ 4 C to +85 C Cerdip-6 Q-6 SMP4EP 4 C to +85 C PDIP-6 N-6 SMP4ES 4 C to +85 C SO-6 R-6A *Q = Cerdip; N = Plastic DIP; R = Small Outline. NC = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP4 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE
SMP4 V OUT V OUT V OUT V OUT4 V IN V IN V IN4 V IN S/H S/H DGND S/H S/H 4 Dice Characteristics Die Size:.8 x. mil = 9,6 sq. mil (. x.48mm = 6.9 sq. mm) WAFER TEST LIMITS (@ = + V, = DGND = V, R L = No Load, T A = +5 C, unless otherwise noted.) SMP4G Parameter Symbol Conditions Limits Units Buffer Offset Voltage V OS V IN = +6 V ± mv max Hold Step V HS V IN = +6 V ± 4 mv max Droop Rate V/ t V IN = +6 V 5 mv/s max Output Source Current I SOURCE V IN = +6 V. ma min Output Sink Current I SINK V IN = +6 V.5 ma min Output Voltage Range OVR R L = kω.6/. V min/max R L = kω.6/9.5 V min/max LOGIC CHARACTERISTICS Logic Input High Voltage V INH.4 V min Logic Input Low Voltage V INL.8 V max Logic Input Current I IN µa max SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR.8 V. V 6 db min Supply Current I DD 7 ma max Power Dissipation P DIS 84 mw max NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 4
Typical Performance Characteristics SMP4 DROOP RATE mv/s = V V IN = +5V R L = k DROOP RATE mv/s 5 = V DROOP RATE mv/s 8 6 4 8 = V 55 5 5 5 5 45 65 85 5 5 TEMPERATURE C Figure. Droop Rate vs. Temperature 5 4 5 6 7 8 9 INPUT VOLTAGE Volts Figure. Droop Rate vs. Input Voltage (T A = +5 C) 6 4 5 6 7 8 9 INPUT VOLTAGE Volts Figure. Droop Rate vs. Input Voltage (T A = +5 C) HOLD STEP mv T A = +5 C = V HOLD STEP mv = V V IN = +5V SLEW RATE V/ s 7 6 5 4 T A = +5 C = V SR +SR 4 5 6 7 8 9 INPUT VOLTAGE Volts Figure 4. Hold Step vs. Input Voltage 55 5 5 5 5 45 65 85 5 5 TEMPERATURE C Figure 5. Hold Step vs. Temperature 4 5 6 7 8 Volts Figure 6. Slew Rate vs. OFFSET VOLTAGE mv R L = R L = k = V R L = k OFFSET VOLTAGE mv 5 5 5 5 R L = R L = k = V R L = k OFFSET VOLTAGE mv 4 4 6 8 R L = R L = k = V R L = k 4 4 5 6 7 8 9 INPUT VOLTAGE Volts Figure 7. Offset Voltage vs. Input Voltage (T A = +5 C) 4 5 6 7 8 9 INPUT VOLTAGE Volts Figure 8. Offset Voltage vs. Input Voltage (T A = +5 C) 4 5 6 7 8 9 INPUT VOLTAGE Volts Figure 9. Offset Voltage vs. Input Voltage (T A = 55 C) 5
SMP4 OFFSET VOLTAGE mv 4 = V V IN = +5V R L = k 5 55 5 5 5 45 65 85 5 5 TEMPERATURE C Figure. Offset Voltage vs. Temperature SUPPLY CURRENT ma 7 6 5 4 = V R L = +5 C +5 C 55 C 4 6 8 4 6 8 Volts Figure. Supply Current vs. REJECTION RATIO db 9 8 7 6 5 4 PSSR = V V IN = +6V +PSSR k k k M FREQUENCY Hz Figure. Sample Mode Power Supply Rejection GAIN db 4 GAIN PHASE 9 45 45 9 5 8 PHASE SHIFT Degrees OUTPUT IMPEDANCE 5 5 5 5 PEAK-TO-PEAK OUTPUT Volts 5 9 6 T A = +5 C = +6V = 6V 5 5 k k k M M FREQUENCY Hz Figure. Gain, Phase Shift vs. Frequency k k k M FREQUENCY Hz Figure 4. Output Impedance vs. Frequency k k M M FREQUENCY Hz Figure 5. Maximum Output Voltage vs. Frequency 6
SMP4 GENERAL INFORMATION The SMP4 is a quad sample-and-hold with each track-andhold having its own input, output, control, and on-chip hold capacitor. The combination of four high performance track-andhold capacitors on a single chip greatly reduces board space and design time while increasing reliability. After the device selection, the primary considerations in using track-and-holds are the hold capacitor and layout. The SMP4 eliminates most of these problems by having the hold capacitors internal, eliminating the problems of leakage, feedthrough, guard ring layout and dielectric absorption. POWER SUPPLIES The SMP4 is capable of operating with either single or dual supplies over a voltage range of 7 to 5 volts. Based on the supply voltages chosen, and establish the output voltage range, which is: +.5 V V OUT V Note that several specifications, including acquisition time, offset and output voltage compliance will degrade for a total supply voltage of less than 7 V. Positive supply current is typically 4 ma with the outputs unloaded. The SMP4 has an internally regulated TTL supply so that TTL/CMOS compatibility will be maintained over the full supply range. Single Supply Operation Grounding Considerations In single supply applications, it is extremely important that the (negative supply) pin be connected to a clean ground. This is because the hold capacitor is internally tied to. Any noise or disturbance in the ground will directly couple to the output of the sample-and-hold, degrading the signal-to-noise performance. It is advisable that the analog and digital ground traces on the circuit board be physically separated to reduce digital switching noise from entering the analog circuitry. Power Supply Bypassing For optimum performance, the supply pin must also be bypassed with a good quality, high frequency ceramic capacitor. The recommended value is. µf. In the case where dual supplies are used, (negative supply) bypassing is particularly important. Again this is because the internal hold capacitor is tied to. Good bypassing prevents high frequency noise from entering the sample-and-hold amplifier. A. µf ceramic bypass capacitor is generally sufficient. For high noise environments, adding a µf tantalum capacitor in parallel with the. µf provides additional protection. Power Supply Sequencing It may be advisable to have the turn on prior to having logic levels on the inputs. The SMP4 has been designed to be resistant to latch-up, but standard precautions should still be taken. OUTPUT BUFFERS (Pins,, 4 and 5) The buffer offset specification is ± mv; this is less than / LSB of an 8-bit DAC with V full scale. Change in offset over the output range is typically mv. The hold step is the magnitude of the voltage step caused when switching from sample-to-hold mode. This error is sometimes referred to as the pedestal error or sample-to-hold offset, and is about mv with little variation. The droop rate of a held channel is µv/ms typical and ± 5 µv/ ms maximum. The buffers are designed primarily to drive loads connected to ground. The outputs can source more than. ma each, over the full voltage range and maintain specified accuracy. In split supply operation, symmetrical output swings can be obtained by restricting the output range to V from either supply. On-chip SMP4 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capacitive loads up to 5 pf. However, since the SMP4 s buffer outputs are not short-circuit protected, care should be taken to avoid shorting any output to the supplies or ground. SIGNAL INPUT (Pins, 5, and ) The signal inputs should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP4 s fast acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails ( V IN ) to avoid the possibility of setting up a latch-up condition. The internal hold capacitance is typically 6 pf and the internal switch ON resistance is kω. If single supply operation is desired, op amps such as the OP8 or AD8, that have input and output voltage compliances including ground, can be used to drive the inputs. Split supplies, such as ±7.5 V, can be used with the SMP4 and the above mentioned op amps. APPLICATION TIPS All unused digital inputs should be connected to logic LOW and the analog inputs connected to analog ground. For connectors or driven analog inputs that may become temporarily disconnected, a resistor to or analog ground should be used with a value ranging from. MΩ to MΩ. Do not apply signals to the SMP4 with power off unless the input current s value is limited to less than ma. Track-and-holds are sensitive to layout and physical connections. For the best performance, the SMP4 should not be socketed. 7
SMP4 FREQUENCY DOMAIN PERFORMANCE The SMP4 has been characterized in the frequency domain for those applications that require capture of dynamic signals. See Figure 6a for typical 86. khz sample rate and an 8 khz input signal. Typically, the SMP4 can sample at rates up to 85 khz. In addition to the maximum sample rate, a minimum sample pulsewidth will also be acceptable for a given design. Our testing shows a drop in performance as the sample pulsewidth becomes less than 4 µs. db/div RANGE 5. dbm 6. dbm START. Hz a. db/div RANGE 5. dbm 6. dbm START. Hz STOP. Hz STOP. Hz b. Figure 6. Spectral Response at a Sampling Frequency of 86 khz. Photo (a) Shows a khz Carrier Frequency and Photo (b) Shows an 8 khz Frequency. Optimizing Dynamic Performance of the SMP4 Various operating parameters such as input voltage amplitude, sampling pulsewidth and, as mentioned before, supply bypassing and grounding all have an effect on the signal-to-noise ratio. Table I shows the SNR versus input level for the SMP4. Distortion of the SMP4 is reduced by increasing the supply voltage. This has the effect of increasing the positive slew rate. Table II shows data taken at. khz sample rate and khz input frequency. Total harmonic distortion is dominated by the second and third harmonics. Table III shows the effect of sampling pulsewidth on the SNR of the SMP4. The recommended operating pulsewidth should be a minimum of 5 µs to achieve a good balance between acquisition time and SNR for the.4 V p-p signal shown. For larger swings the pulsewidth will need to be larger to account for the time required for the signal to slew the additional voltage. This could be used as a method of measuring acquisition time indirectly. Table I. SNR vs. V IN Input Voltage SNR (V p-p) (db) 6 5 5 4 47 5 45 6 44 Conditions: V S = ± 6 V, f S = 4.4 khz, f IN =.8 khz, t PW = µs. Table II. SNR vs. Supply Voltage Supply Voltage nd rd (V) (db) (db) 49 6 55 7 4 6 8 5 6 < 8 6 6 < 8 7 65 < 85 Table III. SNR vs. Sample Pulsewidth Sample Pulsewidth ( s) SNR (db) 7 44 5 4 54 5 54.9 6 55 7 55. Conditions: V S = ± 6 V, V IN =.4 V p-p, f S = 4.4 khz, f IN =.8 khz. 8
SMP4 Sample-Mode Distortion Characteristics Although designed as a sample-and-hold, the SMP4 may be used as a straight buffer amplifier by configuring it in a continuous sample mode. This is done by connecting the S/H control pin to a logic LOW. Its buffer bandwidth is primarily limited by the distortion content as the signal frequency increases. Figure 7 shows the distortion characteristics of the SMP4 versus frequency. It maintains less than % total harmonic distortion over a voiceband of 8 khz. Output spot noise voltage measures 4 nv/ Hz at f = khz. different sampling frequencies of 4.4 khz, 9.6 khz and 7. khz. The signal-to-noise ratios measure 58. db, 59. db and 6 db respectively. Figure 9 depicts SMP4 s spectral response operating with voice frequency of khz sampling at a 5.7 khz rate. Under this condition, the signal-to-noise measures 5 db. db/div RANGE 5. dbm 5.9 dbm V S = 6V V IN = 4Vp-p THD + NOISE %....5 k k k k FREQUENCY Hz Figure 7. THD+N vs. Frequency Sampled Data Dynamic Performance In continuous sampled data applications such as voice digitization or communication circuits, it is important to analyze the spectral response of a sample-and-hold. Figures 6a and 6b show the SMP4 sampling at a frequency of 86 khz with a.4 V p-p pure sine wave input of khz and 8 khz respectively. The photos include the sampling carrier frequency as well as its multiplying frequencies. In the case of the khz carrier frequency, the second harmonic measures 4 db down from the fundamental, because the second is dominant, the signal-to-noise ratio is 4.9 db. The 8 khz case produces an improved S/N performance of 48 db. In the V. and V. modem environment, where a.8 khz carrier signal frequency is applied to the SMP4, Figure 8 compares the spectral responses of the SMP4 under three START. Hz STOP. Hz Figure 9. SMP4 Spectral Response with an Input Carrier Frequency of khz and the Sampling Frequency of 5.7 khz Sampled Data Dynamic Performance In continuous sampled data applications such as voice digitization or communication circuits, it is important to analyze the spectral response of a sample-and-hold. Figures 6a and 6b show the SMP4 sampling at a frequency of 86 khz with a.4 V p-p pure sine wave input of khz and 8 khz respectively. The photos include the sampling carrier frequency as well as its multiplying frequencies. In the case of the khz carrier frequency, the second harmonic measures 4 db down from the fundamental, because the second is dominant, the signal-tonoise ratio is 4.9 db. The 8 khz case produces an improved S/N performance of 48 db. In the V. and V. modem environment, where a.8 khz carrier signal frequency is applied to the SMP4, Figure 8 compares the spectral responses of the SMP4 under three different sampling frequencies of 4.4 khz, 9.6 khz and 7. khz. The signal-to-noise ratios measure 58. db, 59. db and 6 db respectively. db/div RANGE 5. dbm 5.9 dbm db/div RANGE 5. dbm 5.7 dbm db/div RANGE 5. dbm 5. dbm CENTER 5. Hz SPAN 9. Hz START. Hz STOP. Hz START. Hz STOP. Hz a. b. c. Figure 8. SMP4 Spectral Response with a.8 khz Carrier Frequency. (a) Shows the Sampling Frequency at 4.4 khz; it Exhibits a S/N Ratio of 58. db. (b) Shows a 59. db S/N at a Sampling Frequency of 8.6 khz. (c) Shows a 6 db S/N at 7. khz. 9
SMP4 APPLICATIONS MULTIPLEXED QUAD DAC (Figure ) The SMP4 can be used to demultiplex a single DAC converter s output into four separate analog outputs. The circuit is greatly simplified by using a voltage output DAC such as the DAC88. To minimize output voltage perturbation, 5 µs should be allowed to settle to its final voltage before a sample signal is asserted. Each sample-and-hold amplifier must be refreshed every second or less in order to assure the droop does not exceed mv or / LSB. +V F + +V. F REF +5V SMP4 +V V OUT WR V Z / DAC88 V O 5V TO V V OUT CS V REF GND V OUT DIGITAL INPUTS ADDRESS INPUTS CHANNEL DECODE S/H S/H S/H V OUT4 S/H 4 Figure. Multiplexed Quad DAC DGND
SMP4 V IN (.5V) RESET AMPLIFIER A +5V / OP 5V R k D N94 D G SD4 R D S Q +5V 5V V OUT POSITIVE PD/H POSITIVE / SMP4 AMPLIFIER B R k / OP D N94 D 4 R4 V OUT NEGATIVE G SD4 D S Q PD/H NEGATIVE DGND Figure. Positive and Negative Peak Detector with Hold Control POSITIVE AND NEGATIVE PEAK DETECTOR WITH HOLD CONTROL (Figure ) In this application the top amplifier (Amplifier A) is the positive peak detector and the bottom amplifier (Amplifier B) is the negative peak detector. Operation can be analyzed as follows: Assume that the S/H switch is closed. As a positive increasing voltage is applied to V IN, D turns on, and D turns off, closing the feedback loop around Amplifier A and the SMP4, causing the output to track the input. Conversely, in the negative peak detector circuit at the bottom, D 4 turns off and D turns on, holding the last most negative input voltage on the SMP4. This voltage is buffered to the V O(NEG) output. As V IN falls in voltage the above conditions reverse, causing the most positive peak voltage to be held at V O(POS) output. This voltage will be held until the input has a more positive voltage than the previously held peak voltage, or a reset condition is applied. An optional HOLD control can be used by applying a logic HIGH to the PD/H inputs. This HOLD mode further reduces leakage current through the reverse-biased diodes (D and D 4 ) during peak hold. GAIN OF SAMPLE-AND-HOLD (Figure ) This application places the SMP4 in a feedback loop of an amplifier. Because the SMP4 has no sign inversion and the amplifier has very high open-loop gain, the gain of the circuit is set by the ratio of the sum of the source and feedback resistances k V IN V TO.V S/H +V /4 OP49 8.66k k N94 4 /4 SMP4 +V V OUT V TO V Figure. Gain of Sample-and-Hold Amplifier to the source resistance. When a logic LOW is applied to the S/H control input, the loop is closed around the OP49, yielding a gain of (in the example shown) amplifier. When the S/H control goes HIGH, the loop opens and the SMP4 holds the last sampled voltage. The loop remains open and the output is unaffected by the input until a logic LOW is reapplied to the S/H control. The pair of back-to-back diodes from the output of the op amp to the output of the track-and-hold prevents the op amp from saturating when the track-and-hold is in the hold mode and the loop is open.
SMP4 +V INSTRUMENTATION AMP V +V V V IN (V TO 8V) V S/H R G AMP V OUT = G(V V) V 5k G = + R G S/H (DELAYED) t d / SMP4 5V OR V t t DGND Figure. Time Delta Sample-and-Difference Measurement SAMPLE AND DIFFERENCE AMPLIFIER (Figure ) This circuit uses two sample-and-holds to measure the voltage difference of a signal between two time points, t and t. The sampled voltages are fed into the differential inputs of the AMP instrumentation amplifier. A single resistor R G sets the gain of this instrumentation amplifier. Using two channels of the SMP4 in this application has the advantage of matched sample-and-hold performance, since they are both on the same chip. SINGLE SUPPLY, SAMPLING, INSTRUMENTATION AMPLIFIER (Figure 4) This application again uses two channels of the SMP4 and an instrumentation amplifier to provide a sampled difference signal. The sample-and-hold signals in this circuit are tied together to sample at the same point in time. The other two parts of the SMP4 are used as amplifiers by grounding their control lines so they are always sampling. One section is used to drive a guard to the common-mode voltage and the other to generate a +6 V reference to serve as an offset for single supply operation. + INPUT GUARD /4 SMP4 +V GAIN = 5k R G + 5k. F S/H R G AMP INPUT GUARD /4 SMP4 +V 5k REFERENCE V OUT GUARD DRIVE +V k k. F /4 SMP4 +6V REFERENCE /4 SMP4 Figure 4. + V Single Supply Sampling Instrumentation Amplifier with Guard Drive
SMP4 +5V. F +5V A A V REF OUT. F F CERAMIC DB 9 MSB /4 DAC846 DAC C OUT V IN V OUT -BIT COUNTER DB DB 9 DB LSB AGND DGND WR S/H /4 SMP4 ANALOG RETURN DGND F CLOCK GENERATOR DIGITAL RETURN DB +5V AGND DB /4 AD74 DEGLITCH LOGIC /4 AD74 Figure 5. DAC Deglitcher D/A CONVERTER DEGLITCHER Most D/A converters output an appreciable amount of glitch energy during a transition from one code to another. The glitch amplitude can range from several millivolts to hundreds of millivolts. This may become unacceptable in many applications. By selectively delaying the DAC s output transition, the SMP4 can be used to smooth the output waveform. Figure 5 shows the schematic diagram of such a deglitcher circuit. Two simple logic gates (an OR and a NAND gate) provide the proper timing sequence for the DAC WR strobe and the S/H control signal to the SMP4. In this example a linear ramp signal is generated by feeding the most significant eight bits of the -bit binary counter to the DAC. The two least significant bits are used to produce the delayed WR strobe and the S/H control signals. Referring to Figure 6a, new data to the DAC input is set up at the S/H s falling edge, but the DAC output does not change until a WR strobe goes active. During this period, the SMP4 is in a sample mode whose output tracks the DAC output. When S/H goes HIGH, the current DAC output voltage is held by the SMP4. After. µs settling, the WR strobe goes LOW to allow the DAC output to change. Any glitch that occurs at the DAC output is effectively blocked by the SMP4. As soon as the WR strobe goes HIGH, the digital data is latched; at the same time the S/H goes LOW, allowing the SMP4 to track to the new DAC output voltage. Figure 6b shows the deglitching operation. The top trace shows the DAC output during a transition, while the bottom trace shows the deglitched output of the SMP4. 5V 5m a. DLY s 67.4 s b. Figure 6. (a) Shows the Logic Timing of the Deglitcher. The Top Two Traces Are the Two Least Significant Bits, DB and DB, Respectively. These Are Used to Generate the WR and S/H Signals Which Are Shown in the Bottom Two Traces. (b) Shows the Typical Glitch Amplitude of a DAC (Top Trace) and the Deglitched Output of the AMP4 (Bottom Trace). s DB DB WR S/H
SMP4 V IN N-CH P-CH C H LOAD V OUT S/H LOGIC DGND Figure 7. Simplified Schematic of One Channel R 4k R4 k +5V D C F + R C F 6 5 4 R k R k 5 6 SMP4 R k R k 7 8 9 Figure 8. Burn-In Circuit 4
SMP4 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 6-Lead Cerdip (Q-6).5 (.) MIN.8 (.) MAX 6. (5.8) MAX. (5.8).5 (.8). (.58).4 (.6) 6.6 (4.6).5 (.9). (.558).4 (.56) 8 PIN.84 (.4) MAX. (.54) BSC.84 (.4).745 (8.9) 9. (7.87). (5.59).6 (.5).5 (.8).5 (.8) MIN SEATING.7 (.78) PLANE. (.76) 6-Lead Plastic DIP (N-6) 8 9.8 (7.).4 (6.) PIN.6 (.5). (5.).5 (.8) MAX..574 (4.).497 (.8).98 (.5).4 (.). (.54) BSC 6 9 PIN.97 (.).859 (9.8) (.) MIN.7 (.77) SEATING.45 (.5) PLANE 6-Lead SO (R-6A) 8.44 (6.).84 (5.8).688 (.75).5 (.5) 5. (8.).9 (7.7).5 (.8).8 (.).5 (8.6). (7.6).95 (4.95).5 (.9).5 (.8).8 (.4).96 (.5).99 (.5) x 45 PRINTED IN U.S.A. C 4/98 SEATING PLANE.5 (.7) BSC.9 (.49).8 (.5) 8.99 (.5).75 (.9).5 (.7).6 (.4) 5