TSEK38: Radio Frequency Transceiver Design Lecture 7: Receiver Synthesis (II) Ted Johansson, ISY ted.johansson@liu.se
Systematic Receiver Synthesis (II) 4.3 Intermodulation characteristics Phase noise degradation 4.5 Adjacent and alternate channel selectivity 4.5.3 Interference blocking Channel filter 4.6 Receiver Dynamic Range and AGC 4.6.3 DR and ADC 4.7 System Design 4.7.1 Basic aspects 4.7.2 Requirements, key devices 4.7.3 Performance evaluation 2
4.3.3.3 Phase noise and spur degradation 3 Phase noise (P) and spurious emissions (SP) from LO contaminate the signal. Will increase the IIPx,min. Intermodulation interference tones will mix with the LO P and/or SP and generate in-band noise and spurs, which degrades the CR. Covered by other : P + Sp <= other I in I in P(Δf) = P(2Δf)+6dB Δf = n BW -6 db/oct Δf Δf
Phase noise and spur degradation 4 P( f) = average P density over Rx BW at offset f P( Δf ) = P ( Δf ) log BW Iin [dbc/hz] P P dbm/hz P Sp = = P ( Δf ) + Iin + log BW Sp ( Δf ) + I + + (2Δf ) + I In practice, we set Sp P in Sp P (2Δf ) + Iin + log BW in I in I in -6dB/oct P(Δf) = P(2Δf)+6dB Δf = n BW Δf Δf
5 Phase noise estimation in two-tone test P + P + Sp Sp dbm 2 = 2 P ( Δf ) + Iin + log BW P ( Δf ) + Iin + log BW in + 2 1 + P (2Δf ) + Iin + log BW 6dB P ( Δf ) + Iin + log BW = log 2.5 = P( Δf ) + I + log BW + 4dB P(Δf) = P(2Δf)+6dB Other dbm Sp P 1 P ( Δf P ( Δf ) Other dbm I in = 0 + 36 61 4 log BW 4dB ) 129 dbc/hz 135dBc/Hz @ Δf with 6 db margin From this, the impact on IIP3 can be calculated (eq 4.3.51).
Phase noise estimation, IP2/Blocking test 6 SR budget under IP2 test (homodyne Rx). P+SP + TX,SM other The contribution by Tx leakage and self modulation is estimated to -7 dbm in this example (FDD). +6 db is equivalent to 2x2 Pn (P of 2 tones and 2x for LO spurs). 2-30dBm = -27dBm Iin Iin P + Sp dbm P ( f P ( f off off ) + ( I Other dbm log + 3dB) + log BW in ) 138dBm 7dBm = 1dBm + 3dB 1dBm For foff >> Δf the P approx. the same P + Sp 2 P ( f off f off ) + I in + 3dB+ logbw
4.5.3 Two-tone blocking 7 Usually IP2 test not defined by standards. Instead, blockers are specified, which can be considered as IP2 test. P Bl P Bl -3dB P Bl -3dB P IM2 f off f Bl f off f Bl P + Sp 2 P ( f off ) + P Bl + logbw P IM2 dbm = 2(P Bl 3) IIP 2,Rx (two-tone model)
Two-tone blocking 8 Usually, maximum blocker power larger than power in two-tone test. Hence, IP2 and P would be dictated by the maximum blocker rather than by a two-tone test. oise + Distortion budget: P IM 2 + P + Sp = ( S Pin / ) min F Rx ref Other Tradeoff between IP2 and the performance of LO Can present self-mixing of blocker or for FDD also Tx leakage effects (isolation on chip must be carefully considered)
9 4.5 Adjacent and alternate channel selectivity Adj and alt channel selectivity measures a receiver s ability to receive a desired signal in the presence of adjacent/alternate channel signals at a given frequency offset. (modulated) Blocking characteristics measures the same but in other channels/frequencies than the adjacent/alternate channel. (CW) Determined either by: receiver filter phase noise and spurs from LO in the adj/alt channels or around the interferer. The interference signal mixes with P and spurs, generated in-band noise and spurs, which degrades the CR.
Adjacent and alternate channel selectivity Desired signal level for blocking test is usually defined as 3 db above the reference sensitivity level Smin,ref But differently defined for adj/alt channel selectivity and also varies between different mobile systems. Ex: WCDMA, adj channel sel: 14 db above ref.sensitivity = -92.7 dbm. Allowed degradation of the allowed signal:
11 Adjacent and alternate channel selectivity ΔS is defined by the blocking profile and we must verify that the P + spurious contribution by adj/ alt channel does not violate SR min def ΔS Adj +15dB +50dB 2 Alternatively, we estimate how large P + spurious for adj/alt channel can be. P ΔS ΔS = Adj I f RF in = S in ( S / ) min = IM and self-mixing P + Sp + ref FRx I Adj in S in can be neglected here P + Sp = 2 P + I in + log BW P + Sp = P + Iin + log BW + 3dB dbm
I Adjacent and alternate channel selectivity in S SRmin 174+ log BW + = log = 94.6 P 61 3 = 155.6 P in F Rx P log BW 3dB Sin 12 I in = -38 dbm S in = -86 dbm BW = 1.25 MHz SR min = 8 db F Rx = db I I Adj Alt = 155.6 P ( BW ) = 155.6 P (2BW ) and also I I Adj Alt = 86dBm + ΔS = 86dBm + ΔS Adj Alt Assume: P(5 MHz) -135 dbc/hz (5 MHz = 4BW) (2 octaves) P drops 6 db/oct P(BW) -135 + 12 = -123 dbc/hz P(2BW) -135 + 6 = -129 dbc/hz There is much reserve on adj/alt channel selectivity ΔS ΔS Adj Alt = 53.4 db = 59.4 db while ΔS ΔS def Adj def Alt = 15dB = 50dB
13 Adjacent and alternate channel selectivity Adj/alt channel selectivity or the blocking characteristics: Example in book (AMPS): Smin = -120 dbm, ΔSadj = 41.5 db, ΔSalt = 68.5 db. Cf. requirements: Sadj > 16 db, Salt > 60 db.
4.6 Receiver Dynamic Range and AGC 14 DR = range at antenna port when BER is acceptable. Lower limit = sensitivity, upper limit = allowed maximum input power.
Receiver Dynamic Range and AGC 15 Automatic Gain Control (AGC) is needed to cover the full DR. AGC is usually > DR. E.g. CDMA >79 db, AGC range may need 0 db. Also handles gain variations because of processing deviations, temperature, supply voltage. AGC is mainly in the digital domain, but also in the LA, IF-VGA, and BB-VGA.
Receiver Dynamic Range and AGC 16
Receiver Dynamic Range and AGC 17 RF and IF gain control can be made by stepping the LA and IF-VGA gain. Low number of gain steps, typically three steps for the LA. Hysteresis (typically 3 db) is used to avoid gain switch back and forth, causing IMD products or other interferences.
Receiver Dynamic Range and AGC 18 The total gain variation of the LA and IF-VGA must cover the receiver DR, gain variation over temperature, processing, frequency, and some margin. ACG control range: GCRRx > Smax - Smin - ΔGR,T + ΔGR,process + ΔGR,f + margin GR,T = gain variation due to temperature GR,process = gain variation due to device processing GR,f = gain variation due to frequency
RX gain and AGC 19 Gain depends on ADC voltage range Vrange. Assume V range = 1.5 V, S in,min = -92 dbm, S in,max = -15 dbm 3 2 V in, pp Sin = log = 20logVin, pp + 4dB 8R0 1mW Sin,max = -15 dbm +6 db margin for PAR and gain variations = -9 dbm 20log Vin,pp = -13 dbv (max) AV, min = 20 logvrange 20logVin, pp 16. 5dB While for minimum input signal: A V,max = 20 logvrange 20logVin, min ΔA 3.5 + 96 ΔA = 99.5dB ΔA AGC = A V,max - A V,min = 83 db - ΔA ΔA = gain control of the IF-VGA (continuous)
RX gain and AGC 20 Various scenarios possible. Suppose we use AGC = 4 x 17 db + 15 db - ΔA (by simple gain stepping) ΔA = 15 db => AV,max = AV,min + AGC = 83+16.5 db dbv V out @ ADC 3.5 3.5-Δ A V,max 3.5-Δ-15 3.5-Δ-17 A V,min Hysteresis 3 db V in -96-81 -64-47 -30-13 dbv
Channel Filter 21 IF In-band blockers attenuated BPF/LPF ADC Channel selection can be completed in BB but ADC must sustain the blockers I bl A(f bl ) G LPF LPF for Zero-IF +15dB +40dB +60dB A 3 (2 nd Alt) 12 db/oct / 2 ord 18 db/oct / 3 ord 24 db/oct / 4 ord f C Blocking profile (For S in = S in,min +3dB any blocker cannot overload ADC) BW /2 3BW/2 5BW/2 7BW/2 Wanted Adjacent Alternate 2nd Alternate
Channel Filter 22 Filter attenuation: fbl A ( fbl ) n 20log, ( fbl >> ft ) f T Blocking profile: Use simple filter (n=2). ADC must maintain the max blocker and SRmin. Trade-off between filter order and ADC resolution. k BW ( 93dBV + ΔSk ) n 20log BW / 2 93dBV + ΔS n (6 + 20logk) k SR min +8dB (*) +29dB +21dB +24dB (*) The formula works well for larger k values when the filter ch-c is compliant with the linear approximation 0
4.6.3 DR and ADC 23 DR = maximum effective signal-to-(noise+distortion) Requirements set by: AGC range and step size min CR ratio in-channel band noise/interference to quantization noise PAR DC offset Fading margins Filtering (e.g. close-in interferer) Architecture dependent
DR and ADC 24 CDMA (DL): PAR = Q-noise = 12 db below in-channel-band noise min CR = -1 db (Spread Spectrum can have CR < 0 db) fading margin = 3 db => DR = 24 db GSM (superheterodyne) Q-noise = 16 db below in-channel-band noise DC offset: 4 db margin min CR = 8 db fading margins = 20 db => DR = 48 db
DR and ADC 25 DR can also be expressed in EOB CDMA: 4 bits, GSM: 8 bits, TDMA (similar to GSM): bits, EDGE: 12-13 bits. More advanced calculations of ADC DR and EOB: TSEK38_2018_L7_calculations_additionalslides.pdf in the Lectures folder, course page. ADC F pp. 286-287.
4.7 System Design, 4.7.1 Basic aspects 26 Good electrical performance, lower power consumption, low cost, small size. Trade-off between a lot of parameters, e.g. higher linearity costs more current. Highest performance is probably too good! Receiver terminal: sensitivity, intermodulation, channel selectivity, blocking, spurious emissions. Minimum requirements set by standards, with certain margins, typ. 3 db at RT and 1.5 db at max temp. frequency, voltage. Sensitivity 4-5 db, intermodulation 4 db,
Basic aspects 27 Power consumption will directly affect the operation time of a terminal. The PA is the most power hungry component. Architecture selection: Direct conversion and low-if less costly and smaller size than superheterodyne. Superheterodyne may have better performance. Fewer parts, higher integration, more standard parts, ICs costly in low volumes.
Basic aspects 28 Start with choosing a receiver architecture Fundamental receiver block diagram is developed Most important components to choose: RF BPF, RF LA, RF downconverter, UHF LO synthesizer, BB amps, BB LPF, ADC. Additional components for superheterodyne: IF filters, amplifiers, I/Q down-converter, VHF LO. All components have characteristics and must be defined to work together to achieve the full receiver specification. Link budget
Basic requirements on key devices 29 4.7.2.1 Filters Center frequency Bandwidth Insertion loss Ripple Group delay Rejection Input/output impedance Input/output return loss oise figure (IIP3 usually very high)
Basic requirements on key devices 30 4.7.2.2 LA Frequency Gain oise figure IIP3 Reverse isolation Input/output impedance Input/output return loss
Basic requirements on key devices 31 4.7.2.3 Down-Converter and I/Q Demodulator Frequency Conversion loss/gain oise Figure IIP3 IIP2 (direct-conversion) Isolation between different ports RF/IF/LO LO power Input/output impedance Input/output return loss + for I/Q: gain and phase imbalance between output ports
Basic requirements on key devices 32 4.7.2.4 IF and BB amplifiers Similar to LA, but usually less stringent, especially the BB amps IF-VGA: usually continuous adjustable BB-VGA: usually step-controlled 4.7.2.5 Synthesized LO Frequency Output power PLL: phase noise, spurious. Inband and out of band Settling time
4.7.3 Performance evaluation Line-up analysis 33 Dup /BPF LA BPF RFA BPF /LPF IFA /BBA ADC For full-duplex LO Some specs already known: Duplexer/switch loss (F) RF BPF loss (F) IP2 of downconversion mixer Mixer gain, if passive BW of filters Distribution of G, F, IIP3, (IIP2)?
Performance evaluation 34 p. 297
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In the project work, more like this 36 From calculations:
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