ACPL-MU-E Wide Operating Temperature MBd Digital Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description This small outline wide operating temperature, high CMR, high speed, logic gate optocoupler is a single channel device in a five lead miniature footprint. The ACPL-MU optically coupled gates combine a AlGaAs light emitting diode and an integrated high gain photo detector. The output of the detector IC is an Open-collector Schottky-clamped transistor. The internal shield provides a guaranteed minimum common mode transient immunity specification of, V/μs at V CM =V. This optocoupler is suitable for use in industrial high speed communications logic interfacing with low propagation delays, input/output buffering and is recommended for use in high operating temperature environment. This unique design provides maximum AC and DC circuit isolation while achieving TTL compatibility. The optocoupler AC and DC operational parameters are guaranteed from - C to 2 C. Functional Diagram Features High Temperature and Reliability CANBus communication interface for Industrial Application. Min kv/µs High Common-Mode Rejection at V CM = V Compact, Auto-Insertable SO Packages Wide Temperature Range: - C ~ 2 C High Speed: MBd (Typical) Low LED Drive Current:.mA (typ) Low Propagation Delay: ns (max) Worldwide Safety Approval: - UL 77, 7 V RMS / min. - CSA File CA882, Notice # - IEC/EN/DIN EN 77--2 Applications CANBus Communications Interface High Temperature Digital Signal Isolation Micro-controller Interface Digital isolation for A/D, D/A conversion ANODE V CC CATHODE GND The connection of a. μf bypass capacitor between pins and is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information Part number ACPL-MU Option RoHS Compliant Package Surface Mount Gull Wing Tape & Reel UL Vrms/ Minute rating IEC/EN/DIN EN 77--2 Quantity -E X X per tube SO- -E X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-MU-E to order product of SO- Surface Mount package in Tape and Reel packaging with RoHS compliant. Example 2: ACPL-MU-E to order product of SO- Surface Mount package in tube packaging with RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Schematic Land Pattern Recommendation + I CC V CC. (.7) I O 2. (.). (.) - SHIELD USE OF A. µf BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS AND (SEE NOTE ). GND TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H 2. (.8) 8.27 (.2) Dimensions in millimeters and (inches). (.2) 2
Package Outline Drawings ACPL-MU-E Small Outline SO- Package (JEDECMO-). ±. (.7 ±.) MU YWW 7. ±.2 (.27 ±.8) ANODE V CC UT CATHODE GND. ±.* (.2 ±.). ±. (. ±.2) 2. ±. (.98 ±.).2 ±.2 (. ±.).2 ±.8 (.8 ±.).27 (.) BSC.7 (.28) MIN 7 MAX. DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS. mm (.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. MAX. LEAD COPLANARITY =.2 (.) Solder Reflow Temperature Profile TEMPERATURE ( C) 2 PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE 2. C ±. C/SEC. C C C ROOM TEMPERATURE Note: Non-halide flux should be used. C + C/. C 2. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. 2 C 2 2 TIME (SECONDS) SEC. SEC. SEC. PEAK TEMP. 2 C SOLDERING TIME 2 C PEAK TEMP. 2 C TIGHT TYPICAL LOOSE
Recommended Pb-Free IR Profile TEMPERATURE Tp TL Tsmax Tsmin 27 C TIME WITHIN C of ACTUAL PEAK TEMPERATURE - 2 C RAMP-UP C/SEC. MAX. ts PREHEAT to 8 SEC. 2 +/- C tp tl 2- SEC. RAMP-DOWN C/SEC. MAX. to SEC. 2 t 2 C to PEAK TIME Notes: The time from 2 C to peak temperature = 8 minutes max. T smax = 2 C, T smin = C Non-halide flux should be used Regulatory Information The ACPL-MU-E is approved by the following organizations: UL Approved under UL 77, component recognition program up to V ISO = 7 V RMS. CSA Approved under CSA Component Acceptance Notice # IEC/EN/DIN EN 77--2 Approved under: IEC 77--2:997 + A EN 77--2:2 + A DIN EN 77--2 (VDE 88 Teil 2)
IEC/EN/DIN EN 77--2 Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE /.89, Table for rated mains voltage V rms for rated mains voltage Vrms for rated mains voltage V rms I IV I III I II Climatic Classification /2/2 Pollution Degree (DIN VDE /.89) 2 Maximum Working Insulation Voltage V IORM 7 V peak Input to Output Test Voltage, Method b* V IORM x.87=v PR, % Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a* V IORM x.=v PR, Type and Sample Test, t m = sec, Partial discharge < pc V PR V peak V PR 8 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = sec) V IOTM V peak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = V R S > 9 W * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 77--2) for a detailed description of Method a and Method b partial discharge test profiles. 7 2 C ma mw Insulation and Safety Related Specifications Parameter Symbol ACPL-MU Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group (DIN VDE9) L() mm Measured from input terminals to output terminals, shortest distance through air. L(2) mm Measured from input terminals to output terminals, shortest distance path along body..8 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI 7 V DIN IEC 2/VDE Part IIIa Material Group (DIN VDE 9)
Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - 2 C Operating Temperature T A - 2 C Lead Soldering Cycle Temperature 2 C Time sec Input Current Average (avg) 2 ma 2 (% duty cycle, ms pulse width) Peak (peak) ma (<= us pulse width, ps) Transient (trans) ma Reversed Input Voltage V R V Input Power Dissipation P I mw Output Power Dissipation P O 8 mw Output Collector Current I O ma Supply Voltage (Pins -) V CC -. 7 V Output Voltage (Pins -) -. 7 V Recommended Operating Conditions Parameter Symbol Min. Max. Units Supply Voltage V CC.. V Operating Temperature T A - 2 C Input Current, Low Level L * 2 μa Input Current, High Level H ma Fan Out (RL = kω) N TTL Loads Output Pull-Up Resistor R L, Ω * The off condition can also be guaranteed by ensuring that V F (off).8volts Electrical Specifications (DC) Over recommended operating Temperature T A = - C to 2 C, unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Conditions Fig. Note Input Threshold Current I TH 2 ma Vcc =.V, Io ma, Vo =.V High Level Output Current I OH. ma Vcc =.V, Vo =.V, VF =.V Low Level Output Voltage L.. V Vcc =.V, =.ma I OL (Sinking) = ma High Level Supply Current I CCH 7.. ma Vcc =.V, = ma Low Level Supply Current I CCL 9.. ma Vcc =.V, = ma, Input Forward Voltage V F...8 V T A =2 C, = ma...9 V = ma Input Reversed Breakdown Voltage BV R V I R = ma Temperature Coefficient of Forward Voltage *All Typicals at T A = 2 C, Vcc = V. 2,, DV F /DT A -. = ma, 2
Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary Withstand Voltage* V ISO 7 V rms RH %, t = min; T A = 2 C Input-Output Resistance R I-O 2 Ω V I-O = Vdc Input-Output Capacitance C I-O. pf f = MHz; V I-O = Vdc * The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 77--2 Insulation Characteristics Table (if applicable), your equipment level safety specification, or Avago Technologies Application Note 7, Optocoupler Input-Output Endurance Voltage. Switching Specifications (AC) Over recommended temperature T A = - C to 2 C, V CC =. V, =.ma unless Otherwise Specified. 7 Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to Low Output Level Propagation Delay Time to High Output Level t PHL 7 ns T A =2 C R L = Ω, 7, 8 ns C L = pf =.ma t PLH 7 ns T A =2 C, 7, 8 ns Propagation Delay Skew t PSK ns,, Pulse Width Distortion Output Rise Time (% - 9%) Output Fall Time (% - 9%) Common Mode Transient Immunity at High Output Level Common Mode Transient Immunity at Low Output Level *All Typicals at T A = 2 C, Vcc = V. t PHL - t PLH. ns 9 t rise 2 ns t fall ns CM H kv/μs V CM =Vp-p Vo(min) = 2V = ma T A =2 C R L =Ω CM L kv/μs V CM =Vp-p Vo(max) =.8V =.ma T A =2 C R L =Ω 7,9 Notes:. Bypassing of the power supply line is required with a. µf ceramic disc capacitor adjacent to each optocoupler. The total lead length between both ends of the capacitor and the isolator pins should not exceed mm. 2. Peaking circuits may produce transient input currents up to ma, ns maximum pulse width, provided average current does not exceed 2 ma.. Device considered a two terminal device: pins and shorted together and pins, and shorted together.. In accordance with UL 77, each optocoupler is proof tested by applying an insulation test voltage V RMS for second (Leakage detection current limit, I I-O µa).. The t PLH propagation delay is measured from.2 ma point on the falling edge of the input pulse to the. V point on the rising edge of the output pulse.. The t PHL propagation delay is measured from.2 ma point on the rising edge of the input pulse to the. V point on the falling edge of the output pulse. 7. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., UT > 2. V). 8. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., UT <.8 V). 9. For sinusoidal voltages, ( dv CM /dt)max = pf CM V CM (p-p).. See application section; Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew for more information.. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the worst case operating condition range. 2. Input current derates linearly above 8 C free-air temperature at a rate of.2 ma/ C.. Input power derates linearly above 8 C free-air temperature at a rate of.7mw/ C.. Output power derates linearly above 8 C free-air temperature at a rate of.7 mw/ C. 8,9
I OH - HIGH LEVEL OUTPUT CURRENT - ua. 2. 2.. V CC =.V =.V V F =.V - - -2 2 8 2 L - LOW LEVEL OUTPUT VOLTAGE - V....2 V CC =.V =.ma I O = ma I O = 2.8mA I O = 9.mA I O =.ma. - - -2 2 8 2 Figure. High Level Output Current vs Temperature Figure 2. Low Level Output Voltage vs. Temperature - FORWARD CURRENT - ma.... V F + T A = 2 o C - OUTPUT VOLTAGE - V 2 R load = kw R load = W R load = kw V CC =V T A= 2 o C..2.... V F - Forward Voltage - VOLTS Figure. Input Current vs Forward Voltage.2...8.2.. - FORWARD INPUT CURRENT - ma Figure. Output Voltage vs Forward Input current I OL - LOW LEVEL OUTPUT CURRENT - ma 2 V CC =.V L =.V = ma, ma = ma - - -2 2 8 2 Figure. Low Level Output Current vs. Temperature 8
PULSE GEN. Z O = Ω t f = t r = ns + V INPUT MONITORING NODE R M V CC GND.µF BYPASS *C L R L OUTPUT MONITORING NODE INPUT OUTPUT t PHL t PLH =. ma =.2 ma. V *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure. Test Circuit for t PHL and t PLH tp - PROPOGATION DELAY - ns 2 8 2 V CC =.V =.ma t PLH,R L = kω t PLH,R L = Ω t PLH,R L = kω t PHL R L = Ω kω kω - - -2 2 8 2 tp - PROPOGATION DELAY - ns 9 8 7 V CC =.V T A = 2 o C t PLH,R L = Ω t PLH,R L = kω t PLH,R L = Ω t PHL R L = Ω kω kω 7 9 - PULSE INPUT CURRENT - ma Figure 7. Propagation Delay vs. Temperature Figure 8. Propagation Delay vs. Pulse Input Current PWD - PULSE WIDTH DISTORTION - ns 2 V CC =.V =.ma R L = kω R L = Ω R L = kω - - - -2 2 8 2 Figure 9. Pulse Width Distortion vs Temperature tr, tf - Rise, Fall Time - ns 2 2 V CC =.V =.ma R L = kω t RISE t FALL R L = kω R L = RL=Ω, kω, kω - - -2 2 8 2 Figure. Rise and Fall Time vs.temperature 9
V FF B A V CC GND. µf BYPASS + V Ω OUTPUT MONITORING NODE V CM V V. V SWITCH AT A: = ma SWITCH AT B: =. ma V CM (PEAK) (MIN.) (MAX.) CM H CM L + _ PULSE GENERATOR Z O = Ω Figure. Test Circuit for Common Mode Transient Immunity and Typical Waveforms dvf/dt - FORWARD VOLTAGE TEMPERATURE COEFFICIENT - mv/ o C -2. -2.2-2. -2. -.9 -.8. - PULSE INPUT CURRENT - ma Figure 2. Temperature Coefficient for Forward Voltage vs. Input Current V CC V V V CC 2 GND 7Ω *D V F SHIELD 9 Ω. µf BYPASS 2 GND 2 * DIODE D (N9 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. Figure. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure ). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 2-% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS22, RS22, T-, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges. % DATA INPUTS. V CLOCK % DATA. V OUTPUTS t PSK t PSK CLOCK Figure. Illustration of Propagation Delay Skew t PSK t PSK Figure. Parallel Data Transmission Example For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2-29 Avago Technologies. All rights reserved. AV2-9EN - January 7, 29