Low Noise, High Speed Amplifier for -Bit Systems AD FEATURES Low Noise. nv/ Hz Input Voltage Noise. pa/ Hz Input Current Noise Custom Compensation Constant Bandwidth from G = to G = High Speed MHz (G = ) MHz (G = ) Low Power mw or.7 ma Typ for V Supply Output Disable Feature,. ma Low Distortion db Second Harmonic, f C = MHz db Third Harmonic, f C = MHz DC Precision mv Max Input Offset Voltage. V/ C Input Offset Voltage Drift Wide Supply Range, V to V Low Price Small Packaging Available in SOIC- and MSOP- APPLICATIONS ADC Preamp and Driver Instrumentation Preamp Active Filters Portable Instrumentation Line Receivers Precision Instruments Ultrasound Signal Processing High Gain Circuits CONNECTION DIAGRAM LOGIC REFERENCE IN +IN SOIC- (R-) MSOP- (RM-) AD The AD allows the user to choose the gain bandwidth product that best suits the application. With a single capacitor, the user can compensate the AD for the desired gain with little trade-off in bandwidth. The AD is a very well behaved amplifier that settles to.% in ns for a V step. It has a fast overload recovery of ns. The AD is stable over temperature with low input offset voltage drift and input bias current drift,. µv/ C and na/ C, respectively. The AD is also capable of driving a 7 Ω line with ± V video signals. The AD is not only technically superior, but also priced considerably less than comparable amps drawing much higher quiescent current. The AD is a high speed, general-purpose amplifier, ideal for a wide variety of gain configurations, and can be used throughout a signal processing chain and in control loops. The AD is available in both standard -lead SOIC and MSOP packages in the industrial temperature range of C to + C. 7 DISABLE V OUT OMP PRODUCT DESCRIPTION The AD is a very high performance, high speed voltage feedback amplifier that can be used in -bit resolution systems. It is designed to have low voltage and current noise (. nv/ Hz typ and. pa/ Hz typ) while operating at the lowest quiescent supply current (7 ma @ ± V) among today s high speed, low noise op amps. The AD operates over a wide range of supply voltages from ±. V to ± V, as well as from single V supplies, making it ideal for high speed, low power instruments. An output disable pin allows further reduction of the quiescent supply current to. ma. CLOSED-LOOP V OUT = mv p-p G =, R F = k, R G =, R IN =, = pf G =, R F = k, R G =, R IN =., =.pf G =, R F =, R G =, R IN =., = pf G =, R F =, R G =, R IN =., = 7pF.M M M M G Figure. Small Signal Frequency Response Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box, Norwood, MA -, U.S.A. Tel: 7/-7 www.analog.com Fax: 7/-7 Analog Devices, Inc. All rights reserved.
AD SPECIFICATIONS V S = V (@ T A = C, V S = V, R L = k, Gain = +, unless otherwise noted.) ADAR/ADARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth G = +, = pf, V O =. V p-p MHz G = +, = 7 pf, V O =. V p-p MHz G = +, = pf, V O =. V p-p MHz G = +, = pf, V O =. V p-p MHz Slew Rate, V Step G = +, = pf V/µs G = +, = 7 pf V/µs G = +, = pf V/µs G = +, = pf V/µs Settling Time to.% V O = V Step, R L = Ω ns Overload Recovery (%) ±. V Input Step, G = + ns DISTORTION/NOISE PERFORMANCE f = MHz HD V O = V p-p dbc HD V O = V p-p dbc f = MHz HD V O = V p-p 7 dbc HD V O = V p-p dbc Input Voltage Noise f = khz.. nv/ Hz Input Current Noise f = khz. pa/ Hz Differential Gain Error NTSC, R L = Ω. % Differential Phase Error NTSC, R L = Ω. Degrees DC PERFORMANCE Input Offset Voltage.. mv Input Offset Voltage Drift T MIN to T MAX. µv/ C Input Bias Current +Input or Input 7.. µa Input Bias Current Drift na/ C Input Offset Current.. ±µa Open-Loop Gain db INPUT CHARACTERISTICS Input Resistance MΩ Common-Mode Input Capacitance pf Input Common-Mode Voltage Range. to +. V Common-Mode Rejection Ratio V CM = ± V db OUTPUT CHARACTERISTICS Output Voltage Swing. to +.. to +. V Linear Output Current ma Short-Circuit Current 7 ma Capacitive Load Drive for % Overshoot V O = mv p-p/ V p-p / pf DISABLE CHARACTERISTICS Off Isolation f = MHz db Turn-On Time V O = V to V, % Logic to % Output ns Turn-Off Time V O = V to V, % Logic to % Output ns DISABLE Voltage Off/On V DISABLE V LOGIC REFERENCE.7/. V Enabled Leakage Current Logic Ref =. V 7 µa DISABLE =. V µa Disabled Leakage Current Logic Ref =. V µa DISABLE =. V µa POWER SUPPLY Operating Range ±. ± ±. V Quiescent Current Output Enabled 7. 7.7 ma Output Disabled.. ma +Power Supply Rejection Ratio V CC = + V to + V, V EE = V db Power Supply Rejection Ratio V CC = + V, V EE = V to V db Specifications subject to change without notice.
V S = V(@ T A = C, R L = k, Gain = +, unless otherwise noted.) AD ADAR/ADARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth G = +, = pf, V O =. V p-p MHz G = +, = 7 pf, V O =. V p-p 7 MHz G = +, = pf, V O =. V p-p 7 MHz G = +, = pf, V O =. V p-p MHz Slew Rate, V Step G = +, = pf V/µs G = +, = 7 pf 7 V/µs G = +, = pf V/µs G = +, = pf V/µs Settling Time to.% V O = V Step, R L = Ω ns Overload Recovery (%) ± V Input Step, G = + ns DISTORTION/NOISE PERFORMANCE f = MHz HD V O = V p-p dbc HD V O = V p-p dbc f = MHz HD V O = V p-p 7 dbc HD V O = V p-p dbc Input Voltage Noise f = khz.. nv/ Hz Input Current Noise f = khz. pa/ Hz Differential Gain Error NTSC, R L = Ω. % Differential Phase Error NTSC, R L = Ω. Degrees DC PERFORMANCE Input Offset Voltage.. mv Input Offset Voltage Drift T MIN to T MAX. µv/ C Input Bias Current +Input or Input. µa Input Bias Current Drift na/ C Input Offset Current.. ±µa Open-Loop Gain db INPUT CHARACTERISTICS Input Resistance MΩ Common-Mode Input Capacitance pf Input Common-Mode Voltage Range. to +. V Common-Mode Rejection Ratio V CM = ± V db OUTPUT CHARACTERISTICS Output Voltage Swing. to +.. to +. V Linear Output Current 7 ma Short-Circuit Current ma Capacitive Load Drive for % Overshoot V O = mv p-p/ V p-p / pf DISABLE CHARACTERISTICS Off Isolation f = MHz db Turn-On Time V O = V to V, % Logic to % Output ns Turn-Off Time V O = V to V, % Logic to % Output ns DISABLE Voltage Off/On V DISABLE V LOGIC REFERENCE./. V Enabled Leakage Current Logic Ref =. V 7 µa DISABLE =. V µa Disabled Leakage Current Logic Ref =. V µa DISABLE=. V µa POWER SUPPLY Operating Range ±. ± ±. V Quiescent Current Output Enabled 7.. ma Output Disabled.7. ma +Power Supply Rejection Ratio V CC = + V to + V, V EE = V db Power Supply Rejection Ratio V CC = + V, V EE = V to V db Specifications subject to change without notice.
AD V S = V (@ T A = C, R L = k, Gain = +, unless otherwise noted.) ADAR/ADARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth G = +, = pf, V O =. V p-p 7 MHz G = +, = 7 pf, V O =. V p-p MHz G = +, = pf, V O =. V p-p MHz G = +, = pf, V O =. V p-p MHz Slew Rate, V Step G = +, = pf V/µs G = +, = 7 pf V/µs G = +, = pf V/µs G = +, = pf V/µs Settling Time to.% V O = V Step, R L = Ω ns Overload Recovery (%) V to. V Input Step, G = + ns DISTORTION/NOISE PERFORMANCE f = MHz HD V O = V p-p dbc HD V O = V p-p dbc f = MHz HD V O = V p-p dbc HD V O = V p-p dbc Input Voltage Noise f = khz.. nv/ Hz Input Current Noise f = khz. pa/ Hz DC PERFORMANCE Input Offset Voltage.. mv Input Offset Voltage Drift T MIN to T MAX. µv/ C Input Bias Current +Input or Input 7.. µa Input Bias Current Drift na/ C Input Offset Current.. ±µa Open-Loop Gain 7 7 db INPUT CHARACTERISTICS Input Resistance MΩ Common-Mode Input Capacitance pf Input Common-Mode Voltage Range. to. V Common-Mode Rejection Ratio. V to. V db OUTPUT CHARACTERISTICS Output Voltage Swing. to.. to. V Linear Output Current ma Short-Circuit Current ma Capacitive Load Drive for % Overshoot V O = mv p-p/ V p-p / pf DISABLE CHARACTERISTICS Off Isolation f = MHz db Turn-On Time V O = V to V, % Logic to % Output ns Turn-Off Time V O = V to V, % Logic to % Output ns DISABLE Voltage Off/On V DISABLE V LOGIC REFERENCE./.7 V Enabled Leakage Current Logic Ref =. V 7 µa DISABLE =. V µa Disabled Leakage Current Logic Ref =. V µa DISABLE =. V µa POWER SUPPLY Operating Range ±. ± ±. V Quiescent Current Output Enabled.7 7. ma Output Disabled.. ma +Power Supply Rejection Ratio V CC =. V to. V, V EE = V 7 db Power Supply Rejection Ratio V CC = + V, V EE =. V to +. V 7 db Specifications subject to change without notice. REV.
AD ABSOLUTE MAXIMUM RATINGS Supply Voltage................................. V Power Dissipation........ Observed Power Derating Curves Input Voltage (Common-Mode)............... ± V S ± V Differential Input Voltage...................... ±. V Differential Input Current..................... ± ma Output Short-Circuit Duration...................... Observed Power Derating Curves Storage Temperature.................. C to + C Operating Temperature Range........... C to + C Lead Temperature Range (Soldering, sec)........ C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The AD inputs are protected by diodes. Current-limiting resistors are not used in order to preserve the low noise. If a differential input exceeds ±. V, the input current should be limited to ± ma. MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 7 C for an extended period can result in device failure. While the AD is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature ( C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. PIN CONFIGURATION LOGIC REFERENCE IN +IN AD 7 DISABLE V OUT OMP MAXIMUM POWER DISSIPATION (mw).... -LEAD MSOP -LEAD SOIC. 7 AMBIENT TEMPERATURE ( C) Figure. Maximum Power Dissipation vs. Temperature* *Specification is for device in free air: -Lead SOIC: JA = C/W -Lead MSOP: JA = C/W PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function LOGIC REFERENCE Reference for Pin * Voltage Level. Connect to logic low supply. IN Inverting Input +IN Noninverting Input Negative Supply Voltage OMP Compensation Capacitor. Tie to. (See the Applications section for value.) V OUT Output 7 Positive Supply Voltage DISABLE Disable, Active Low* *When Pin (DISABLE) is about V or more higher than Pin (LOGIC REFERENCE), the part is enabled. When Pin is brought down to within about. V of Pin, the part is disabled. (See the Specification tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin can be tied to or a logic high source, and Pin can be tied to ground or logic low. Alternatively, if Pin and Pin are not connected, the part will be in an enabled state. ORDERING GUIDE Model Temperature Range Package Description Package Outline Branding ADAR C to + C -Lead SOIC R- ADAR-REEL C to + C -Lead SOIC R- ADAR-REEL7 C to + C -Lead SOIC R- ADARM C to + C -Lead MSOP RM- HNA ADARM-REEL C to + C -Lead MSOP RM- HNA ADARM-REEL7 C to + C -Lead MSOP RM- HNA ADARZ* C to + C -Lead SOIC R- ADARZ-REEL* C to + C -Lead SOIC R- ADARZ-REEL7* C to + C -Lead SOIC R- *Z = Lead Free CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD Typical Performance Characteristics (T A = C, V S = V, R L = k, G = +, R F = R G =, R S =., R O = 7, R D =., = 7 pf, C L =, C F =, V OUT = V p-p, Freq = MHz, unless otherwise noted.) CLOSED-LOOP G =, R F = k, R G =, = pf G =, R F = k, R G =, = pf G =, R F = R G =, = 7pF G =, R F = 7, = pf 7 G = V S =.V V S =.V V V.M M M M G TPC. Small Signal Frequency Response vs. Frequency and Gain, V OUT = mv p-p, Noninverting. See Test Circuit. M M M TPC. Small Signal Frequency Response vs. Frequency and Supply, V OUT = mv p-p, Noninverting. See Test Circuit. G G = V S =.V G =, R F = k, R G =, R IN =, = pf G =, R F = k, R G =, R IN =., =.pf G =, R F =, R G =, R IN =., = pf V S = V V G =, R F =, R G =, R IN =., = 7pF V S =.V.M M M M G TPC. Small Signal Frequency Response vs. Frequency and Gain, V OUT = mv p-p, Inverting. See Test Circuit. 7 M M M TPC. Small Signal Frequency Response vs. Frequency and Supply, V OUT = mv p-p, Inverting. See Test Circuit. G G = = pf G = 7 7pF 7 V OUT =.V AND mv p-p pf V OUT = V p-p V p-p 7pF pf.m M M M G TPC. Small Signal Frequency Response vs. Frequency and Compensation Capacitor, V OUT = mv p-p. See Test Circuit. M M M TPC. Frequency Response vs. Frequency and V OUT, Noninverting. See Test Circuit. G
AD G = G = R F = R G R F = R F = k 7 R L = k 7 R F = R F = 7 R F =.M M M M G TPC 7. Large Signal Frequency Response vs. Frequency and Load, Noninverting. See Test Circuit. R F = k AND C F =.pf.m M M M TPC. Small Signal Frequency Response vs. Frequency and R F, Noninverting, V OUT = mv p-p. See Test Circuit. G 7 G = + C + C G = + C V OUT = V p-p C V OUT = mv p-p R S =. + C C R S = R S = M M M TPC. Frequency Response vs. Frequency, Temperature and V OUT, Noninverting. See Test Circuit. G.M M M M G TPC. Small Signal Frequency Response vs. Frequency and R S, Noninverting, V OUT = mv p-p. See Test Circuit. G = pf pf pf pf pf OPEN-LOOP 7 PHASE Degrees M M M TPC. Small Signal Frequency Response vs. Frequency and Capacitive Load, Noninverting, V OUT = mv p-p. See Test Circuit and Figure. G k k M M M TPC. Open-Loop Gain and Phase vs. Frequency, R G = Ω, R F = kω, R O = 7 Ω, R D =. Ω, = pf. See Test Circuit. G 7
AD. G =... V V S =.V V P OUT dbm 7 f =.MHz f f 7. P OUT.. M M M TPC.. db Flatness vs. Frequency and Supply, V OUT = V p-p, R L = Ω, Noninverting. See Test Circuit...7... FREQUENCY MHz TPC. Intermodulation Distortion vs. Frequency DISTORTION dbc 7.M R L = R L = k THIRD SECOND M M TPC. Second and Third Harmonic Distortion vs. Frequency and R L M THIRD-ORDER INTERCEPT dbm V S =.V V S = V FREQUENCY MHz TPC 7. Third-Order Intercept vs. Frequency and Supply Voltage DISTORTION dbc 7 k THIRD V S =.V SECOND SECOND V S = V SECOND V S = V THIRD M M M DISTORTION dbc 7 SECOND R L = THIRD SECOND R L = k THIRD V OUT V p-p TPC. Second and Third Harmonic Distortion vs. Frequency and V S TPC. Second and Third Harmonic Distortion vs. V OUT and R L
AD.. DISTORTION dbc 7 SECOND f C = MHz THIRD SECOND f C = MHz THIRD POSITIVE OUTPUT VOLTAGE V...... POSITIVE OUTPUT NEGATIVE OUTPUT......7 NEGATIVE OUTPUT VOLTAGE V V OUT V p-p TPC. Second and Third Harmonic Distortion vs. V OUT and Fundamental Frequency (f C ), G = +.. LOAD TPC. DC Output Voltage vs. Load. See Test Circuit. DISTORTION dbc 7 SECOND THIRD SECOND THIRD f C = MHz f C = MHz SHORT-CIRCUIT CURRENT ma V S = V S =. V S =. V OUT V p-p 7 TEMPERATURE C TPC. Second and Third Harmonic Distortion vs. V OUT and Fundamental Frequency (f C ), G = + TPC. Short-Circuit Current to Ground vs. Temperature 7 f C = MHz R L = k G = R L = k, DISTORTION dbc SECOND THIRD V OUT mv FEEDBACK RESISTANCE TPC. Second and Third Harmonic Distortion vs. Feedback Resistor (R F ) TIME ns TPC. Small Signal Transient Response vs. R L, V O = mv p-p. See Test Circuit, Noninverting.
AD. V O = V p-p G =. V O = V p-p G = R L = k.. V OUT V R L = V OUT V V S =.V.. V S = V.. TIME ns TPC. Large Signal Transient Response vs. R L. See Test Circuit, Noninverting. TIME ns TPC. Large Signal Transient Response vs. V S. See Test Circuit. V O = V p-p G = V IN = V G = + V IN = V/DIV V OUT = V/DIV V OUT, R L = k V IN R L = VOLTS V OUT V IN TIME ns TPC. Large Signal Transient Response. See Test Circuit, Inverting. TIME ns TPC. Overdrive Recovery vs. R L. See Test Circuit.. C L = pf G = V O = V p-p G =. C L = pf, pf V OUT V. OUTPUT SETTLING +.%.% ns. TIME ns TPC 7. Large Signal Transient Response vs. C L. See Test Circuit. VERT =.mv/div HOR = ns/div TPC..% Settling Time, V Step
AD SETTLING V PULSEWIDTH = ns PULSEWIDTH = s V V t TIME s TPC. Long-Term Settling, V to V, V S = ± V, G = + INPUT CURRENT NOISE pa/ Hz k k k M M TPC. Input Current Noise vs. Frequency G =.. V OUT mv TIME ns TPC. Small Signal Transient Response, V O = mv p-p. G = +. See Test Circuit. VOLTAGE OFFSET mv..... 7 TEMPERATURE C TPC. V OS vs. Temperature.. VOLTAGE NOISE nv/ Hz.nV/ Hz INPUT BIAS CURRENT A 7. 7... k k k M M TPC. Input Voltage Noise vs. Frequency. 7 TEMPERATURE C TPC. Input Bias Current vs. Temperature
AD CMRR db 7 DISABLED ISOLATION db 7 k k M M M TPC 7. CMRR vs. Frequency. See Test Circuit..M M M M TPC. Input to Output Isolation, Chip Disabled. See Test Circuit 7. G k k k OUTPUT IMPEDANCE.. OUTPUT IMPEDANCE k k k... k k M M M G k k M M M G TPC. Output Impedance vs. Frequency, Chip Enabled. See Test Circuit. TPC. Output Impedance vs. Frequency, Chip Disabled. See Test Circuit. V DISABLE V PSRR V t EN = ns V OUTPUT PSRR db V S =.V +PSRR V S = V V t DIS = ns 7 V S = V TIME ns TPC. Enable (t EN )/Disable (t DIS ) Time vs. V OUT. See Test Circuit. k k M M M M TPC. PSRR vs. Frequency and Supply Voltage. See Test Circuits and.
AD.. SUPPLY CURRENT ma 7. 7.... 7 TEMPERATURE C TPC. Quiescent Supply Current vs. Temperature Test Circuits HP7D NETWORK ANALYZER CABLE R IN. R S R O R D CABLE AD 7pF. R G R F. C F Test Circuit. Noninverting Gain Test Circuit. CMRR CABLE R S FET PROBE AD HP7D NETWORK ANALYZER R IN. C L R L 7pF R G R F R G R F C F Test Circuit. Noninverting Gain with FET Probe Test Circuit. Output Impedance, Chip Enabled AD CABLE. R O R D CABLE.V V... LOGIC REF DISABLE 7. RIN. R G R F 7pF Test Circuit. Inverting Gain Test Circuit. Enable/Disable
AD HP7D NETWORK ANALYZER CABLE BIAS BNC HP7D NETWORK ANALYZER CABLE.. LOGIC REF DISABLE AD FET PROBE k., W 7. 7pF 7pF Test Circuit 7. Input to Output Isolation, Chip Disabled Test Circuit. Positive PSRR BIAS BNC HP7D NETWORK ANALYZER CABLE AD HP7D +V S NETWORK ANALYZER. W 7pF 7. 7pF Test Circuit. Output Impedance, Chip Disabled Test Circuit. Negative PSRR
AD APPLICATIONS The typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor, C INTERNAL, using dominant pole compensation. To a first-order approximation, voltage feedback op amps have a fixed gain bandwidth product. For example, if its db bandwidth for G = + is MHz, at a gain of G = + its bandwidth will be only about MHz. The AD is a voltage feedback op amp with a minimal C INTERNAL of about. pf. By adding an external compensation capacitor,, the user can circumvent the fixed gain bandwidth limitation of other voltage feedback op amps. Unlike the typical op amp with fixed compensation, the AD allows the user to. Maximize the amplifier bandwidth for closed-loop gains between and, avoiding the usual loss of bandwidth and slew rate.. Optimize the trade-off between bandwidth and phase margin for a particular application.. Match bandwidth in gain blocks with different noise gains, such as when designing differential amplifiers (as shown in Figure ). OPEN-LOOP 7 = pf = pf (A) k k k M M M G G (B) (B) (A) (C) (C) Figure. Simplified Diagram of Open-Loop Gain and Phase Response Figure is the AD gain and phase plot that has been simplified for instructional purposes. If the desired closed-loop gain is G = + and = pf is chosen, Arrow A of the figure shows that the bandwidth is about MHz and the phase margin is about. If the gain is changed to G = + and is fixed at pf, then (as expected for a typical op amp) the PHASE Degrees bandwidth is degraded to about MHz and the phase margin increases to (Arrow B). However, by reducing to zero, the bandwidth and phase margin return to about MHz and (Arrow C), respectively. In addition, the slew rate is dramatically increased, as it roughly varies with the inverse of. COMPENSATION CAPACITANCE pf 7 7 NOISE GAIN V/V Figure. Suggested Compensation Capacitance vs. Gain for Maintaining db Peaking Table I and Figure provide recommended values of compensation capacitance at various gains and the corresponding slew rate, bandwidth, and noise. Note that the value of the compensation capacitor depends on the circuit noise gain, not the voltage gain. As shown in Figure, the noise gain, G N, of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or noninverting gain. Thus, R S + Noninverting GN = RF / RG + Inverting G = R / R + AD OMP G = G N = NONINVERTING N F G R F R G R G AD + R F OMP G = G N = INVERTING Figure. The Noise Gain of Both Is Table I. Recommended Component Values. See Test Circuit. C F = C L =, R L = k, R IN =. Noise Gain Slew db Output Noise Output Noise (Noninverting R S R F R G OMP Rate SS BW (AD Only) (AD with Resistors) Gain) ( ) ( ) ( ) (pf) (V/ s) (MHz) (nv/ Hz) (nv/ Hz) 7 7 NA... 7... k.7.. k. 7.. k...7. k..
AD With the AD, a variety of trade-offs can be made to fine-tune its dynamic performance. Sometimes more bandwidth or slew rate is needed at a particular gain. Reducing the compensation capacitance, as illustrated in TPC, will increase the bandwidth and peaking due to a decrease in phase margin. On the other hand, if more stability is needed, increasing the compensation cap will decrease the bandwidth while increasing the phase margin. As with all high speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. Often, the input capacitance (due to the op amp itself, as well as the PC board) could have a significant effect. The feedback resistance, together with the input capacitance, may contribute to a loss of phase margin, thereby affecting the high frequency response, as shown in TPC. Furthermore, a capacitor (C F ) in parallel with the feedback resistor can compensate for this phase loss. Additionally, any resistance in series with the source will create a pole with the input capacitance (as well as dampen high frequency resonance due to package and board inductance and capacitance), the effect of which is shown in TPC. It must also be noted that increasing resistor values will increase the overall noise of the amplifier, and that reducing the feedback resistor value will increase the load on the output stage, thus increasing distortion (TPC ). Using the Disable Feature When Pin (DISABLE) is approximately V or more higher than Pin (LOGIC REFERENCE), the part is enabled. When Pin is brought down to within about. V of Pin, the part is disabled. See the Specification tables for exact disable and enable voltage levels. If the disable feature is not going to be used, Pin can be tied to V S or a logic high source, and Pin can be tied to ground or logic low. Alternatively, if Pin and Pin are not connected, the part will be in an enabled state. THEORY OF OPERATION The AD is fabricated on the second generation of Analog Devices proprietary High Voltage extra-fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar f T s in the GHz region. The transistors are dielectrically isolated from the substrate (and each other), eliminating the parasitic and latch-up problems caused by junction isolation. It also reduces nonlinear capacitance (a source of distortion) and allows a higher transistor f T for a given quiescent current. The supply current is trimmed, which results in less part-to-part variation of bandwidth, slew rate, distortion, and settling time. As shown in Figure, the AD input stage consists of an NPN differential pair in which each transistor operates at. ma collector current. This allows the input devices a high transconductance; thus, the AD has a low input noise of. nv/ Hz @ khz. The input stage drives a folded cascode that consists of a pair of PNP transistors. The folded cascode and current mirror provide a differential to single-ended conversion of signal current. This current then drives the high impedance node (Pin ), where the external capacitor is connected. The output stage preserves this high impedance with a current gain of,, so that the AD can maintain a high open-loop gain even when driving heavy loads. Two internal diode clamps across the inputs (Pins and ) protect the input transistors from large voltages that could otherwise cause emitter-base breakdown, which would result in degradation of offset voltage and input bias current. +IN IN C INTERNAL.pF OMP Figure. Simplified Schematic OUTPUT PCB LAYOUT CONSIDERATIONS As with all high speed op amps, achieving optimum performance from the AD requires careful attention to PC board layout. Particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply. Otherwise, lead inductance can influence the frequency response and even cause high frequency oscillations. Use of a multilayer printed circuit board, with an internal ground plane, will reduce ground noise and enable a compact component arrangement. Due to the relatively high impedance of Pin and low values of the compensation capacitor, a guard ring is recommended. The guard ring is simply a PC trace that encircles Pin and is connected to the output, Pin, which is at the same potential as Pin. This serves two functions. It shields Pin from any local circuit noise generated by surrounding circuitry. It also minimizes stray capacitance, which would tend to otherwise reduce the bandwidth. An example of a guard ring layout may be seen in Figure 7. Also shown in Figure 7, the compensation capacitor is located immediately adjacent to the edge of the AD package, spanning Pin and Pin. This capacitor must be a high quality surfacemount COG or NPO ceramic. The use of leaded capacitors is not recommended. The high frequency bypass capacitor(s) should be located immediately adjacent to the supplies, Pins and 7. To achieve the shortest possible lead length at the inverting input, the feedback resistor R F is located beneath the board and just spans the distance from the output, Pin, to inverting input Pin. The return node of resistor R G should be situated as closely as possible to the return node of the negative supply bypass capacitor connected to Pin.
AD LOGIC REFERENCE IN +IN (TOP VIEW) 7 DISABLE OMP V OUT GROUND PLANE BYPASS CAPACITOR Table II. Summary of ADC Driver Performance, f C = khz, V OUT = V p-p Parameter Measurement Unit Second Harmonic Distortion. db Third Harmonic Distortion. db THD. db SFDR. db METAL BYPASS CAPACITOR GROUND PLANE COMPENSATION CAPACITOR Figure 7. Recommended Location of Critical Components and Guard Ring DRIVING -BIT ADCS Low noise and adjustable compensation make the AD especially suitable as a buffer/driver for high resolution analogto-digital converters. As seen in TPC, the harmonic distortion is better than db at frequencies between khz and MHz. This is a real advantage for complex waveforms that contain high frequency information, as the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process. The increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a sample. This advantage is particularly apparent when using -bit high resolution ADCs with high sampling rates. Figure shows a typical ADC driver configuration. The AD is in an inverting gain of 7., f C is khz, and its output voltage is V p-p. The results are listed in Table II. R G khz + +V AD V pf R F.k pf IN LO V AD7 7kSPS Figure. Inverting ADC Driver, Gain = 7., f C = khz IN HI BITS + R G. +V AD V R F 7 OPTIONAL C F IN HI IN LO V AD7 7kSPS ADC Figure. Noninverting ADC Driver, Gain =, f C = khz Table III. Summary of ADC Driver Performance, f C = khz, V OUT = V p-p Parameter Measurement Unit Second Harmonic Distortion. db Third Harmonic Distortion. db THD. db SFDR. db Figure shows another ADC driver connection. The circuit was tested with a noninverting gain of. and an output voltage of approximately V p-p for optimum resolution and noise performance. No filtering was used. An FFT was performed using Analog Devices evaluation software for the AD7 -bit converter. The results are listed in Table III. DIFFERENTIAL DRIVER The AD is uniquely suited as a low noise differential driver for many ADCs, balanced lines, and other applications requiring differential drive. If pairs of internally compensated op amps are configured as inverter and follower, the noise gain of the inverter will be higher than that of the follower section, resulting in an imbalance in the frequency response (see Figure ). A better solution takes advantage of the external compensation feature of the AD. By reducing the OMP value of the inverter, its bandwidth may be increased to match that of the follower, avoiding compromises in gain bandwidth and phase delay. The inverting and noninverting bandwidths can be closely matched using the compensation feature, thus minimizing distortion. BITS 7
AD Figure illustrates an inverter-follower driver circuit operating at a gain of, using individually compensated ADs. The values of feedback and load resistors were selected to provide a total load of less than kω, and the equivalent resistances seen at each op amp s inputs were matched to minimize offset voltage and drift. Figure is a plot of the resulting ac responses of driver halves. V IN. + G = + AD 7pF k G = + AD k pf Figure. Differential Amplifier V OUT V OUT USING THE AD IN ACTIVE FILTERS The low noise and high gain bandwidth of the AD make it an excellent choice in active filter circuits. Most active filter literature provides resistor and capacitor values for various filters but neglects the effect of the op amp s finite bandwidth on filter performance; ideal filter response with infinite loop gain is implied. Unfortunately, real filters do not behave in this manner. Instead, they exhibit finite limits of attenuation, depending on the gain bandwidth of the active device. Good low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low frequency, pass-band performance. Figure shows the schematic of a -pole, low-pass active filter, and Table IV lists typical component values for filters having a Bessel-type response with gains of and. Figure is a network analyzer plot of this filter s performance. V IN R R C C AD V OUT R G R F G = G = + Figure. Schematic of a Second-Order Low-Pass Active Filter Table IV. Typical Component Values for Second-Order Low-Pass Filter of Figure Gain R ( ) R ( ) R F ( ) R S ( ) 7. nf nf 7 pf.. nf nf pf k M M M G Figure. AC Response of Two Identically Compensated High Speed Op Amps Configured for Gains of + and G = G = G = k k k M M Figure. Frequency Response of the Filter Circuit of Figure for Two Different Gains k M M M G Figure. AC Response of Two Dissimilarly Compensated AD Op Amps (Figure ) Configured for Gains of + and. Note the Close Gain Match.
AD Driving Capacitive Loads When the AD drives a capacitive load, the high frequency response may show excessive peaking before it rolls off. Two techniques can be used to improve stability at high frequency and reduce peaking. The first technique is to increase the compensation capacitor,, which reduces the peaking while maintaining gain flatness at low frequencies. The second technique is to add a resistor, R SNUB, in series between the output pin of the AD and the capacitive load, C L. Figure shows the response of the AD when both and R SNUB are used to reduce peaking. For a given C L, Figure can be used to determine the value of R SNUB that maintains db of peaking in the frequency response. Note, however, that using R SNUB attenuates the low frequency output by a factor of R LOAD /(R SNUB + R LOAD )... FET PROBE R SNUB pf R L k = 7pF; R SNUB = = pf; R SNUB = R SNUB CAPACITIVE LOAD pf Figure. Relationship of R SNUB vs. C L for db Peaking at a Gain of + = pf; R SNUB = 7... FREQUENCY MHz Figure. Peaking vs. R SNUB and for C L = pf
AD OUTLINE DIMENSIONS -Lead Standard Small Outline Package [SOIC] (R-) Dimensions shown in millimeters and (inches). (.7). (.7). (.). (.) COPLANARITY.. (.). (.) SEATING PLANE.7 (.) BSC. (.). (.).7 (.). (.). (.). (.). (.).7 (.7). (.). (.).7 (.). (.7) C /(D) COMPLIANT TO JEDEC STANDARDS MS-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters. BSC. BSC. BSC PIN. BSC.... COPLANARITY.. MAX SEATING PLANE.. COMPLIANT TO JEDEC STANDARDS MO-7AA... Revision History Location Page / Data Sheet changed from REV. C to. Edits to SPECIFICATIONS heading........................................................................ Changes to ORDERING GUIDE........................................................................... 7/ Data Sheet changed from REV. B to REV. C. Deleted all references to evaluation board...............................................................universal Replaced Figure....................................................................................... Updated OUTLINE DIMENSIONS....................................................................... / Data Sheet changed from REV. A to REV. B. Edits to Evaluation Board Applications...................................................................... Edits to Figure 7...................................................................................... / Data Sheet changed from REV. to REV. A. Edits to SPECIFICATIONS...............................................................................