DesignCon East 2005 Feasibility of 40 to 50 Gbps NRZ Interconnect Design for Terabit Backplanes Roger Weiss, Paricon Technologies Corporation President, RWeiss@paricon-tech.com Scott McMorrow, Teraspeed Consulting Group LLC Director of Engineering Scott@teraspeed.com
Abstract The design of an electrically transparent interconnect technology is investigated for backplane and interconnect design of 40 to 50 Gbps NRZ baseband systems as would be used in terabit backplane systems. We will show that it is feasible to design a copper based interconnect environment, utilizing thin anisotropic elastomeric materials, advanced connector transition design and low loss PCB materials, that is capable of delivering a significant increase in performance over current generation products. Details of 3D full wave design methodologies used, evaluation of material properties and mechanical design techniques, and final design deterministic jitter will be discussed. Author(s) Biography Roger Weiss, President, Paricon Technologies Corporation Scott McMorrow, President, Teraspeed Consulting Group LLC- Mr. McMorrow is an experienced technologist with over 20 years of broad background in complex system design, interconnect & Signal Integrity engineering, modeling & measurement methodology, engineering team building and professional training. Mr. McMorrow has a consistent history of delivering and managing technical consultation that enables clients to manufacture systems with state-of-the-art performance, enhanced design margins, lower cost, and reduced risk. Mr. McMorrow is an expert in high-performance design and Signal Integrity engineering, and has been a consultant and trainer to engineering organizations world-wide.
Introduction The interconnection path has many elements from device to package to board to cable etc. An interconnection discontinuity is found at each juncture. Each element of the path needs to be designed so as to provide low loss, low reflection, and low crosstalk capability a challenging task for transmission speeds that are above 10 GHz. The solution to this performance challenge must also introduce little increase in cost over today s technology if it is to be adopted by the electronic industry. One key source of signal loss is created by the interconnection discontinuities in the system. Paricon Technologies has applied its PariPoser contact system at each traditional level of interconnection used in electronic systems. The goal of this work is to demonstrate the feasibility of a low cost interconnection capability, which can provide electrical interconnection at a bandwidth well above 35 GHz. An overview of the interconnection capability will be provided, with a status report on the performance of the reference designs being developed. Board-to-board and backplane connector systems designed with PariPoser anisotropic elastomeric interposer materials are shown to have extraordinary performance characteristics, which can be utilized in ultra high-speed differential interconnect design. During the course of this presentation we will demonstrate the design of an advanced test vehicle capable of operation at 40 to 50 Gbps NRZ baseband in a terabit/s system. The design includes: advanced RF measurement launch design, advanced connector transition design and compensations for flex and PCB contact pad geometries, and lowloss flex and PCB stripline laminate designs will be shown to correlate in measurements out to 35 GHz, when compared to the details of 3D solver optimization studies. At data rates beyond 10 Gbps, modeling and optimization of connector pad transitions, material loss profiles, and jitter budgets can be exacting. We will show the necessary tradeoffs required to design at these speeds, and develop an electrically transparent interconnect that can easily accomplish, chip-to-chip, board-to-board, and module to module communication at 40 to 50 Gbps. Ultimately, we will show that current systems are nowhere near the performance limits of copper interconnect. Additionally, at 40+ Gbps speeds, noise and jitter are significant challenges. We will show that systems need not be limited by excessive deterministic jitter and attenuation. PariPoser Overview High performance, low loss interconnection presents a challenging goal for every component of the interconnection from separable connectors to cables and boards. Key among the challenges is to maintain constant characteristic impedance throughout the total path. Surface mount connector systems can provide the best opportunity to eliminate the impedance mismatch introduced at the separable interconnect, and the PariPoser
interconnection fabric which was discussed in detail at the 2003 IMAPS conference provides the opportunity to have a virtually invisible separable interconnection. Figure 1 presents a cross sectional view of the PariPoser Fabric. The fabric consists of an array of fine conductive elements that are imbedded in a polymer matrix. The conductive elements consist of chains of spherical, silver plated, nickel particles that can provide very low resistance interconnection. These chains are uniformly distributed throughout the polymer sheet providing a z-axis interconnection capability. The density of the conductors is much higher than the elements being connected. As a result, the PariPoser does not require orientation and can be treated as an anisotropically conductive fabric. Cross Section of Paricon s BallWire PariPoser Fabric Figure 1 Figure 2 provides a z-axis view of an array of circular contacts on 1 mm centers (pads on the printed circuit board), as viewed through the PariPoser interconnect. This view shows the tops of the columns relative to the contacts. As can be seen, the column density is very high as compared to the contact density. Figure 2 Figure 3 The manner in which the materials function is demonstrated in figure 3. Here two components that are to be interconnected are aligned to each other, with a layer of PariPoser fabric placed between them. As the two components are compressed to each other, the PariPoser sheet deforms, and the BallWire conductors bend to provide an interconnection that has an average resistance of about 10 milliohms. An insulation resistance of greater than 109 ohms is achieved when the gap between adjacent
conductors is greater than 40% of the pitch. This provides an anisotropic resistance ratio of ~1012. A complete overview of the PariPoser can be found on Paricon s website www.paricon-tech.com.. High Bandwidth Interconnection PariPoser surface contact technology can be used in the design of extremely high bandwidth PCB-to-PCB and PCB-to-flex interconnections. These interconnects can be used as the basis for high performance mezzanine (straight thru) and backplane (right angle) connector systems, along with arbitrary flex interconnect systems which are formidable in their versatility and bandwidth. At high differential data rates and bandwidth, the classical limitations of material conductor and dielectric losses come heavily into play. Because of relatively short z-axis dimensions of the PariPoser fabric, material loss causes an almost-negligible degradation in signaling performance well beyond 100 GHz. The full passive transmission channel, will dictate the overall performance of a PariPoser connection system. But, silicon differential driver and receiver digital signal processing (DSP) technology is currently advancing at astonishing rates, thereby transforming the passive interconnect channel into an active one. Equalization, among other advanced signal processing techniques, is capable of flattening the interconnect response curve, nearly eliminating the adverse effect of loss across the entire broadband frequency spectrum required for differential signaling. However, in order to flatten the frequency response curve, active electronics require a well defined interconnect transfer characteristic that is free from unwanted resonance and crosstalk, which can be detrimental to received signal quality. Therefore, large amounts of interconnect loss can be tolerated if an interconnect channel can be designed to be well-behaved. For the purposes of our discussion, a wellbehaved interconnect will have no major quarter or half-wave resonances, and return loss of -15 db, or better, across the transmission bandwidth. Connectors have historically been the least well-behaved element in the interconnect path. Recent advances in commercial connector technology have shown increased component performance that allows for the design of 3.125, 6.25, 10 and 12.5 Gbps NRZ transmission channels on a backplane, with the potential of 20 Gbps in the future. In these cases, however, several serious limitations arise that must be dealt with before reliable scaling to 20 Gbps and 40 Gbps data rates can be achieved. First, many of the current generation of backplane connectors have no path for system scaling. Should a designer wish to enhance overall system performance by increasing data rates, eventually connector (and mounted connector) resonance effects form a brick wall through which no signal will pass. Many current commercial connector systems fail the brick wall test at data rates between 6 and 10 Gbps. A select few fail in the 10 to 20 Gbps range. And no commercial connector, which these authors know of, is capable of scaling to OC-768 rates of 40 + Gbps and beyond.
Second, many of the current generation of backplane connector systems are based upon some form of wafer technology, where the connector is comprised of vertical wafers, that are stacked together lengthwise, to form the connector assembly. This lengthwise arrangement of the wafers requires that differential pairs be segregated to vertical stripes, or channels, within the connector, and on the PCB. Unfortunately, this configuration, although optimal for manufacturing and PCB routing considerations, is not optimal for high-speed signaling. This configuration causes differential pair skew and differential to common mode conversion, resulting in increased attenuation, noise, crosstalk and EMI, further exacerbating the performance brick wall. Third, most connector systems are not well matched to the printed circuit boards that they are interconnecting. The electrical invisibility required for a 40 + Gbps interconnect channel dictates that the transition boundary between the connector contacts and the PCB be well matched. This matching extends out to any pads, traces or vias required on the board. Should the PCB characteristics change, the connector must necessarily change. But, because of the high R&D and capitol expense required for manufacturing current generation connector systems, manufacturers create one design fits all types of highspeed connectors. The PCB must be designed to work with the connector and not the other way around. As a result, most connector system designs are a compromise, and poor fit at best for any particular application. A connector based upon the PariPoser system, however, can be designed into custom, semi-custom, and commodity applications, as an electrically invisible interconnect system that is capable of scaling to 40 + Gbps. PariPoser fabric conforms to the underlying contact geometry of the supporting laminate structures with the following benefits: 1) A thin high-performance interposing fabric with bandwidth greater than 50 GHz; 2) A contact region that conforms to the geometry of the application; 3) A contact region that matches the performance capability of the underlying design. PariPoser fabric allows a connector to scale to meet the bandwidth capability of the underlying electrical support structure of pads, vias and traces. Bandwidth is no longer a limitation. One connector that fits all applications can truly be designed, since various different contact and transition structures can be accommodated by the physical boundary of the contact area. As a result, different performance points and density requirements can be accommodated, limited only by the physical boundary of the contact region. How to Achieve Data Transmission at 40 + Gbps NRZ At 40 + Gbps NRZ, with a bit interval of 25 ps or less, the requirements for the data transmission channel are exacting, when compared to more conventional current day
channels. First, in order to achieve a low jitter solution, the transmission channel must have minimal group delay variation throughout the bandwidth required for the data pattern being transmitted. Second, the transmission channel must have low return loss (< -12 db) out to, and beyond, the Nyquist frequency of 20+ GHz, to reduce signal distortion and ISI, due to reflections. Third, for the received signal to be recovered, insertion loss should be better than 26 to -32 db, which implies a maximum signal attenuation of 20:1 and 40:1. Group Delay Group delay control is a major key component to any 40 + Gbps NRZ transmission channel. One unit interval (UI) at 40 Gbps is 25 ps. This does not leave much room for jitter in the channel for whatever reason. If we use modern compliance specifications as a general rule to follow, then channel jitter should be apportioned as follows: 0.3 UI for transmitter deterministic jitter 0.3 UI for channel deterministic jitter 0.4 UI eye opening at the receiver (less random jitter components) Based on this rule of thumb, both the transmitter and our interconnect channel will be allowed a maximum of 7.5 ps jitter each. Certainly, this is within the reach of current transmitter technology, with SiGe and possibly CMOS devices. But is it within the reach of our hypothetical interconnect channel? A group delay measurement for 50 ohm microstrip trace is shown in Figure 5, which shows classical microstrip dispersion with increasing frequency, due to a mixed dielectric environment. As frequency rises, an increased percentage of the microstrip electromagnetic field propagates in the PCB dielectric, rather than the surrounding air. For the purposes of most conventional 50 ohm interconnect, significant dispersion is not apparent below 10 GHz. Signaling below 20 Gbps NRZ is not appreciably effected. However, above 10 GHz, dispersion rises, with a delta delay of approximately 1.5 ps/in @ 20 GHz, and 2 ps/in at 25 GHz. Clearly, when the total allocated deterministic jitter for our hypothetical channel is 7.5 ps @ 40 Gbps, 1.5 ps/in of delay variation with respect to frequency is significant, and eliminates low loss microstrip traces from consideration in a 20 + inch backplane design. In fact, any trace, package, or connector design that utilizes mixed dielectrics, with large differences in dielectric constant, will face significant group delay dispersion, disqualifying them from consideration for 40 + Gbps NRZ data transmission systems. This may include: grounded co-planar wave; co-planar waveguide; connector systems with mixed air/plastic dielectrics; mixed dielectric stripline using materials with large Er differences, and some package constructions. On the other hand, stripline, heavily embedded microstrip, and coaxial transmission line construction techniques may be considered.
Figure 5 Measured microstrip group delay variation (~8 inches of microstrip) Return Loss Adequate impedance control of all elements of a 40 + Gbps NRZ transmission channel is mandatory. Although current multi-tap equalizer technology can be successfully utilized to compensate for ISI due to reflections, it is generally a good idea to reduce the impedance mismatch of all elements. However, control of return loss is exceedingly difficult using conventional connector design methods, at frequencies beyond 10 GHz. Most serial interconnect compliance specifications require a return loss of < -10 db to -12 db at, and below, the Nyquist frequency of the channel. However, these correspond to impedance mismatches of between 20% and 30%, and, in these author s opinions, represent a significantly higher percentage of the signal amplitude than we would like to allow. As a general rule, we would like to limit return loss mismatch to between 10% and 15% of the signal amplitude, or -20 db to -15 db, to reduce the need for the use of complex receive or transmit equalizers, which may be problematic to implement at 40 + Gbps data rates. Ideally, we would like to achieve these rates with de-emphasis techniques, which are relatively easy to implement. Insertion Loss For the received signal to be recovered, insertion loss should be better than 26 db to -32 db, which implies a maximum signal attenuation of 20:1 and 40:1. If an 800 mv differential transmitter is used, differential received signal levels of between 40 mv and 20 mv are implied. Sensitivity of the receiver is critical to any potential loss calculations, but is beyond the scope of this paper. As an example, we will assume that the receiver minimum required differential amplitude is 40 mv, to achieve a low BER. In this case, our budget will allow -26 db insertion loss at 20 GHz. If we further assume that 20% of the insertion loss can be apportioned to crosstalk effects, we then require a
50 mv final amplitude, in the absence of crosstalk, or a channel insertion loss of -24 db, as summarized below: Channel signal amplitude w/o crosstalk = 50 mv (-24 db @ 20 GHz) Channel Crosstalk = 10 mv (-38 db @ 20 GHz) Channel received signal amplitude = 40 mv (-26 db @ 20 GHz) To achieve 40 Gbps NRZ data transmission, we require a backplane transmission channel, including traces and connectors, with no more than -24 db insertion loss. As a line in the sand, we will allocate -2 db @ 20 GHz of attenuation per backplane connector, with the remaining 20 db of attenuation for backplane traces. With this in mind, is 40 Gbps data transmission on a backplane feasible? Calculations of stripline trace, in various materials, show the following losses per inch for differential stripline with 7.5 mil trace width and a 9 mil gap: Loss Tangent Loss/inch Material 0.025-2.4 db FR-4 0.014-1.5 db Pyralux FR Flex 0.01-1.11 db Low loss FR-4 0.005-0.7 db Rogers 4350/4003 0.003-0.53 db Pyralux AP Flex 0.002-0.45 db LCP Flex 0.001-0.37 db PTFE We can now calculate the maximum feasible total trace length which can be achieved at 40 Gbps, using our -20 db loss assumption: Material FR-4 Pyralux FR Low loss FR-4 Rogers 4350 Pyralux AP LCP Flex PTFE Maximum Trace Length 8 inches 13 inches 18 inches 28 inches 37 inches 44 inches 54 inches FR-4-class materials are not capable of sustaining 40 Gbps data transmission over any but small lengths of trace. Clearly, however, other lower loss materials have the theoretical capability of sustaining extremely high bit rates over some remarkable lengths. If we can design a connector system which can meet our differential insertion loss requirement of -2 db @ 20 GHz, then we believe our goal of a 40 Gbps backplane is achievable. Toward this end, Paricon Technologies and Teraspeed Consulting Group undertook the design of a validation vehicle, to test the concept of a right angle backplane
connector, utilizing PariPoser material, flex, and optimized pad transitions. A drawing of the Gigacon TM connector system, under current development, is shown in Figure 6. Figure 6 Gigacon orthogonal backplane connector system Electromagnetic Validation of the Test Vehicle To demonstrate the capabilities of the PariPoser system in both mezzanine and right angle backplane connector applications, a test vehicle was co-designed by Paricon Technologies and Teraspeed Consulting Group LLC. Figure 7 shows the test vehicle configuration of two printed circuit boards and one flex cable, utilizing PariPoser Interconnect to join the contact structures.
Figure 7 Flex Interconnect Test Vehicle Full-wave time domain electromagnetic modeling and simulation with CST Microwave Studio was used in the design and validation of the PariPoser Test Vehicle contact transition regions. Figure 8 shows an example of a modeled section of PariPoser material sandwiched between two 0.062 thick FR-4 printed circuit boards, with appropriate highbandwidth thru-board microstrip-to-microstrip transitions. Full-wave simulation of this section was taken to 40 GHz, in order to guarantee faithful modeling up to the Nyquist frequency of 20 GHz, necessary for 40 Gbps NRZ digital data transmission. 5 and 10 mil thick PariPoser material was modeled and subsequently compared to ideal modeling of the interposer area with perfect contacts placed between the two boards at 10 mil and 5 mil heights. Insertion loss and return loss results are shown in Figures 9 and 10. PariPoser 10-mil material compares with favorable slight additional loss when compared to the ideal 10-mil transition. This loss can be attributed to additional dielectric loading caused by the floating metal BallWire conductors in the non-contact region of the interface, where the high frequency dipoles of the floating metal cause an increase in effective dielectric constant at the interface boundary. This slight increase in effective constant has the effect of loading the transition and adding a slight amount of loss, which reduces its resonance characteristics and effectively forms a better-behaved interface. Finally, a 5-mil ideal interface was simulated to show the improvement in both insertion loss and return loss performance that can be achieved thru thin PariPoser layers. Real
PariPoser performance should track this decrease in spacing, providing an interface transition with better than 1.5 db insertion loss, and 15 db return loss at the 20 GHz Nyquist frequency required for well-behaved 40 Gbps data transmission. Figure 8 PariPoser Transition Modeling Figure 9 Modeled Insertion Loss
Figure 10 Modeled Return Loss Modeling and simulation of single-ended transitions for FR-4 and flex substrates clearly show that satisfactory results can be obtained out to at least 20 GHz, and possibly to 25 GHz, as would be required for 50 Gbps NRZ data. Measured insertion loss and return loss data for the connector validation vehicle are shown in Figures 11 and 12, respectively. Our insertion loss data is nothing short of remarkable. A connector designed with 1 of Pyralux FR flex, with a loss tangent of ~0.014, has an insertion loss of better than 2dB @ 25 GHz, with return loss below -15 db for most of the bandwidth. The -3 db bandwidth for this connector is approximately 33 GHz. More startling is the lack of any major resonance, until the upper cutoff of the structure is achieved.
Figure 11 Measured connector insertion loss (2 contact transitions, and 1, 2, or 5 Pyralux FR flex.) Figure 12 Measured connector return loss
Design and Simulation of the Gigacon TM Connector System Measurements have validated the potential of a 40 + Gbps NRZ connector system design. Further work has been done, and is currently under progress, to validate a differential connector interfaced to low loss backplane materials. For the purposes of our study, a contact system utilizing PariPoser material, Pyralux AP flex, and Rogers RO4003, with stripline construction was designed. Full wave simulations and optimizations, using CST Microwave Studio, were performed on various differential transition structures. One such structure is shown in Figure 13. Extracted differential s-parameters for this contact structure are shown in Figure 14. Figure 13 Candidate differential transition structure
Figure 14 Candidate differential transition structure To form a complete connector, two contact structures, Figure 13, and one piece of Pyralux AP are required. At 20 GHz, our loss budget is therefore: Contact -0.38 db 1 Pyralux AP -0.53 db Contact -0.38 db Total Loss -1.29 db @ 20 GHz Our loss per connector clearly falls within our design target of 2 db/connector @ 20 GHz, with design margin left on the table. Rogers RO4003 laminate system was chosen, as an experimental test vehicle, for its low loss characteristics and ease of fabrication. Ansoft 2D was used in the extraction of frequency dependent W-element table models, for simulation in Synopsys HSPICE. All extracted s-parameters were converted into HSPICE Laplace E-element black box subcircuits, with Sigrity Broadband Spice. Finally, this potential backplane design with two Gigacon TM connectors, and 20 of backplane trace, were integrated into SiSoft SIAuditor. Simulation with a simple-to-implement de-emphasis driver, and various bit patterns, were performed, an example of which is shown in Figure 15. For this particular test case, modeling and simulation indicate that it is possible to transmit 40 Gbps NRZ data on a high performance backplane with 6 ps of received deterministic jitter and a remarkable 98 mv eye opening.
Figure 15 40 Gbps NRZ data on 20 RO4003 with two Gigacon backplane connectors, and transmitter de-emphasis. Summary The answer to the question, Is it feasible to design a connector and backplane systems capable of 40+ Gbps NRZ differential data? is clearly yes. We have shown that it is feasible to design a copper based interconnect environment, utilizing thin anisotropic elastomeric materials, advanced connector transition design and low loss PCB materials, that is capable of delivering a significant increase in performance over current generation products. Further development and tests are currently on-going.