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1 Rev. 2.2_ CMOS SERIAL E 2 PROM Features Low power consumption Standby :. µa Max. (V CC =5.5 V) Operating :.8 ma Max. (V CC =5.5 V) :.4 ma Max. (V CC =2.5 V) Wide operating voltage range Read/Write :.8 to 5.5 V Sequential read capable Pin Assignment 8-pin P (PKG drawing code : DP8-A,DP8-C,DP8-E) 8-pin SOP (PKG drawing code : FJ8-D,FJ8-E) 8-pin MSOP (PKG drawing code : FN8-A) 8-pin TSSOP (PKG drawing code : FT8-B) Pin Assignment pin P Top view S-93C46ADP-A S-93C56ADP-A S-93C66ADP-A * See Dimensions Pin Functions Name VCC NC TEST GND NC The is high speed, low power K/2K/4K-bit E 2 PROM with a wide operating voltage range. It is organized as 64-word 6-bit, 28- word 6-bit, 256-word 6-bit, respectivly. Each is capable of sequential read, at which time addresses are automatically incremented in 6-bit blocks. The instruction code is compatible with the NM9346/56/66. VCC 8-pin SOP Top view S-93C46AFJ S-93C56AFJ S-93C66AFJ Pin Number TEST GND Table P SOP SOP2 TSSOP MSOP 8-pin SOP2 Top view VCC 2 NC S-93C46ADFJ S-93C56ADFJ S-93C66ADFJ 3 8 Chip select input Serial clock input Serial data input Serial data output GND Ground TEST GND Function VCC NC TEST GND TEST Test pin (normally kept open) (can be connected to GND or Vcc) NC No Connection V CC Power supply Endurance : 6 cycles/word Data retention : years S-93C46A : K bits NM9346 instruction code compatible S-93C56A : 2K bits NM9356 instruction code compatible S-93C66A : 4K bits NM9366 instruction code compatible Figure pin TSSOP Top view S-93C46AFT S-93C56AFT S-93C66AFT 8-pin MSOP Top view S-93C46AMFN S-93C56AMFN S-93C66AMFN VCC NC TEST GND

2 CMOS SERIAL E 2 PROM Rev. 2.2_ Block Diagram Memory array Address decoder V CC GND Data register Mode decode logic Output buffer Clock generator Figure 2 Instruction Set Table 2 Instruction Start Bit Op Code Address Data S-93C46A S-93C56A S-93C66A READ (Read data) A 5 to A XA 6 to A A 7 to A D 5 to D Output* WRITE (Write data) A 5 to A XA 6 to A A 7 to A D 5 to D Input ERASE (Erase data) A 5 to A XA 6 to A A 7 to A WRAL (Write all)*2 xxxx xxxxxx xxxxxx D 5 to D Input ERAL (Erase all)*2 xxxx xxxxxx xxxxxx EWEN (Program enable) xxxx xxxxxx xxxxxx EWDS (Program disable) xxxx xxxxxx xxxxxx x : Doesn t matter. * : Addresses are continuously incremented. *2 : Valid only at Vcc = 2.5 V to 5.5 V. Absolute Maximum Ratings Table 3 Parameter Symbol Ratings Unit Power supply voltage V CC -.3 to +7. V Input voltage V IN -.3 to V CC +.3 V Output voltage V OUT -.3 to V CC V Storage temperature under bias T bias -5 to +95 C Storage temperature T stg -65 to +5 C 2

3 Rev. 2.2_ CMOS SERIAL E 2 PROM Recommended Operating Conditions Table 4 Parameter Symbol Conditions Min. Typ. Max. Unit Power supply voltage V CC EWEN/EWDS READ/WRITE/ERASE WRAL/ERAL High level input voltage V IH V CC =2.7 to 4.5 V V CC=4.5 to 5.5 V V CC =.8 to 2.7 V Low level input voltage V IL V CC =2.7 to 4.5 V V CC=4.5 to 5.5 V V CC =.8 to 2.7 V Vcc.8 Vcc Vcc Vcc Vcc.8.2 Vcc.5 Vcc Operating temperature T opr C Pin Capacitance Endurance Table 5 (Ta=25 C, f=. MHz, V CC =5 V) Parameter Symbol Conditions Min. Typ. Max. Unit Input Capacitance C IN V IN = V 8 pf Output Capacitance C OUT V OUT = V pf Table 6 Parameter Symbol Min. Typ. Max. Unit Endurance N W 6 cycles/word V V V V V V V V 3

4 CMOS SERIAL E 2 PROM Rev. 2.2_ DC Electrical Characteristics Table 7 Parameter Smbl Conditions V CC =4.5 V to 5.5 V V CC =2.5 V to 4.5 V V CC =.8 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Current consumption I CC unloaded ma (READ) Current consumption (PROGRAM) I CC2 unloaded ma V Parameter Smbl Conditions CC =4.5 V to 5.5 V V CC =2.5 to 4.5 V V CC =.8 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Standby current consumption Input leakage current Output leakage current I SB =GND =Open..6.4 µa Connected to V CC or GND I LI V IN =GND to V CC µa I LO V OUT =GND to V CC µa Low level output V OL I OL =2. ma.4 V voltage I OL = µa... V I High level output V OH =-4 µa 2.4 V OH voltage I OH =- µa V CC -.7 V CC -.7 V I OH =- µa V CC -.7 V CC -.7 V CC -.2 V Write enable latch data hold voltage V DH Only when write disable mode Table V 4

5 Rev. 2.2_ CMOS SERIAL E 2 PROM AC Electrical Characteristics Table 9 Input pulse voltage Output reference voltage Output load. V CC to.9 V CC.5 V CC pf Table Parameter Smbl V CC =4.5 to 5.5V V CC =2.5 to 4.5 V V CC =.8 to 2.5V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. setup time t S.2.4. µs hold time t H µs deselect time t CDS µs Data setup time t DS..2.4 µs Data hold time t DH..2.4 µs Output delay t PD µs Clock frequency f MHz Clock pulse width t H, t L µs Output disable time t HZ, t HZ µs Output enable time t SV.5.5. µs Programming time ms (READ) (VERIFY) t S t CDS t DS t DH Valid data t H t PD t L t DS Valid data t H t SV t HZ2 t HZ t DH t PD Figure 3 Read Timing 5

6 CMOS SERIAL E 2 PROM Rev. 2.2_ Operation Instructions (in the order of start-bit, instruction, address, and data) are latched to in synchronization with the rising edge of after goes high. A start-bit can only be recognized when the high of is latched to the rising edge of when goes from low to high, it is impossible for it to be recognized as long as is low, even if there are pulses after goes high. Any pulses input while is low are called "dummy clocks." Dummy clocks can be used to adjust the number of clock cycles needed by the serial IC to match those sent out by the CPU. Instruction input finishes when goes low, where it must be low between commands during t CDS. All input, including and signals, is ignored while is low, which is stand-by mode.. Read The READ instruction reads data from a specified address. After A is latched at the rising edge of, output changes from a high-impedance state () to low level output. Data is continuously output in synchronization with the rise of. When all of the data (D) in the specified address has been read, the data in the next address can be read with the input of another clock. Thus, it is possible for all of the data addresses to be read through the continuous input of clocks as long as is high. The last address (An A A = ) rolls over to the top address (An A A = ) A5 A4 A3 A2 A A D5 D4 D3 D2 D D D5 D4 D3 D2 D D D5 D4 Figure 4 Read Timing(S-93C46A) A 5A 4A 3A 2A A + A 5A 4A 3A 2A A D3 X A6 A5 A4 A3 A2 A A D5 D4 D3 D2 D D D5 D4 D3 D D D5 D4 D3 A 6A 5A 4A 3A 2A A + A 6A 5A 4A 3A 2A A +2 Figure 5 Read Timing (S-93C56A) 6

7 Rev. 2.2_ CMOS SERIAL E 2 PROM A7 A6 A5 A4 A3 A2 A A D5 D4 D3 D2 D D D5 D4 D3 D2 D D D5 D4 D3 A 7A 6A 5A 4A 3A 2A A + A 7A 6A 5A 4A 3A 2A A Write (WRITE, ERASE, WRAL, ERAL) Figure 6 Read Timing (S-93C66A) There are four write instructions, WRITE, ERASE, WRAL, and ERAL. Each automatically begins writing to the nonvolatile memory when goes low at the completion of the specified clock input. The write operation is completed in ms ( Max.), and the typical write period is less than 5 ms. In the S- 93C46A/56A/66A, it is easy to VERIFY the completion of the write operation in order to minimize the write cycle by setting to high and checking the pin, which is low during the write operation and high after its completion. This VERIFY procedure can be executed over and over again. Because all and inputs are ignored during the write operation, any input of instruction will also be disregarded. When outputs high after completion of the write operation or if it is in the high-impedence state (), the input of instructions is available. Even if the pin remains high, it will enter the high-impedence state upon the recognition of a high of (start-bit) attached to the rising edge of an pulse. (see Figure 3). input should be low during the VERIFY procedure. 7

8 CMOS SERIAL E 2 PROM Rev. 2.2_ 2. WRITE This instruction writes 6-bit data to a specified address. After changing to high, input a start-bit, op-code (WRITE), address, and 6-bit data. If there is a data overflow of more than 6 bits, only the last 6 bits of the data is considered valid. Changing to low will start the WRITE operation. It is not necessary to make the data "" before initiating the WRITE operation. t CDS VERIFY A5 A4 A3 A2 A A D5 D t SV Figure 7 WRITE Timing(S-93C46A) VERIFY X A6 A5 A4 A3 A2 A A D5 D Figure 8 WRITE Timing(S-93C56A) Figure 9 WRITE Timing(S-93C66A) busy t CDS ready t HZ t SV busy ready t CDS VERIFY A7 A6 A5 A4 A3 A2 A A D5 D t SV busy ready t HZ t HZ 8

9 Rev. 2.2_ CMOS SERIAL E 2 PROM 2.2 ERASE This command erases 6-bit data in a specified address. After changing to high, input a start-bit, op-code (ERASE), and address. It is not necessary to input data. Changing to low will start the ERASE operation, which changes every bit of the 6-bit data to "." t CDS VERIFY A5 A4 A3 A2 A A t SV busy ready t HZ Figure ERASE Timing(S-93C46A) X A6 A5 A4 A3 A2 A A Figure ERASE Timing(S-93C56A) A7 A6 A5 A4 A3 A2 A A Figure 2 ERASE Timing(S-93C66A) t CDS t SV t CDS t SV VERIFY busy ready VERIFY busy ready t HZ t HZ 9

10 CMOS SERIAL E 2 PROM Rev. 2.2_ 2.3 WRAL This instruction writes the same 6-bit data into every address. After changing to high, input a start-bit, op-code (WRAL), address (optional), and 6-bit data. If there is a data overflow of more than 6 bits, only the last 6 bits of the data is considered valid. Changing to low will start the WRAL operation. It is not necessary to make the data "" before initiating the WRAL operation. t CDS VERIFY D5 D 4Xs Figure 3 WRAL Timing(S-93C46A) t SV busy ready VERIFY D5 D 6Xs Figure 4 WRAL Timing(S-93C56A) t CDS t HZ t SV busy ready VERIFY D5 D 6Xs Figure 5 WRAL Timing(S-93C66A) t CDS t SV busy ready t HZ t HZ

11 Rev. 2.2_ CMOS SERIAL E 2 PROM 2.4 ERAL This instruction erases the data in every address. After changing to high, input a start-bit, op-code (ERAL), and address (optional). It is not necessary to input data. Changing to low will start the ERAL operation, which changes every bit of data to "." t CDS VERIFY Xs Figure 6 ERAL Timing(S-93C46A) Xs Figure 7 ERAL Timing(S-93C56A) Xs 9 Figure 8 ERAL Timing(S-93C66A) 8 t CDS t CDS t SV busy 9 ready VERIFY t SV busy VERIFY t SV busy t HZ ready ready t HZ t HZ

12 CMOS SERIAL E 2 PROM Rev. 2.2_ 3. Write enable (EWEN) and Write disable (EWDS) The EWEN instruction puts the into write enable mode, which accepts WRITE, ERASE, WRAL, and ERAL instructions. The EWDS instruction puts the into write disable mode, which refuses WRITE, ERASE, WRAL, and ERAL instructions. The powers on in write disable mode, which protects data against unexpected, erroneous write operations caused by noise and/or CPU malfunctions. It should be kept in write disable mode except when performing write operations, after power-on and before shut-down. STANDBY Xs =EWEN =EWDS Figure 9 EWEN/EWDS Timing(S-93C46A) =EWEN 6Xs =EWDS Figure 2 EWEN/EWDS Timing(S-93C56A) =EWEN 6Xs =EWDS Figure 2 EWEN/EWDS Timing(S-93C66A) STANDBY STANDBY 2

13 Rev. 2.2_ CMOS SERIAL E 2 PROM Receiving a Start-Bit Both the recognition of a start-bit and the VERIFY procedure occur when is high. Therefore, only after a write operation, in order to accept the next command by having go high, the pin switch from a state of high-impedence to a state of data output; but if it recognizes a start-bit, the pin returns to a state of high-impedence. Three-wire Interface (- direct connection) Although the normal configuration of a serial interface is a 4-wire interface to,,, and, a 3-wire interface is also a possibility by connecting and. However, since there is a possibility that the output from the serial memory IC will interfere with the data output from the CPU with a 3-wire interface, install a resistor between and in order to give preference to data output from the CPU to (See Figure 22). CPU SIO R : k kω Figure 22 Please refer Application Note S-29 & S-93C series EEPROMs Tips, Tricks & Traps for equivalent circuit of each pin. 3

14 CMOS SERIAL E 2 PROM Rev. 2.2_ Ordering Information S-93Cx6A yy - zz - w Note P code (Distincion for package process) None S A Taping specification None (for P) TB Package code DP : P FJ : SOP DFJ : SOP2 FT : TSSOP MFN : MSOP Product name S-93C46A : k bits S-93C56A : 2k bits S-93C66A : 4k bits Product name Package code Taping specification P code Package/Tape/Reel drawings None DP8-A DP None S DP8-A DP8-E -A DP8-C S-93C46A None FJ8-D S-93C66A DFJ S FJ8-D FJ8-E None FT8-A S FT8-A FT8-B MFN -TB None FN8-A ) Package dimensions of SOPs whose package codes are FJ and DFJ are the same in the range of deviation. 2) Please contact an SII local office or a local representative for details. 4

15 Rev. 2.2_ CMOS SERIAL E 2 PROM Chracteristics. DC Characteristics. Current consumption (READ) I CC I CC.4.2 V CC =5.5 V f =2 MHz DATA=.2 Current consumption (READ) I CC I CC.4.2 V CC =3.3 V f =5 KHz DATA= Current consumption (READ) I CC I CC.4.2 V CC =.8 V f = KHz DATA= Current consumption (READ) I CC Power supply voltage V CC I CC.4.2 Ta=25 C f = KHz, KHz DATA= KHz V CC (V).7 Current consumption (WRITE) I CC2 V CC =5.5 V KHz Current consumption (READ) I CC Power supply voltage V CC I CC.4.2 Ta=25 C f = MHz, 5 KHz DATA= V CC (V).6 Current consumption (READ) I CC Clock frequency f I CC.4.2 K MHz V CC =5. V Ta=25 C K f (Hz) M 2M.8 Current consumption (WRITE) I CC2 V CC =3.3 V 5KHz I CC2..5 I CC

16 CMOS SERIAL E 2 PROM Rev. 2.2_.9 Current consumption (WRITE) I CC2. Current consumption (WRITE) I CC2 Power supply voltage V CC V CC =.8 V Ta=25 C I CC2..5 I CC Standby current consumption I SB I SB (A).3 Input leakage current I LI I LI (µa).5 Output leakage current I LO I LO (µa) V CC =5.5 V V CC =5.5 V,,, TEST=5.5 V V CC =5.5 V =5.5 V.2 Input leakage current I LI I LI (µa).4 Output leakage current I LO I LO (µa) V CC (V) V CC =5.5 V,,, TEST= V V CC =5.5 V = V High level output voltage V OH V OH (V) V CC =4.5 V I OH =-4µA

17 Rev. 2.2_ CMOS SERIAL E 2 PROM.7 High level output voltage V OH 2.7 V CC =2.7 V I OH =-µa.8 High level output voltage V OH 2.5 V CC =2.5 V I OH =-µa V OH (V) 2.6 V OH (V) High level output voltage V OH V OH (V).2 Low level output voltage V OL V OL (V) V CC =.8 V I OH =-µa V CC =.8 V I OL =µa High level output current I OH V CC =2.7 V V OH =2. V Low level output voltage V OL V OL (V).3.2. V CC =4.5 V I OL =2. ma High level output current I OH I OH V CC =4.5 V V OH =2.4 V High level output current I OH V CC =2.5 V V OH =.8 V -4-4 I OH I OH

18 CMOS SERIAL E 2 PROM Rev. 2.2_.25 High level output current I OH V CC =.8 V V OH =.6 V.26 Low level output current I OL V CC =4.5 V V OL =.4 V I OH I OL Low level output current I OL I OL..5 V CC =.8 V V OL =. V Input voltage V IN (V IL,V IH ) V INV (V) V CC =5. V,, Input voltage V IN (V IL,V IH ) Power supply voltage V CC V INV (V) 3..5 Ta=25 C,, V CC (V) 7 8

19 Rev. 2.2_ CMOS SERIAL E 2 PROM 2. AC Characteristics 2. Maximum operating frequency f max Power supply voltage V CC Ta=25 C 2.2 Program time Power supply voltage V CC Ta=25 C f max 2M M (Hz) K K (ms) V CC (V) 2.3 Program time (ms) 2.5 Program time (ms) V CC =5. V V CC =.8 V Data output delay time t PD t PD (µs).6.4 V CC =2.7 V V CC (V) 2.4 Program time (ms) V CC =3. V Data output delay time t PD t PD (µs).3.2. V CC =4.5 V Data output delay time t PD t PD (µs).5. V CC =.8 V

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28 The information described herein is subject to change without notice. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Although exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.