CMP 200 FUNCTIONAL DRAWINGS. DC Bus and Power Distribution

Transcription

1 CPI Canada Inc Functional Drawing Index CMP 00 FUNCTIONAL DRAWINGS DESCRIPTION DC Bus and Power Distribution System ON Room Interface XRay Exposure Radiographic kv Control and Feedback Filament Drive and ma Control Low Speed Starter Automatic Exposure Control (AEC) Serial Communications DAP Aux VAC / VDC Power Dist (optional) DRAWING NUMBER MD08 MD08 MD08 MD08 MD08 MD08 MD08 MD088 MD089 MD080 MD08 THE PART NUMBER OF THE ORIGINAL AEC BOARD IN THE GENERATOR FOR WHICH THIS MANUAL WAS PREPARED IS LISTED BELOW: AEC BOARD PART NUMBER (AS ORIGINALLY SHIPPED) See Drawing List for the AEC Board Part Number for this particular unit. MF08C

2 REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: AC MAINS INPUT F F F E INVERTER BOARD E V V SWITCHING REGULATOR CIRCUIT (U AND ASSOCIATED COMPONENTS) TP V J J J J J J F V TP V F V J J THIS TRANSFORMER AND ASSOCIATED WIRING IS ONLY FITTED ON UNITS CONFIGURED FOR 0 VAC BOOST, OR WITH THE VAC / VDC POWER DIST OPTION 80V N.C. 00V N.C. 0V 0V 08V 0V 0V 0V 0V 0V 9V V 8V 0V 8V SEE MD08 THIS SHEET DEPICTS PH. UNITS. REFER TO PAGE FOR PH. 00/80 V UNITS, AND PAGE FOR PH. 08 V UNITS J J J0 J0 J J J9 J9 F8 F9 J9 E * E F0 E V V J J J J J F F F E ** E E F F E V VAC TO MD08 K D8 H.V. AUXILIARY BOARD D0 F D MAIN CONTACTOR DRIVE FROM MD08 E0 E F * E8 0/0 VAC TO LOW SPEED ER MD08 SOFT CONTACTOR DRIVE FROM MD08 K BUCKY DRIVE TO MD08 D VDC TO MD08 D R DS R R D C C R C C D U R R V V J J J J J J J J J J J J J8 J J9 J J J9 J J8 J J J J V V V TP9 ON / OFF COMMAND FROM MD08 SOFT SENSE TO MD08 * E, E, E, E, E8, E0, E CONFIGURE THE BUCKY OUTPUTS FOR VDC, 0 VAC, OR 0 VAC. REFER TO CHAPTER 8 FOR DETAILS. ** E, E, E CONFIGURE THE LOW SPEED ER BOOST VOLTAGE FOR 0 OR 0 VAC. REFER TO CHAPTER FOR DETAILS. V V V TP D D D D9 V V V SWITCHING REGULATOR CIRCUIT (U0 AND ASSOCIATED COMPONENTS) V V SWITCHING REGULATOR CIRCUIT (U AND ASSOCIATED COMPONENTS) F V V SWITCHING REGULATOR CIRCUIT (U9 AND ASSOCIATED COMPONENTS) K TP TP V V ON / OFF COMMAND FROM MD08 TP0 V V V V V TP9 J J J J9 J J J8 J J J J88 J8 F V TP V FILAMENT SUPPLY BOARD FLUORESCENT LAMP LCD DISPLAY ASSEMBLY V F TP9 00 VAC BACKLIGHT POWER SUPPLY (Q, Q, T, ETC) G. SANWALD FEB 00 TP REFER TO MD088 (AEC) FOR PINOUTS OF THE / VDC AND VDC SUPPLIES AEC BOARD CONSOLE BOARD 8 FEB 00 FEB /0 C / 0VDC POWER SUPPLY & REGULATOR (U, L, DD, ETC) J J TP TP8 V 0V DC BUS & POWER DISTRIBUTION MD08 REV F SHEET OF

3 AC MAINS INPUT F F F F F ~ ~~ DS EMC CAPACITOR BOARD E * INVERTER BOARD E * 0 KW UNITS USE TWO INVERTER BOARDS V V SWITCHING REGULATOR CIRCUIT (U AND ASSOCIATED COMPONENTS) V TP V J J J J J J J J F V TP V ALTERNATE TRANSFORMER. (USED ON UNITS WITH THE AUX VAC / VDC POWER DISTRIBUTION OPTION) 80V 00V 0V 0V 0V 0V SEE MD08 J J J0 J0 J J E E ** E F F D MAIN CONTACTOR DRIVE FROM MD08 0/0 VAC TO LOW SPEED ER MD08 D R TP V J J J J V ON / OFF COMMAND FROM MD08 TP D V V SWITCHING REGULATOR CIRCUIT (U0 AND ASSOCIATED COMPONENTS) TP V V J V J V J V J F V J V FILAMENT SUPPLY BOARD 80V 00V F F K R R TP J9 J REFER TO MD088 (AEC) FOR PINOUTS OF THE / VDC AND VDC SUPPLIES N.C. N.C. 0V 0V 0V 00V 80V 0V 0V 0V 9V V 8V 0V 8V THIS SHEET DEPICTS PH. 00/80 V UNITS. REFER TO PAGE FOR PH. UNITS, AND PAGE FOR PH. 08 V UNITS F8 J9 J9 J9 J9 J J J J J V F F F F9 E E * E E VAC TO MD08 V E0 H.V. AUXILIARY BOARD E * F0 D0 D8 E8 V K SOFT CONTACTOR DRIVE FROM MD08 BUCKY DRIVE TO MD08 D VDC TO MD08 D R0 DS R C R C C D U V R8 R9 TP TP V TP TP J J J J J J J J J8 J J9 J J J9 J J8 J J J J V V TP9 SOFT SENSE TO MD08 * E, E, E, E, E8, E0, E CONFIGURE THE BUCKY OUTPUTS FOR VDC, 0 VAC, OR 0 VAC. REFER TO CHAPTER 8 FOR DETAILS. ** E, E, E CONFIGURE THE LOW SPEED ER BOOST VOLTAGE FOR 0 OR 0 VAC. REFER TO CHAPTER FOR DETAILS. V V D D D9 V V V SWITCHING REGULATOR CIRCUIT (U AND ASSOCIATED COMPONENTS) F V K V SWITCHING REGULATOR CIRCUIT (U9 AND ASSOCIATED COMPONENTS) ON / OFF COMMAND FROM MD08 TP0 V V TP9 J J8 J J88 J8 FLUORESCENT LAMP LCD DISPLAY ASSEMBLY V F TP 00 VAC BACKLIGHT POWER SUPPLY (Q, Q, T, ETC) TP9 TP G. SANWALD FEB 00 AEC BOARD CONSOLE BOARD 8 FEB 00 FEB /0 C / 0VDC POWER SUPPLY & REGULATOR (U, L, DD, ETC) J J TP TP8 V 0V DC BUS & POWER DISTRIBUTION MD08 REV F SHEET OF

4 AC MAINS INPUT F F F F F ~ ~~ DS EMC CAPACITOR BOARD E INVERTER BOARD E V V SWITCHING REGULATOR CIRCUIT (U AND ASSOCIATED COMPONENTS) V TP V J J J J J J J J F V TP V THIS TRANSFORMER AND ASSOCIATED WIRING IS ONLY FITTED ON UNITS CONFIGURED FOR 0 VAC BOOST, OR WITH THE VAC / VDC POWER DIST OPTION 80V N.C. 00V N.C. 0V 0V 08V 0V 0V 0V 0V 0V 9V V 8V 0V 8V SEE MD08 THIS SHEET DEPICTS PH. 08 V UNITS. REFER TO PAGE FOR PH. UNITS, AND PAGE FOR PH. 00/80 V UNITS J J J0 J0 J J J9 J9 F8 F9 J9 E * E F0 E V V J J J J J F F F E ** E E F F E V VAC TO MD08 K D8 H.V. AUXILIARY BOARD D0 D MAIN CONTACTOR DRIVE FROM MD08 E0 E F F * E8 0/0 VAC TO LOW SPEED ER MD08 SOFT CONTACTOR DRIVE FROM MD08 K BUCKY DRIVE TO MD08 D VDC TO MD08 D R DS R R D C C R C C D U R R V V V J J J J J J J J J J J J J8 J J9 J J J9 J J8 J J J J V V V TP9 ON / OFF COMMAND FROM MD08 SOFT SENSE TO MD08 * E, E, E, E, E8, E0, E CONFIGURE THE BUCKY OUTPUTS FOR VDC, 0 VAC, OR 0 VAC. REFER TO CHAPTER 8 FOR DETAILS. ** E, E, E CONFIGURE THE LOW SPEED ER BOOST VOLTAGE FOR 0 OR 0 VAC. REFER TO CHAPTER FOR DETAILS. V V TP D D D D9 V V V SWITCHING REGULATOR CIRCUIT (U0 AND ASSOCIATED COMPONENTS) V V SWITCHING REGULATOR CIRCUIT (U AND ASSOCIATED COMPONENTS) F V V SWITCHING REGULATOR CIRCUIT (U9 AND ASSOCIATED COMPONENTS) K TP TP V V ON / OFF COMMAND FROM MD08 TP0 V V V V V TP9 J J J J9 J J J8 J J J J88 J8 F V TP V FILAMENT SUPPLY BOARD FLUORESCENT LAMP LCD DISPLAY ASSEMBLY V F TP9 00 VAC BACKLIGHT POWER SUPPLY (Q, Q, T, ETC) G. SANWALD FEB 00 TP REFER TO MD088 (AEC) FOR PINOUTS OF THE / VDC AND VDC SUPPLIES AEC BOARD CONSOLE BOARD 8 FEB 00 FEB /0 C / 0VDC POWER SUPPLY & REGULATOR (U, L, DD, ETC) J J TP TP8 V 0V DC BUS & POWER DISTRIBUTION MD08 REV F SHEET OF

5 NOTE REFERENCE REMARKS LOW (APPROXIMATELY 0 VDC) DISABLES THE V, / V, AND V REGULATORS (GENERATOR SWITCHED OFF). HIGH (APPROXIMATELY VDC) ENABLES THESE REGULATORS (GENERATOR SWITCHED ON VIA THE CONSOLE ON/OFF SWITCHES, OR VIA THE ON/OFF SWITCHES ON THE ). VDC IS PRESENT AT THIS POINT WHEN THE GENERATOR IS SWITCHED ON, ENERGIZING K ON THE. THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE BELOW. 8 s FIGURE V 8 V G. SANWALD FEB 00 8 FEB 00 FEB /0 DC BUS & POWER DISTRIBUTION MD08 REV F SHEET OF

6 REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: V J J8 J Q ON / OFF COMMAND TO MD08 OFF ON J J TP J8 J J8 J TP9 S OFF Q Q R R Q ON / OFF COMMAND TO MD08 KEYBOARD ASSEMBLY CONSOLE BOARD S ON V U TP R J J BUFFER MAIN CONTACTOR DRIVE TO MD08 SOFT SENSE FROM MD08 U D J J TP V J J TP0 J J J J U0 U TP J J DRIVER CPLD SOFT CONTACTOR DRIVE TO MD08 J J DATA, ADDRESS, & CONTROL BUS H.V. AUXILIARY BOARD G. SANWALD FEB 00 8 FEB 00 FEB /0 SYSTEM ON MD08 REV A SHEET OF

7 NOTE REFERENCE THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE BELOW. REMARKS LOW (APPROXIMATELY 0 VDC) ENERGIZES THE MAIN POWER CONTACTOR IN THE GENERATOR, ( HIGH, VDC = NOT ENERGIZED). THIS CONTACTOR IS ENERGIZED AFTER THE MAIN BUS CAPACITORS ARE CHARGED, APPROXIMATELY 0 SECONDS AFTER POWERON. LOW (APPROXIMATELY 0 VDC) ENERGIZES THE SOFT CONTACTOR K ON THE H.V. AUXILIARY BOARD, ( HIGH, VDC = NOT ENERGIZED). THIS CONTACTOR IS ENERGIZED FOR A MAXIMUM OF APPROXIMATELY 0 SECONDS AFTER POWERON IN ORDER TO CHARGE THE DC BUS CAPACITORS. MAXIMUM SEC. FIGURE V 0 V GENERATOR SWITCHED ON G. SANWALD FEB 00 8 FEB 00 FEB /0 SYSTEM ON MD08 REV A SHEET OF

8 BUCKY DRIVE FROM MD08 V BUCKY RETURN BUCKY BUCKY OUT BUCKY BUCKY READY INTERLOCK # INTERLOCK # BUCKY RETURN BUCKY BUCKY OUT BUCKY VAC OUT VDC OUT BUCKY READY J0 J9 J8 J J J J J J J J J J J J J J J J J RETURN K K F F VDC, 0 / 0 VAC R0 V R VAC FROM MD08 V VDC FROM MD08 V R U K V U R D V R9 U V U K U D TP TP TP TP TP8 TP TP9 8 J J J J J J J J J9 J9 J8 J J8 J V V V V R0 R0 R0 V V R99 R00 U0 DRIVER U BUFFER U BUFFER U BUFFER U0 DRIVER U BUFFER U BUFFER U CPLD U CPLD DOOR INTERLOCK THERMAL SWITCH ROOM LIGHT J0 J9 J J J J R R V V H.V. AUXILIARY BOARD J0 J0 REFER TO CHAPTER OF THE SERVICE MANUAL FOR ADDITIONAL DETAILS REGARDING INTERFACING OF BUCKYS, INTERLOCKS, ETC. REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: K D TP U9 J9 J0 J9 J0 V D Q R98 R U BUFFER R U CPU DATA, ADDRESS, & CONTROL BUS G. SANWALD FEB 00 8 FEB/0 FEB /0 ROOM INTERFACE MD08 REV C SHEET OF

9 NOTE REFERENCE 8 REMARKS LOW (APPROXIMATELY 0 VDC) = BUCKY. HIGH (APPROXIMATELY VDC) = BUCKY NOT REQUESTED TO. LOW (APPROXIMATELY 0 VDC) = BUCKY READY. HIGH (APPROXIMATELY VDC) = BUCKY NOT READY. LOW (APPROXIMATELY 0 VDC) = 0 S.I.D. INTERLOCK CLOSED. HIGH (APPROXIMATELY VDC) = 0 S.I.D. INTERLOCK OPEN. LOW (APPROXIMATELY 0 VDC) = S.I.D. INTERLOCK CLOSED. HIGH (APPROXIMATELY VDC) = S.I.D. INTERLOCK OPEN. LOW (APPROXIMATELY 0 VDC) = BUCKY. HIGH (APPROXIMATELY VDC) = BUCKY NOT REQUESTED TO. LOW (APPROXIMATELY 0 VDC) = BUCKY READY. HIGH (APPROXIMATELY VDC) = BUCKY NOT READY. LOW (APPROXIMATELY 0 VDC) = DOOR INTERLOCK CLOSED. HIGH (APPROXIMATELY VDC) = DOOR INTERLOCK OPEN. LOW (APPROXIMATELY 0 VDC) = THERMAL SWITCH CLOSED. HIGH (APPROXIMATELY VDC) = THERMAL SWITCH OPEN. G. SANWALD FEB 00 8 FEB/0 FEB /0 ROOM INTERFACE MD08 REV C SHEET OF

10 V V V R9 R9 R8 U CPU REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: U XRAY ENABLE TO MD08 TP J8 J DS U U0 U DRIVER CPLD J U0 R V V R9 TP J8 J DS U XRAY R V U CPU DATA, ADDRESS, & CONTROL BUS U9 J PREP J HANDSWITCH ASSY DATA, ADDRESS, & CONTROL BUS J XRAY J PREP J KEYBOARD ASSEMBLY CONSOLE BOARD G. SANWALD FEB 00 FEB/0 FEB /0 XRAY EXPOSURE (RADIOGRAPHIC) MD08 REV A SHEET OF

11 NOTE REFERENCE REMARKS LOW (APPROXIMATELY 0 VDC) = XRAY REQUESTED. HIGH (APPROXIMATELY VDC) = XRAY NOT REQUESTED. LOW (APPROXIMATELY 0 VDC) = PREP REQUESTED. HIGH (APPROXIMATELY VDC) = PREP NOT REQUESTED. G. SANWALD FEB 00 FEB/0 FEB /0 XRAY EXPOSURE (RADIOGRAPHIC) MD08 REV A SHEET OF

12 R R R0 J9 U R U8B R R U8A R0 U0B R R8 R R R J9 J9 J98 KV FEEDBACK SIGNAL FROM PAGE U J J J J U A/D CONV V V J J J J INVERTER DRIVE SIGNAL CONTINUED ON PAGE U CPU R Q R R Q R U D/A CONV U0A R0 TP R9 R R8 R0 UA R8 R D R9 ERROR AMPLIFIERS INCLUDES UA, UB UA UB D R8 R8 D R UA VCO INCLUDES U9, U0, U, U, U, Q UA UB U8A U8B R TP TP R U U R9 R99 DD9 CURRENT SENSE U REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: TP V V V INVERTER SHOOT THRU SENSE, FROM PAGE INVERTER SHOOT THRU SENSE, FROM PAGE J0 J0 J J V = 0 kv OF H.V. FEEDBACK TP8 CPLD TP U9 U INVERTER SHOOT THRU DETECTOR CIRCUITS T R9 T R R V U9 V CPLD TP R R R R9 GATE DRIVE CIRCUIT FOR MOSFET INVERTER (INCLUDES Q9, 0,, ) R R V = kv OF H.V. DEMAND 8 TP R V 0 CPU TP R8 Q V TP R9 TP9 R9 V R8 V R8 9 TP J99 J9 CPLD R9 TP8 R98 R9 V R T T R R0 Q H.V. OIL TANK DATA BUS D0..D J J H.T. PRIMARY CURRENT SENSE FROM PAGE XRAY ENABLE FROM MD08 R G. SANWALD FEB 00 8 FEB/0 FEB /0 KV CONTROL & FEEDBACK MD08 REV A SHEET OF

13 TO J98 PART OF HT TANK kv FEEDBACK TO PAGE TO J9 TO J9 MOSFET INVERTER (INCLUDES QQ) PART OF INVERTER SHOOT THROUGH DETECTOR CIRCUIT E: 0 to 0 VDC () T J J TO J TO J INVERTER SHOOT THRU SENSE, TO PAGE TO J9 * HV ANODE BOARD J ANODE C S L J J J J J J J J E J8 J J HV MULT ASSY (ANODE) E J FROM PAGE INVERTER BOARD E: 0 to 0 VDC () E9 MOSFET INVERTER (INCLUDES QQ) PART OF INVERTER SHOOT THROUGH DETECTOR CIRCUIT E: 0 to 0 VDC () T J J TO J0 TO J0 INVERTER SHOOT THRU SENSE, TO PAGE E0 HV MULT ASSY (CATHODE) J J J J * J J J J E C L S E TANK LID BOARD HV CATHODE BOARD J CATHODE GENERATOR CONTROL BOARD INVERTER BOARD E: 0 to 0 VDC () THIS PAGE DEPICTS 0 KW UNITS (WITH TWO INVERTER ASSEMBLIES. REFER TO PAGE FOR 0//0KW UNITS THAT USE ONE INVERTER ONLY. H.T. PRIMARY CURRENT SENSE, TO PAGE TO J TO J * DEPENDING ON GENERATOR MODEL, THE H.T. TRANSFORMERS MAY USE TWO PAIRS OF SECONDARY WINDINGS, OR THREE SECONDARIES AS SHOWN ABOVE PART OF H.V. OIL TANK G. SANWALD FEB 00 8 FEB/0 FEB /0 KV CONTROL & FEEDBACK MD08 REV A SHEET OF

14 MOSFET INVERTER (INCLUDES QQ) PART OF INVERTER SHOOT THROUGH DETECTOR CIRCUIT E: to 0 VDC () T J J TO J0 TO J0 INVERTER SHOOT THRU SENSE, TO PAGE FROM PAGE J J J J TO E9 AND E0 OF H.V. TANK (PAGE ) E J J J J E GENERATOR CONTROL BOARD INVERTER BOARD E: to 0 VDC () H.T. PRIMARY CURRENT SENSE, TO PAGE TO J TO J NOTE REFERENCE REMARKS A NARROW PULSE WILL BE PRESENT AT THIS TEST POINT IF AN INVERTER SHOOT THROUGH HAS BEEN DETECTED. THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE BELOW. THIS PULSE MAY BE VERY DIFFICULT O DETECT, AS THE INVERTER DRIVE WILL BE SHUT DOWN WHEN A SHOOT THROUGH IS DETECTED, THUS REMOVING THE FAULT CONDITION. AS PER #. A NARROW PULSE WILL BE PRESENT AT THIS TEST POINT IF KV OVER VOLTAGE HAS BEEN DETECTED (0 KV FOR KV UNITS, KV FOR 0 KV UNITS). REFER TO FIGURE. THIS PULSE MAY BE VERY DIFFICULT TO DETECT, AS THE HIGH VOLTAGE WILL BE SHUT DOWN WHEN THE OVER VOLTAGE CONDITION IS DETECTED, THUS REMOVING THE FAULT CONDITION. LOW (APPROXIMATELY 0 VDC) = XRAY REQUESTED BY THE CPU, HIGH (APPROXIMATELY VDC) = NO XRAY REQUEST BY THE CPU. A NARROW PULSE WILL BE PRESENT AT THIS TEST POINT IF INVERTER OVER CURRENT HAS BEEN DETECTED. THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE BELOW. THIS PULSE MAY BE VERY DIFFICULT O DETECT, AS THE INVERTER DRIVE WILL BE SHUT DOWN WHEN AN OVER CURRENT CONDITION S DETECTED, THUS REMOVING THE FAULT CONDITION. LOW (APPROXIMATELY 0 VDC) = NO FAULT PRESENT, ALLOW AN XRAY EXPOSURE. HIGH (APPROXIMATELY VDC) = XRAY EXPOSURE INHIBITED. LOW (APPROXIMATELY 0 VDC) = XRAY REQUESTED BY CONSOLE, HIGH (APPROXIMATELY VDC) = XRAY NOT REQUESTED. LOW (APPROXIMATELY 0 VDC) = NAND GATES UA, UB DISABLED. HIGH (APPROXIMATELY VDC) = NAND GATES ENABLED, THUS ALLOWING INVERTER GATE DRIVE. LOW (0 VDC) = H.V. TANK CONNECTED, HIGH (APPROXIMATELY VDC) = H.V. TANK NOT CONNECTED. THE VOLTAGE AT TP AND TP SHOULD BE A 0% DUTY CYCLE SQUARE WAVE, RANGING IN FREQUENCY FROM APPROXIMATELY 80 khz TO APPROXIMATELY 0 khz, DEPENDING ON GENERATOR OUTPUT POWER. SEE FIGURE. V FIGURE 0 V FIGURE VDC 0 VDC G. SANWALD FEB 00 8 FEB/0 FEB /0 KV CONTROL & FEEDBACK MD08 REV A SHEET OF

15 REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: MAXIMUM FILAMENT CURRENT LIMIT CIRCUIT UA V RNA SET MAX CURRENT JW. A. A ERROR AMPLIFIER, PWM REGULATOR, AND FILAMENT CURRENT DRIVERS V TP U8 D/A CONV UB R0 R8 J J J J RNA RNB RNF UB RNG RNG D RNH UB U PWM REGULATOR TP Q Q Q Q RNH C U CPLD U A/D CONV R R R V D8 Q9 R TP9 TP8 J J J J RNC TP RND TP FILAMENT CURRENT SENSE, RMS CONVERTER, AND FILAMENT FEEDBACK UB UA U RMS CONVERTER V K D, D, 8 T V K J J J J J J J J L S HV CATHODE BOARD J CATHODE C L S R TANK LID BOARD DATA BUS D0..D PART OF H.V. OIL TANK FILAMENT SUPPLY BOARD G. SANWALD FEB 00 8 FEB/0 FEB /0 FILAMENT DRIVE & MA CONTROL MD08 REV B SHEET OF

16 U8A R V = 00 ma OF ANODE CURRENT TP R R R J ANODE S L C HV ANODE BOARD R R0 R R8 R UA R R R0 U A/D CONV V V J J9 R R R0 R8 R9 TP J J9 R R R8 UB R U E8 ma TEST JACK R9 R V E V R8 R U R9 TP U CPLD R J J9 R0 R L S C J J9 R R R R U0A R R DATA BUS D0..D J CATHODE HV CATHODE BOARD TANK LID BOARD PART OF HV OIL TANK G. SANWALD FEB 00 8 FEB/0 FEB /0 FILAMENT DRIVE & MA CONTROL MD08 REV B SHEET OF

17 NOTE REFERENCE, REMARKS VOLT AT THIS TEST POINT = AMP OF FILAMENT DEMAND. LOW (APPROXIMATELY 0 VDC) ENERGIZES K ON THE FILAMENT SUPPLY BOARD (SMALL FILAMENT), HIGH (APPROXIMATELY VDC) DEENERGIZES K (LARGE FILAMENT). 0. VOLT AT THIS TEST POINT = AMP OF ACTUAL FILAMENT CURRENT. VOLT AT THIS TEST POINT = AMP OF ACTUAL FILAMENT CURRENT. PWM OUTPUT. THE WAVEFORM WILL BE AS PER FIGURE FOR LOW AND HIGH FILAMENT CURRENT DEMAND. A NARROW PULSE WILL BE PRESENT AT THESE TEST POINTS DURING SEVERE ANODE OR CATHODE OVER CURRENTS (I.E. TUBE OR TANK ARCS). REFER TO FIGURE. THESE PULSES MAY BE VERY DIFFICULT TO OBSERVE, AS THE HIGH VOLTAGE WILL SHUT DOWN WHEN A FAULT IS DETECTED, THUS REMOVING THE OVER CURRENT SITUATION. Approx usec (0 khz) V LOW FILAMENT DEMAND FIGURE 0 V V HIGH FILAMENT DEMAND 0 V V TP FIGURE 0 V V TP 0 V G. SANWALD FEB 00 8 FEB/0 FEB /0 FILAMENT DRIVE & MA CONTROL MD08 REV B SHEET OF

18 0/0 VAC TO LOW SPEED ER FROM MD08 F F R0 R9 C J J J COM SHIFT MAIN R R R R J U U8 TP V V R9 R9 U TP8 J8 J8 J J BUFFER J J K TP9 U0 U K D9 TP0 J J J J J J DRIVER CPLD D TP V J J J J DATA, ADDRESS, & CONTROL BUS H.V. AUXILIARY BOARD REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: G. SANWALD FEB 00 8 FEB/0 FEB /0 LOW SPEED ER MD08 REV B SHEET OF

19 NOTE REFERENCE REMARKS MAIN STATOR CURRENT SENSE. IF MAIN CURRENT IS LOW, THIS WILL BE APPROXIMATELY VDC. PULSES AT 0 HZ WILL BE PRESENT AS SHOWN IN FIGURE AT NORMAL STATOR CURRENT. PHASESHIFT STATOR CURRENT SENSE. IF SHIFT CURRENT IS LOW, THIS WILL BE APPROXIMATELY VDC. PULSES AT 0 HZ WILL BE PRESENT AS SHOWN IN FIGURE AT NORMAL STATOR CURRENT. LOW (APPROXIMATELY 0 VDC) FOR APPROXIMATELY.8 SEC DURING PREP, THEN PULSED LOW FOR 00 MSEC EVERY SECONDS DURING PREP. REFER TO FIGURE. LOW (APPROXIMATELY 0 VDC) ENERGIZES K ON THE H.V. AUXILIARY BOARD, ( HIGH, VDC = NOT ENERGIZED). THIS RELAY IS ENERGIZED AFTER THE MAIN BUS CAPACITORS ARE CHARGED, APPROXIMATELY 0 SECONDS AFTER POWERON. FIGURE 0 V V THIS APPROACHES 0 V AS CURRENT INCREASES PULSE WIDTH INCREASES AS CURRENT INCREASES FIGURE V 0 V K DEENERGIZED K ENERGIZED APPROXIMATELY.8 SEC. PREP ED G. SANWALD FEB 00 8 FEB/0 FEB /0 LOW SPEED ER MD08 REV B SHEET OF

20 REFER TO PAGE FOR LOGIC LEVELS, NOTES, ETC, REFERENCED BY THIS SYMBOL: U U CPLD DRIVER V VOLTAGE AMPLIFIER J J J J J J J8 J9 CHAMBER CHAMBER CHAMBER CHAMBER FIELD FIELD RIGHT FIELD TO AEC BOARD. REFER TO SHEETS AS APPLICABLE FOR THE AEC BOARD IN YOUR UNIT TP R00 R0 COMPARATOR U UB R0 R0 R0 J J0 J PT RAMP PT REF PT STOP TP U D/A CONV U0B R9 R08 U UD TP CPU R0 DATA, ADDRESS, & CONTROL BUS G. SANWALD FEB 00 8 FEB/0 FEB /0 AEC MD088 REV C SHEET OF

21 FROM PAGE CHAMBER CHAMBER CHAMBER CHAMBER FIELD FIELD RIGHT FIELD FROM MD08 PAGE PT RAMP PT REF PT STOP J J J J J J J8 J9 J J J J8 J J J J0 J J J J J J J J8 J9 J J J J8 J J J J0 J D D TP DS D D D0 D V R88 TP R V V D V V V V DS DS DS DS R R8 U UF R TP UE R R D0 U0A R80 R AEC BOARD SAMPLE & HOLD R TP R D9 TP R8 R8 V Q R R0 R9 UA R R C UB R0 U UC R UD R9 R0 R R8 D8 R D D D D U0B R8 V Q R M R R R R R9 D0 V U9B Q R8 R R8 L R8 R0 UA UB UC UD R R R R L R M R R UA UB UA UB L R M R R L R M R R0 L R M R R R R9 R9 R R R8 R8 R R R R R0 JW JW JW JW J J J J J J J (shell) J J J J J J J J J J J J (shell) J J J J J J J J J J J J (shell) J J J J J J J J J J J J (shell) J J J J J AEC CH ANODE CATH (R) ANODE CATH (R) AEC CH ANODE CATH (R) ANODE CATH (R) AEC CH ANODE CATH (R) ANODE CATH (R) AEC CH ANODE CATH (R) ANODE CATH (R) THIS SHEET APPLIES TO AEC BOARD ASSEMBLY REFER TO CHAPTER D FOR INSTALLATION AND CALIBRATION DETAILS. DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. SWITCHES THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL (0V = OFF, V = ON). G. SANWALD FEB 00 8 FEB/0 FEB /0 AEC MD088 REV C SHEET OF

22 FROM PAGE CHAMBER CHAMBER CHAMBER CHAMBER FIELD FIELD RIGHT FIELD J J J J J J J8 J9 J J J J J J J8 J9 D D D D D V V V V V RNB RNA UE RNC UD RND DS DS DS DS DS UF RNA UA RNE UB RNC RNB UC RND CH RNA CH STRT CH CH V V V V V V * D0 D0 D D V V Q Q Q Q RIGHT * TP V CONVERTER CIRCUIT VDC TO VDC AND 00 / 00 VDC INCLUDES U AND T * * * * * * 00V TP0 SET VALUE TP ** TP9 R9 R /00V V * RIGHT H.V. CH RIGHT CH JW8 JW TP 9 SD R90 JW JW TP 9 SC R8 /00V J /00 V AEC CH H.V. J J /00/00 V V J V J J8 J J0 M FIELD SEL J L/R J9 L FIELD SEL J R/L J R FIELD SEL J R89 J J9 J SIGNAL /00V J /00 V AEC CH H.V. J J /00/00 V V J V J J8 J J0 M FIELD SEL J L/R J9 L FIELD SEL J R/L J R FIELD SEL J R J J9 J SIGNAL FROM MD08 PAGE PT RAMP PT REF PT STOP J9 J J J J J0 J TP8 J9 V TP J V TP TP TP J TP J V TP J R J0 RNC J D U D R RNB TP TP0 UB R R R R UA C CH R SA CH SB CH SC CH SD S R C UB STRT * TP9 UA R R R R STRT SA SB SC SD SAMPLE & HOLD TP CH CH CH CH 8 UA RIGHT CH RIGHT CH JW JW TP 9 SB R8 JW JW TP 9 /00V J /00 V AEC CH H.V. J J /00/00 V V J V J J8 J J0 M FIELD SEL J L/R J9 L FIELD SEL J R/L J R FIELD SEL J R J J9 J SIGNAL /00V J /00 V AEC CH H.V. J J /00/00 V V J V J J8 J J0 M FIELD SEL J L/R J9 L FIELD SEL J R/L J R FIELD SEL J R J J9 J SIGNAL AEC BOARD SA R THIS SHEET APPLIES TO AEC BOARD ASSEMBLY REFER TO CHAPTER D FOR INSTALLATION AND CALIBRATION DETAILS. THE / V OUTPUTS ON J TO J AND J TO J ARE NOT SHOWN ON THIS DIAGRAM. THESE ARE DETAILED ON THE CONNECTOR PIN OUT TABLES IN CHAPTER D. * ** R9 ADJUSTS THE V, 00V, AND 00V OUTPUTS FROM THE DC TO DC CONVERTER CIRCUIT. REFER TO CHAPTER D FOR DETAILS. DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. SWITCHES THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. DESIGNATES A FACTORY CONFIGURED LOGIC OR SIGNAL LEVEL. AEC BOARDS ARE CONFIGURED AT THE TIME OF ORDER TO BE COMPATIBLE WITH THE SPECIFIED AEC CHAMBER(S). FOR EXAMPLE, THE SIGNAL TO THE CHAMBER MAY BE FACTORY CONFIGURED TO BE ACTIVE LOW (0 V), ACTIVE HIGH ( V), OR ACTIVE HIGH ( V). G. SANWALD FEB 00 8 FEB/0 FEB /0 AEC MD088 REV C SHEET OF

23 RIGHT R9 UA RIGHT JW JW R RN RN R RN RN J J ANODE (R) ANODE (R) J J CATH (R) R0 RN RN CATH (R) RN RN 8 J 8 J ANODE (M) UA ANODE (M) UA J UA J J J ANODE (L) ANODE (L) J J J (shell) J (shell) R RN RN R RN8 RN8 R0 AEC CH AEC CH R0 R9 UB R RN RN RN8 RN8 8 8 UB UB UB RIGHT R UC J J ANODE (R) J J CATH (R) JW J JW J ANODE (M) R RN9 RN9 R8 RN0 RN0 J RIGHT J J J ANODE (L) R RN9 RN9 RN0 RN0 8 J 8 J UC U8A J U9A J R R8 ANODE (R) CATH (R) ANODE (M) ANODE (L) CH UD R CH UD R CH OUT (SHT ) CH OUT (SHT ) RIGHT RIGHT CH R0 R R UD RIGHT JW JW R RN RN R RN RN J J ANODE (R) ANODE (R) J J CATH (R) R RN RN CATH (R) RN RN 8 J 8 J UA ANODE (M) UA ANODE (M) U8B J U9B J J J ANODE (L) ANODE (L) J J J (shell) J (shell) R RN RN R RN RN UB R9 RN RN RN RN 8 8 UB UA UA J J ANODE (R) J J CATH (R) JW J JW8 J ANODE (M) R RN RN R8 RN RN J RIGHT J J J ANODE (L) R RN RN RN RN 8 J 8 J UC UC UB J UB J R R R AEC CH AEC CH CH UD R R R ANODE (R) CATH (R) ANODE (M) ANODE (L) CH OUT (SHT ) CH OUT (SHT ) THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 99. THIS PAGE SHOWS THE INPUT CIRCUITS; THE SIGNAL PROCESSING CIRCUITS ARE CONTINUED ON THE NEXT PAGE. REFER TO CHAPTER D FOR INSTALLATION AND CALIBRATION DETAILS. DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. SWITCHES THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL (0V = OFF, V = ON). G. SANWALD FEB 00 8 FEB/0 FEB /0 AEC MD088 REV C SHEET OF

24 V V V V 8 CHAMBER J J R RN RN RN RN DS DS DS DS U 8 CH CH OUT (FROM SHT ) CHAMBER J J R CH CHAMBER J J R CH CHAMBER J J R INVERTING BUFFER CH FIELD FIELD RIGHT FIELD J J J8 J9 J J J8 J9 R R R D8 8 9 RIGHT CH OUT (FROM SHT ) V R TP 0 R R8 FROM PAGE FROM MD08 PAGE J J J J J J V V U V REGULATOR TP TP V R R8 R Q R9 TP UA R R8 UB R UB R R R9 R CH OUT (FROM SHT ) CH PT RAMP PT REF PT STOP J J0 J J J0 J TP V TP R C R9 UA R0 CH CH R R R SAMPLE & HOLD CH OUT (FROM SHT ) V R D8 TP R0 D R R9 R0 CH R U0 AEC BOARD THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 99. THIS PAGE SHOWS THE SIGNAL PROCESSING CIRCUITS; THE INPUT CIRCUITS ARE SHOWN ON THE PREVIOUS PAGE. REFER TO CHAPTER D FOR INSTALLATION AND CALIBRATION DETAILS. DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. SWITCHES THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL (0V = OFF, V = ON). G. SANWALD FEB 00 8 FEB/0 FEB /0 AEC MD088 REV C SHEET OF

25 FROM PAGE CHAMBER CHAMBER CHAMBER CHAMBER FIELD FIELD RIGHT FIELD FROM MD08 PAGE PT RAMP PT REF PT STOP J J J J J J J8 J9 J J J J J0 J J J J J J J J8 J9 J J J J J0 J R R R R R R R R8 V TP0 V R9 V R0 V R DS DS DS DS V TP9 D0 V REGULATOR V R U TP D TP U9 R V TP8 R R0 R V R 8 9 UB U INVERTING BUFFER UA 8 TP R TP CH CH CH CH U8B / * U8A SAMPLE & HOLD R0 R9 V R R R R / Q TP / R8 CH CH CH CH UA V V V V D D0 D9 RIGHT R Q Q Q R Q D RIGHT RIGHT RIGHT RIGHT JW8 JW CH JW JW CH JW JW CH JW JW CH UD UC UB UA 9 R 9 R 9 R 9 R8 TP TP TP TP NO CONNECTION V V V V V V V V R NO CONNECTION R NO CONNECTION R NO CONNECTION R J J J J J8 J J J9 J J J J J8 J J J9 J J J J J8 J J J9 J J J J J8 J J J9 AEC CH N/C /RIGHT /RIGHT V SIGNAL V AEC CH N/C /RIGHT /RIGHT V SIGNAL V AEC CH N/C /RIGHT /RIGHT V SIGNAL V AEC CH N/C /RIGHT /RIGHT V SIGNAL V AEC BOARD THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 998 REFER TO CHAPTER D FOR INSTALLATION AND CALIBRATION DETAILS. DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. SWITCHES THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD FEB 00 8 FEB/0 FEB /0 AEC MD088 REV C SHEET OF

26 NOTE REFERENCE REMARKS GENERATES A PULSE PER FIGURE WHEN THE AEC RAMP IS APPROXIMATELY % OF THE AEC REFERENCE IF THE AEC RAMP IS ON THE CORRECT TRAJECTORY. AEC REFERENCE VOLTAGE, 0 TO 0 VDC, DEPENDING ON AEC TECHNIQUE. THE LENGTH OF THE AEC EXPOSURE IS PROPORTIONAL TO THE AEC REFERENCE VOLTAGE. AEC STOP (PT STOP) SIGNAL. THIS IS NORMALLY HIGH (APPROXIMATELY VDC), SWITCHING LOW WHEN THE AEC RAMP = THE AEC REFERENCE VOLTAGE. REFER TO FIGURE. AEC RAMP. THIS IS A SIGNAL RAMPING FROM 0 TOWARD 0 VDC, THE ACTUAL MAGNITUDE WILL DEPEND ON THE AEC TECHNIQUE. REFER TO FIGURE. AS PER #. PWM OUTPUT. THIS WILL BE VARIABLE WIDTH PULSES (PULSE WIDTH INCREASING AT INCREASING LOAD), UP TO A MAXIMUM OF 0% DUTY CYCLE. REFER TO FIGURE. AEC RAMP OR DC VOLTAGE. THIS IS A RAMP OR DC VOLTAGE, DEPENDING ON AEC CHAMBER TYPE (INTEGRATING OR NONINTEGRATING). REFER TO FIGURE. AS PER #, EXCEPT THAT THE RAMP OR DC VOLTAGE WILL BE POSITIVE GOING AND NOT OF THE SAME MAGNITUDE. THE VOLTAGE AT THIS TEST POINT IS THE OUTPUT OF THE AEC CHAMBER. REFER TO THE AEC CHAMBER MANUFACTURERS DOCUMENTATION FOR DETAILS. THIS IS THE SIGNAL. HIGH ( VDC) = = ANALOG SWITCHES CLOSED, LOW (0 VDC) = = ANALOG SWITCHES OPEN. THIS WILL BE A NEGATIVE DC VOLTAGE. THE MAGNITUDE OF THE DC VOLTAGE IS DEPENDENT ON THE AEC TECHNIQUE IN USE. AS PER #, EXCEPT THAT THE POLARITY WILL BE POSITIVE. THE POLARITY AND MAGNITUDE OF THE RAMP AT THIS POINT SHOULD BE APPROXIMATELY THE SAME AS THE PT RAMP OUTPUT. NOTE REFERENCE. FIGURE FIGURE AEC STOP V 0 V <0 VDC 0 V FIGURE 0 V < 0 VDC OR INTEGRATING AEC CHAMBERS NONINTEGRATING AEC CHAMBERS 00 khz FIGURE VDC 0 VDC G. SANWALD FEB 00 8 FEB/0 FEB /0 AEC MD088 REV C SHEET OF

27 V V DS TP Hz V V V V TP DS Hz DS DS DS DS U R0 TXD R9 RXD R0 U8 TP0 TP U8 RXD R TXD R R U R J8 J R9 CPU R J8 J R8 CPU V DATA BUS D0..D V DS RXD R DS TXD R U R R R R8 RS (LAPTOP) J 8 TXD RTS RXD CTS DATA BUS D0..D CONSOLE BOARD A PULSE TRAIN WILL BE OBSERVED AT TP0, TP DURING CONSOLE GENERATOR COMMUNICATION. THE TXD AND RXD LEDs ON THE CONSOLE BOARD AND WILL FLASH TO INDICATE THE PRESENCE OF THESE PULSES. THIS LED SHOULD FLASH AT A CONSTANT HZ RATE, INDICATING THAT THE CPU IS FUNCTIONAL. G. SANWALD FEB 00 8 FEB/0 FEB /0 SERIAL COMMUNICATIONS MD089 REV A SHEET OF

28 V V Q Q U MICRO CONTROLLER DS V R Q Q V R U RS DRIVER V V R R8 J J J J J J J J8 J9 SWITCHED V TEST V TEST V DOSE DOSE OPTO RELAY DAP CHAMBER R V Q8 R0 R D DATA BUS D0..D G. SANWALD FEB 00 8 FEB/0 FEB /0 DAP MD080 REV A SHEET OF

29 F F TO AC MAINS. SEE MD08, SHEETS TO F TP D TP F J C DS D VDC W MAX THE PRIMARY TAP WILL BE SET TO MATCH THE LINE VOLTAGE IN USE R J 80V 00V 0V 0V 0V J J F J J VAC 0W MAX 0V CUSTOM INTERFACE BOARD G. SANWALD JULY 00 J. CUNNINGHAM JAC JULY 00 JULY 00 AUX VAC / VDC POWER DIST (OPTIONAL) MD08 REV A SHEET OF