Advanced Digital Controls Improve PFC Performance

Transcription

1 Power Supply Design Seminar Advanced Digital Controls Improve PFC Performance Reproduced from 2012 Power Supply Design Seminar SEM2000, TI Literature Number: 2012, 2013 Incorporated Power Seminar topics and online powertraining modules are available at: ti.com/psds

2 Advanced Digital Controls Improve PFC Performance Zhong Ye and Bosheng Sun Abstract A power-factor-correction (PFC) circuit s boost inductor and power MOSFET output capacitance resonate inevitably when the inductor current becomes discontinuous. The resonant current can be big enough to distort the PFC current significantly. In this paper, we will describe a new digital control scheme to predict the optimal MOSFET switching-on position. Using an external Vds sensing signal and the predicted switching-on position, the PFC is able to turn on the MOSFET at the Vds valley or zerovoltage positions to minimize switching loss and reduce PFC current distortion. The digital controller uses oversampling to improve current-sensing accuracy and noise immunity one of the most effective ways to minimize PFC current distortion. An EMI filter s X-cap is the main cause degrading power factor at light load and high line. Digitally delaying the PFC current reference generates a lagging reactive current to compensate for the X-cap s leading reactive current. A 360-W PFC circuit validates the control concepts, with performance improvements demonstrated through test results. I. Introduction A power-factor-correction (PFC) circuit with a power level more than 200 W, as shown in Figure 1, usually uses average current-mode control and operates at a constant switching frequency. The circuit s boost inductor current, i L, can maintain continuous conduction mode (CCM) for certain heavy load ranges. However, at light loads, the current becomes discontinuous. Once the boost inductor current declines to zero, the boost inductor, L, resonates freely with the PFC MOSFET Q1 s output capacitance, C1. The resonant current can be big enough to distort the PFC current significantly, as shown in Figure 2a. Depending on the MOSFET s turn-on time, the resonant current can add to or subtract from the boost inductor current, as shown in the zoom-in waveforms of Figure 2b. Since this effect occurs at much higher frequency than a PFC s current-loop bandwidth at discontinuous conduction mode (DCM), the current loop cannot regulate the boost inductor current fast enough to compensate for the abrupt current disturbance. Figure 1 Experimental digitally controlled 360-W PFC circuit. 7-2

3 (a) AC current distortion at crossover area. The first part of this paper introduces a new, simple zero-current detection circuit and reliable control to minimize PFC current distortion while achieving zero voltage switching (ZVS) or valley switching without using operating-mode switching. Unlike an analog controller, a digital controller uses discrete data for signal processing. Ripple and noise on the sensed signal could easily corrupt the data acquired by single-point sensing per switching cycle. Section IV of this paper will cover one of the most effective ways to improve signal-sensing accuracy and reject noise. Some stringent power-factor specifications have made power-supply design more challenging in the past few years. At light load and high line, the EMI s X-cap s leading reactive current contributes a large percentage of the total current, which results in a low power factor. Section V of this paper will introduce reactive currentcompensation control to minimize the impact of the X-cap. (b) Zoom-in of waveform. II. Circuit Operation and Blanking Time Prediction For steady state operation, a boost inductor s volt second can be considered balanced in each switching cycle. Referring to Figures 1 and 3a, given Q1 s turn-on time, t Da, the time for the boost inductor current, i L, to first return to zero is expressed in Equation 1 [8]. Figure 2 A typical current distortion waveform at light loads. Several techniques include adding a snubber [1] and complex resonant-voltage valley tracking and duty-cycle prediction [2] [3] [4] [5] [6]. Using a snubber to damp the resonant current is an undesirable approach because of the efficiency penalty. Using a fast digital device to predict a boost MOSFET Vds valley position cycle by cycle is expensive. Some solutions also require an operating-mode switch between CCM and DCM operations. Adding an additional winding to a boost inductor for boost-inductor-current-zerocrossing detection is not a popular approach either [6]. (1) After i L becomes negative, the boost inductor, L, resonates with MOSFET capacitance, C1. If instantaneous AC input voltage Vin (= Vac ) is higher than one-half the boost output voltage, Vo, the MOSFET Q1 s Vds never resonates to 0 V, as shown in Figure 3a. If the instantaneous AC voltage is lower than one-half the PFC output voltage, the MOSFET s Vds can resonate to 0 V and be clamped by the MOSFET body diode, as shown in Figure 3b. 7-3

4 (a) MOSFET valley switching. (b) MOSFET ZVS. Figure 3 Resonant period between boost inductor and MOSFET output capacitance. During this resonant period, when the boost inductor current, i L, resonates to a negative value and then a second time returns to zero at time, t x, the volt second applied to the boost inductor maintains balance. Using volt-second balancing, SA = SB + SC, t x can be described as Equation 2: (2) where Vp = Vo-Vin and ωr is the angular frequency of the resonant circuit (ωr = 1/2π Tr). 7-4

5 Equation 2 can be simplified to reduce processor computing time. An approximate t x value can be calculated in Equation 3: (3) t x decreases when Vin increases until Vin is equal to or larger than Vo/2 when the MOSFET Vds starts to oscillate freely. Therefore, t x s low limit should be clamped to Tr/4 by firmware calculation, which is used for valley-switching control. From Equations (1) and (2) or (1) and (3), a predicted pulse-width modulation (PWM) switching period is expressed as Equation 4: (4) These equations apply to both Vin larger and less than one-half Vo. It is possible for a digital controller to update the switching period with the predicted t s cycle by cycle and achieve ZVS or valley switching of the MOSFET s. However, a MOSFET s output capacitance is actually nonlinear versus its drain-to-source voltage. The output capacitance of a typical MOSFET, such as SPP20N60C3, stays relatively constant from 600 V down to 50 V, but the value increases by about 10 times at Vds = 25 V and nearly 100 times at Vds = 0 V. The nonlinearity introduces some error to the calculation when the instantaneous AC voltage is lower than one-half the PFC output voltage. Instead of using t s to update the PWM switching period directly to ensure ZVS, a simple zero Vds and zero i L detection circuit with t s as signalblanking time provides a more reliable control. The circuit consisting of D2, R, C2 and Q2, as shown in Figure 1, generates a synchronous signal, Syn, for controller digital pulse-width modulation (DPWM) synchronization. When the instantaneous AC input voltage Vin (= Vac ) is higher than one-half Vo, the boost inductor, L, resonates freely with the MOSFET output capacitance, C1. For this case, t x is clamped to Tr/4 and the switching period is calculated with Equation 5: (5) 7-5 Q2 is turned on when the main MOSFET, Q1, switches on. Q1 is controlled by the PFC s average-mode current loop. Q2 is turned off at the end of the predicted switching period and the Syn signal restarts a DPWM period when it rises to a valid logic level. As soon as a new period is started, Q1 and Q2 are both turned on at almost the same time when the MOSFET Q1 Vds is at a valley position. The waveforms are shown in Figure 3a. When the Vds valley voltage is lower than 50 V, the nonlinear characteristic of the MOSFET output capacitance starts to affect the Vds waveform, as shown in the dashed line in Figure 4. The actual valley occurs later than the calculated position. However, since the valley becomes flat, the switching loss increase caused by the premature turning on of the MOSFET is insignificant. Figure 4 Effect of nonlinear parasitic capacitance. When the instantaneous AC input voltage, Vin, (= Vac ) is lower than one-half the boost output voltage, Vo, the Vds of the MOSFET always resonates to zero voltage. As in the previous case, Q2 is turned on when the main MOSFET, Q1, switches on. Q2 is turned off at the end of the predicted period, as shown in Figure 3b. To ensure Syn is generated at the point when i L changes from a negative value to a positive value, Q2 should be turned off before the positive current occurs. Theoretically, Q2 can be turned off at any place where i L is negative without affecting circuit performance. However, we have observed that noise could mistrigger a circuit and a PWM period could start prematurely if Q2 is turned off too early. The main task of Q2 here is to block noise and allow the zero-current detection to generate the Syn signal.

6 When load increases and the boost inductor current is continuous, the calculated minimum period ts (= tda + tdb + Tr/2) always becomes larger than the PWM switching period (= tda + tdb) set for normal mode operation. A new switching period starts before Q2 is turned off; therefore, Q2 is on all the time and Syn remains low. For this case, the PFC returns to conventional hard-switching CCM operation, ignoring the input AC voltage. III. ZVS and Valley-Switching Experiment and Test Results We used a 360-W PFC evaluation module [10] with a UCD3040 digital controller [7] for the concept validation. Figure 5a shows input current waveforms at 120-Vac input and 10 percent load with conventional fixed-frequency hard-switching control. Figure 5b shows the reduction of harmonic current with the new control method. The lowfrequency current distortion at the crossover points was almost completely eliminated. Total harmonic distortion (THD) dropped from 5.25 percent to 4.18 percent, while efficiency improved more than 2 percent. Figure 5c shows that the PFC MOSFET achieves both ZVS and ZCS. At high-line input and light loads, MOSFET Q1 operates in either valley switching or ZVS/ ZCS depending on the instantaneous AC voltage. Figures 6a and 6b show current waveforms at 230-V input and 20 percent load before and after applying the new control. The measured THDs are slightly lower with the new control, and the current ripple at switching frequency is greatly reduced. The reduction of measured THD is not as significant as it appears. That is due to the 30th-harmonic measurement limitation of the test equipment. Figure 6c shows Vdc valley switching of Q1. Since the t x calculation equations are valid for both instantaneous AC voltages higher and lower than one-half Vo, no operating-mode switching control is required. When the PFC operates at CCM, the computed period becomes larger than the maximum PWM period, which is set based on hard-switching operation. No Syn pulse is generated. The circuit transitions seamlessly between constant frequency mode and variable frequency mode. Figure 7 and 8 show the PFC THD, power factor and efficiency data. Overall PFC efficiency improved, except at high line and 10 percent load. The efficiency decrease at high line and 10 percent load was due to the additional switching loss caused by the increased switching frequency. At these points, the increased switching loss surpasses the energy saved from valley switching. The digital controller knows its own switching frequency and can calculate or measure output load to disable the valley-switching control (based on preset conditions), avoiding performance degradation and enabling the control to once again gain the efficiency and THD benefit for the rest of operating conditions. 7-6

7 (a) With conventional control: THD = 5.25 percent, power factor (PF) = (b) With proposed control: THD = 4.18 percent, PF = (c) ZVS and ZCS waveforms with proposed control. Figure 5 PFC current harmonic reduction and ZVS/ZCS operation at low line and 10 percent load. 7-7

8 (a) With conventional control: THD = 4.34 percent, PF = (b) With proposed control: THD = 4.18 percent, PF = (c) ZVS and ZCS waveforms with proposed control. Figure 6 PFC current harmonic reduction and ZVS/ZCS operation at high line and 20 percent load. 7-8

9 (a) THD comparison. (b) Power factor correction. (c) Efficiency comparison. Figure 7 THD, PF and efficiency comparison with and without ZVS or valley switching at low line. 7-9

10 (a) THD comparison. (b) Power factor correction. (c) Efficiency comparison. Figure 8 THD, PF and efficiency comparison with and without ZVS or valley switching at high line. 7-10

11 IV. Oversampling Reduces PFC Current Distortion PFC inductor current shape changes dramatically from CCM to DCM, as shown in Figures 9 and 10. With CCM, the current at the mid-point of PWM is the average current; but with DCM, the current is no more an average current. In addition, driver and power-stage delay also contribute to current-sensing variation. Singlepoint current sensing per switching period cannot guarantee that the sensed value is an average value. Current-sensing error can negatively impact THD. Furthermore, a PFC s current-loop bandwidth decreases significantly when operating at DCM, which makes it even more difficult for the PFC current to follow current command. Oversampling effectively averages out current ripple and noise. It minimizes noise effect and improves current-sensing accuracy. Besides that, oversampling scales up the control loop s frequency response to a higher frequency range and increases the loop s bandwidth [9]. Oversampling is one of the most effective ways to reduce PFC current distortion. It has been widely used in high-end PFC product design in the past few years. Figure 11 shows a well-tuned PFC without oversampling and Figure 12 shows the current distortion reduction when 8x oversampling is enabled. Figures 13 and 14 provide THD comparison before and after oversampling is enabled. As you can see, THD is reduced considerably across the whole load range at both high line and low line. We took the current waveforms from a 360-W PFC converter with a UCD3020 controller. There is significant current distortion reduction by using the 8x oversampling technique. Figure 9 PFC inductor current sensing at CCM. Figure 10 PFC inductor current sensing with oversampling at DCM. 7-11

12 Figure 11 Input AC current waveform without oversampling. Figure 12 Input AC current waveform with 8x oversampling. 7-12

13 Figure 13 THD comparison at low line. Figure 14 THD comparison at high line. 7-13

14 V. X-Cap Reactive-Current Compensation AC input EMI filters typically consist of X-caps, Y-caps and common-mode inductors. Some may use different mode inductors for one EMI stage. The X-cap s capacitance has to be sized large enough to absorb most switching current ripple. The larger capacitance X-caps have, the better current ripple attenuation the EMI filter can achieve. However, a large X-cap, often seen in Class-B AC/DC converter designs, can degrade input power factor. The impact of X-caps becomes more significant at high line and light loads, where the leading reactive current generated by the X-caps becomes large enough to affect the total AC current phase. Figure 15 shows the EMI filter with differential current paths, AC voltage and current polarity references for analysis purposes. All capacitor currents, denoted as ic1, ic2 and ic3, contribute to the leading current. In common design practices, the PFC is controlled to draw a current in phase with Vac from input. The total AC input current becomes leading, as illustrated in Figure 16, because of the effect of the X-cap s reactive currents. If an AC reference current iref is generated with a lagging phase and the lagging phase angle is controlled based on X-cap value, input AC voltage and load, the leading reactive current can be fully compensated theoretically, as depicted in Figure 17. Figures 18a and 18b show the waveforms with and without reactive-current compensation. With reactive-current compensation at the specific test condition listed in the figures, the power factor can improve from 0.86 to Note that PF increase is at the cost of THD degradation. Since the PFC is not able to generate enough inductor current at the AC voltage crossover area when a current phase offset is added, the current becomes distorted. Figure 15 A typical EMI filter at PFC input. Figure 16 AC leading current caused by X-caps. Figure 17 X-cap leading current compensation. 7-14

15 (a) With no reactive current compensation (PF = 0.86, THD = 8.8 percent). (b) With reactive current compensation (PF = 0.92, THD = 11.3 percent). Figure 18 PFC control. Test condition: Vin = 220 Vac, Vo = 360 V, load = 108 W. VI. Conclusion We have validated the proposed ZVS and valley-switching control concept. The control uses a synchronization signal generated by external hardware to restart a new PWM cycle for ZVS and valley switching. The predicted time, ts, is used to block noise and prevent mistriggering PWM synchronization. This control proved to be valid for all line and load conditions and both CCM and DCM operations. It allows the PFC to transfer between a constant frequency hard-switching mode and variable-frequency ZVS or valley-switching mode seamlessly, without using any conditional modeswitching mechanism. The control reduces current ripple significantly. It improves PFC overall performance, including THD, power factor and efficiency, at low line and light loads. Good PF improvement and some THD reduction were also achievable at high line. However, we observed an efficiency decrease below 10 percent load and at high line. The controller should disable valley-switching control when a light load is detected in product designs. Oversampling of digital control improves signal-sensing accuracy and noise immunity. It scales up frequency response to a higher frequency region. It increases the control-loop bandwidth without sacrificing its phase margin. Oversampling is one of the most effective ways to reduce harmonics and improve power factor to meet stringent specification requirements in product designs. Digital controllers give the freedom of computing and control, generating a delayed PFC current reference based on variables of X-cap capacitance, input AC voltage and load conditions. The leading reactive current caused by EMI X-cap can be compensated out in real time. Our tests showed a significant power factor improvement. However, the improvement is at the cost of THD. A good design practice can utilize this trade-off between PF and THD to achieve a design goal. 7-15

16 VII. References [1] De Gusseme, K., D.M. Van de Sype, A.P. Van Den Bossche, and J.A. Melkebeek. Input- Current Distortion of CCM Boost PFC Converters Operated in DCM. IEEE Transactions on Industrial Electronics 54 (2007) [2] De Gusseme, K., D.M. Van de Sype, A.P. Van den Bossche, and J.A. Melkebeek. Digitally Controlled Boost Power-Factor-Correction Converters Operating in Both Continuous and Discontinuous Conduction Mode. IEEE Transactions on Industrial Electronics 52 (2005) [3] Huber, Laszlo, Brian T. Irving, and Milan M. Jovanović. Line Current Distortions of DCM/CCM Boundary Boost PFC Converter. IEEE Transactions on Industrial Electronics 54 (2007) [4] Chen, J., A. Prodic, R.W. Erickson, and D. Maksimovic. Predictive Digital Current Programmed Control. IEEE Transactions on Power Electronics 18 (2003) [5] Zhang, W., G. Feng, Y.F. Liu, and B. Wu. A Digital Power Factor Correction (PFC) Control Strategy Optimized for DSP. IEEE Transactions on Power Electronics 19 (2004) [6] Chen, F., and D. Maksimovic. Digital Control for Improved Efficiency and Reduced Harmonic Distortion over Wide Load Range in Boost PFC Rectifiers. IEEE Transactions on Power Electronics 25 (2010) [7] Data Sheet. Fusion Digital Power Controller UCD3040. Accessed June 19, ucd3040. [8] Ye, Zhong, and Bosheng Sun. PFC Efficiency Improvement and THD Reduction at Light Loads with ZVS and Valley Switching. Paper presented at Applied Power Electronics Conference and Exposition (APEC) 2012, February 5-9, [9] Xu, S., and Zhong Ye. Analysis of Oversampling Effects on Digitally Controlled Power Supply Performances. Paper presented at Applied Power Electronics Conference and Exposition (APEC) 2012, February 5-9, [10] Application Note. Fusion Digital Power UCD3138 PFC EVM- PWR026. Accessed June 19,

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