Topology: Active Clamp Forward Device: UCC2897A Unless otherwise mentioned the measurements were done with about 2A output current.

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1 Startup... 2 2 Shutdown... 4 3 Efficiency... 6 4 Load Regulation... 7 5 Line Regulation... 8 6 Output Ripple Voltage... 9 7 Input Ripple Voltage... 10 8 Load Transients.

1 1 Startup Shutdown Efficiency Load Regulation Line Regulation Output Ripple Voltage Input Ripple Voltage Load Transients Control Loop Frequency Response Miscellaneous Waveforms Input Voltage = 36V Input Voltage = 48V Input Voltage = 60V Thermal Image Addendum Topology: Active Clamp Forward Device: UCC2897A Unless otherwise mentioned the measurements were done with about 2A output current. This design is dedicated to a RF application design topic is low reflected ripple and low output ripple. So the converter itself is powered across a differential input filter, the output filter uses ceramics only. Due to constant load the output capacitance is pretty low, but fully sufficient for constant current. A minimum load >100mA is required to ensure BIAS power. Page 1 of 32

2 1 Startup The startup waveform is shown in the Figure 1. The input voltage was set to 36V. Ch1=> input voltage 10V/div Ch2=> output voltage 10V/div 5ms/div Figure 1 The startup waveform is shown in the Figure 2. The input voltage was set to 48V. Ch1=> input voltage Ch2=> output voltage 10V/div 5ms/div Figure 2 Page 2 of 32

3 The startup waveform is shown in the Figure 3. The input voltage was set to 60V. Ch1=> input voltage Ch2=> output voltage 10V/div 5ms/div Figure 3 Page 3 of 32

4 2 Shutdown The shutdown waveform is shown in the Figure 4. The input voltage was set to 36V. The power supply was disconnected. Ch1=> input voltage 10V/div Ch2=> output voltage 10V/div 2ms/div Figure 4 The shutdown waveform is shown in the Figure 5. The input voltage was set to 48V. The power supply was disconnected. Ch1=> input voltage Ch2=> output voltage 10V/div 2ms/div Figure 5 Page 4 of 32

5 The shutdown waveform is shown in the Figure 6. The input voltage was set to 60V. The power supply was disconnected. Ch1=> input voltage Ch2=> output voltage 10V/div 2ms/div Figure 6 Page 5 of 32

6 3 Efficiency The efficiency curves are shown in the Figure 7 below. Measurements were done with resistor load. Inductor is MSS KE, suited up to 1.6Amps load. Figure 7 Page 6 of 32

7 4 Load Regulation The load regulation of the output is shown in the Figure 8 below. Measurements were done with resistor load. Figure 8 Page 7 of 32

8 5 Line Regulation The line regulation is shown in Figure 9. Measurements were done with electronic EL 100. Figure 9 With the same setup the efficiencies are shown in Figure 10. Figure 10 Page 8 of 32

9 6 Output Ripple Voltage The output ripple voltage (measured at J2 bottom side) is shown in Figure 11 output 50mV/div Ch2 => output 50mV/div Ch3 => output 50mV/div AC coupled 20MHz bw 2µs/div Figure 11 The output voltage ripple voltage is well below specified 100mVpp, here 40mVpp, means only 0.14% for a 28V output. The filtered reflected input voltage ripple is around 40mVpp, at the converter input close to 1Vpp; This, differential filter provides roughly an attenuation of 40mV/880mV, means -27dB. Page 9 of 32

10 7 Input Ripple Voltage The input ripple voltage is shown in Figure 12 (measured at J1 bottom side). input voltage 60V 50mV/div Ch2 => input voltage 48V 50mV/div Ch3 => input 50mV/div AC coupled 20MHz bw 2µs/div Figure 12 The input ripple voltage is shown in Figure 13 (measured near C9). input voltage 60V 200mV/div Ch2 => input voltage 48V 200mV/div Ch3 => input 200mV/div AC coupled 20MHz bw 2µs/div Figure 13 Page 10 of 32

11 8 Load Transients The Figure 14 shows the response to load transients. The load is switching from 1A to 2A with a frequency of 75Hz. The input voltage was set to 36V output voltage 1V/div Ch2=> output current 1A/div 2ms/div Figure 14 The Figure 15 shows the response to load transients. The load is switching from 1A to 2A with a frequency of 75Hz. The input voltage was set to 48V output voltage 1V/div Ch2=> output current 1A/div 2ms/div Figure 15 Page 11 of 32

12 The Figure 16 shows the response to load transients. The load is switching from 1A to 2A with a frequency of 75Hz. The input voltage was set to 60V output voltage 1V/div Ch2=> output current 100mA/div 20MHz bandwidth setting 2ms/div Figure 16 The converter itself is designed for CONSTANT load, transient response around du 2V for a transient di of 1A; this means a deviation of 7%. For dynamic loads output capacitance needs to be increased and loop to be adjusted. For loads <100mA BIAS needs to be changed from buck to peak detection or additional auxiliary power via diode ORing. For continuous load >1.5A the output inductor needs a custom design (220uH, 2.5Arms, 3.0Asat, shielded, ferrite) Page 12 of 32

13 9 Control Loop Frequency Response Figure 17 shows the loop response. 2A-load applied. The input voltage was set to 36V (Electronic load). Figure 17 Figure 18 shows the loop response. 2A-load applied. The input voltage was set to 36V (resistor load) Figure 18 Page 13 of 32

19 Figure 20 shows the loop response. 2A-load applied.

14 Figure 19 shows the loop response. 2A-load applied. The input voltage was set to 48V (Electronic load) Figure 19 Figure 20 shows the loop response. 2A-load applied. The input voltage was set to 48V (resistor load). Figure 20 Page 14 of 32

15 Figure 21 shows the loop response. 2A-load applied. The input voltage was set to 60V (Electronic load). Figure 21 Figure 22 shows the loop response. 2A-load applied. The input voltage was set to 60V(resistor load). Figure 22 Page 15 of 32

16 Table 1 summarizes the results from the frequency response measurements with electronic load. Vin 36V 48V 60V Bandwidth (khz) Phase margin slope (20dB/decade) gain margin (db) slope (20dB/decade) freq (khz) Table 1 Table 2 summarizes the results from the frequency response measurements with resistor load. Vin 36V 48V 60V Bandwidth (khz) Phase margin slope (20dB/decade) gain margin (db) slope (20dB/decade) freq (khz) Table 2 Page 16 of 32

17 10 Miscellaneous Waveforms 10.1 Input Voltage = 36V The waveform of the voltage on switchnode Q2 (drain-source) is shown in Figure 23. 1µs/div full bandwidth 50ns/div Figure 23 Delay resistor RT of 2.2kOhm offers a shiny drain waveform but less QR switching and less efficiency; screenshots are taken w/ RT of 16kOhm. Placing 2k55 to 16k in parallel and switching 2k55 shows the difference; 2k2 means hard switching. Page 17 of 32

18 The waveform of the voltage on Q1 (PMOS) drain-source is shown in Figure 24. 1µs/div full bandwidth 50ns/div Figure 24 Page 18 of 32

19 The waveform of the voltage at the transformer output is shown in Figure V/div 1µs/div full bandwidth 50V/div 100ns/div Figure 25 Page 19 of 32

20 10.2 Input Voltage = 48V The waveform of the voltage on switchnode Q2 (drain-source) is shown in Figure 26. 1µs/div full bandwidth 50ns/div Figure 26 Page 20 of 32

21 The waveform of the voltage on Q1 (PMOS) drain-source is shown in Figure 27. 1µs/div full bandwidth 50ns/div Figure 27 Page 21 of 32

22 The waveform of the voltage at the transformer output is shown in Figure V/div 1µs/div full bandwidth 50V/div 100ns/div Figure 28 Page 22 of 32

23 10.3 Input Voltage = 60V The waveform of the voltage on switchnode Q2 (drain-source) is shown in Figure 29. 1µs/div full bandwidth 50ns/div Figure 29 Page 23 of 32

24 The waveform at Q2 gate-source is shown in Figure 30 5V/div 1µs/div full bandwidth 5V/div 20ns/div Figure 30 Page 24 of 32

25 The waveform of the voltage on Q1 (PMOS) drain-source is shown in Figure 31. 1µs/div full bandwidth 50ns/div Figure 31 Page 25 of 32

26 The waveform of the voltage on Q1 (PMOS) gate-source is shown in Figure 32. 5V/div 1µs/div full bandwidth 5V/div 20ns/div Figure 32 Page 26 of 32

27 The waveform of the voltage at the transformer output is shown in Figure V/div 1µs/div full bandwidth 50V/div 100ns/div Figure 33 Page 27 of 32

28 11 Thermal Image Figure 34 shows the thermal image at 48V input voltage and 1A output current. Figure 34 Figure 35 shows the thermal image at 48V input voltage and 1.5A output current. Figure 35 Page 28 of 32

5 C 41.3 C 47.7 C U3 42.1 C 42.4 C 50.5 C Q1 37.5 C 37.6 C 42.6 C D3 37.1 C D4 37.

29 Figure 36 shows the thermal image at 48V input voltage and 2A output current. Figure 36 Table 3 sumarizes the last three figures. Name 1A 1.5A 2A L C 67.4 C 93.4 C Q C 41.3 C 47.7 C U C 42.4 C 50.5 C Q C 37.6 C 42.6 C D C D C Table 3 For continuous output current >1.5A the output inductor needs a custom design (220uH, 2.5Arms, 3.0Asat, shielded, ferrite) Page 29 of 32

30 12 Addendum Added RC-snubber on switchnode (secondary side) to GND2 across lowside Schottky. Figure 37 is the waveform of the switchnode without snubber circuit. 100ns/div full bandwidth Figure 37 Figure 38 is the waveform of the switchnode with snubber (here used 430pF+27Ohms) 100ns/div full bandwidth Figure 38 RF noise and overshoot could be reduced simply by adding 470pF (E6) / 33 Ohms (E6) or similar. Page 30 of 32

31 Figure 38 is the waveform of the transformer output (with snubber). See Figure 28 to compare the waveform with the waveform without snubber 50V/div 1µs/div full bandwidth 50V/div 100ns/div full bandwidth Figure 39 Page 31 of 32

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SEPIC, added CC charging by additional current ctr ( via TLC272) TPS40210 and CSD18563Q5A

SEPIC, added CC charging by additional current ctr ( via TLC272) TPS40210 and CSD18563Q5A 1 Startup 3 2 Shutdown 5 3 Efficiency 7 4 Load Regulation 8 5 Line Regulation 9 6 Output Ripple Voltage 10 7 Input Ripple Voltage 10 8 Load Transients 11 9 Control Loop Frequency Response 13 9.1 Resistive