Preliminary DATA SHEET VWA Product-Line

Transcription

1 VWA AA Description The VWA AA is a distributed amplifier designed on a 0.15 µm phemt process. The device includes an internal biasing circuit which can be used to feed directly the drain current, as an alternative to bias the drain from the HF-Output access. Depending on the desired low cut off frequency, external components can be added to ensure operations started from 30KHz to 2GHz through up to 40GHz. The device includes also an embedded output signal detector and an embedded input gate biasing circuit which can be used to reduce the power consumption in many linear receiving amplifier chains. It is capable of more than +21dBm of output power at saturation regime, up to 40GHz. And more than +17dBm of output power at 1 db of gain compression, up to 34GHz. It provides more than 12 db of linear gain from DC to 44 GHz with a positive slope of dB/GHz, up to 40 GHz. This device can provide up to 10 db gain up to 50 GHz with an excellent group delay. Optimized biasing configurations are proposed depending on the input power level pattern. Features DC to 44 GHz 12 db 21 dbm Medium Power Amplifier with Half-Inductor-bias option Distributed amplifier phemt GaAs MMIC Wide band: DC to 46 GHz. Internal biasing access. Flat group delay. 50ΩRF Single ended input and output DC coupled IN, DC coupled Out P1dB >+17dBm DC to 34GHz High output Psat >+21dBm DC to 40GHz Small signal gain : >12dB from 2GHz to 40GHz Nominal Power Supply: V 2.29 x x 0.1mm (VWA AA) Applications Up to 50GBps, E/O Modulator driver (3V/75mA) Receiver chain amplification Wide band MPA Radar / ECM / ECCM Test and measurement Broadband / datalink communication S2P file can be provided for system design simulation. DXF file is available for mechanical design. Evaluation board available on request. Ordering information Product code VWA AA Definition Single Die VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 1 /4

2 Typical Characteristics Tamb = 25 C, VD = +6V, VG1A=0V, VG2=+2.5V, ID = 162 ma. Parameter measured Symbol Min Typ Max Unit Frequency range F DC 40 GHz Small signal gain G 12.5 db Average gain positive slope + ΔG db/ghz Small signal gain flatness ΔG +/-1 db Input return loss S db Output return loss S22 12 db Output P1 db from DC to 34GHz P1dB dbm Saturated output power PSat 21 dbm Drain supply voltage VD 6 V Supply current ID 162 ma Environmental parameters Environment Parameters Symbols Min Max Units Storage temperature Tst C Operating temperature Top C Absolute maximum ratings Maximum ratings Symbols Min Max Units Positive external DC bias voltage VD 9 V RF input power (In) Pin max 18 dbm Temperature process max 20 secondes T process 325 C Continuous power dissipation (@ 85 C) Pcw 2.5 W Handling This product is sensitive to electrostatic discharge and should not be handled except at a static free workstation. Take precautions to prevent ESD; use wrist straps, grounded work surfaces and recognized anti-static techniques when handling the VWA AA device. VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 2 /4

3 Mechanical view Pin out and Pad positions Die thickness = 100µm Die bottom must be connected to ground (RF and DC) VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 3 /4

4 Access description Pin number 2 HF_AMP_INPUT 4 VG2 5 VDLoad 15 HF_AMP_OUTPUT 7 VDL_IN 8 VSELF_OUT 9 VSELF_IN Name Description Electrical interface HF Amplifier input, This access is DC coupled and internally matched to 50Ohms. Gate control input access for second stage distributed amplifier structure. Apply +2.5V for nominal biasing conditions. Drain termination load decoupling access. This access must be connected to a MIM 100pF or 1000pF capacitor, with a low serial inductance bonding wire. HF Amplifier output, This access is DC coupled and internally matched to 50Ohms. It can also be used to feed the drain current (ID), by using a wide bandwidth external Bias-T structure. Input drain line access, if internal biasing circuit is used, it must be connected to VSELF_IN by using a small bonding wire connection. Biasing circuit input pad access, if internal biasing circuit is used; it must be connected to VDD power supply. Depending on the working bandwidth, some additional external components can be added (See end of documents for explanations). Biasing circuit embedded pad access, if internal biasing circuit is used; it must be connected to VDL_IN by using a small bonding wire connection. 10 VB_REF Biasing reference diode access 11 VREF Reference diode voltage access 12 VDET_OUT Detector output 13 VDET_IN Detector Input 17 VG1_A 18 VG1_B Gate control output access for first stage distributed amplifier structure. It can be connected to a negative power supply voltage source in order to decrease the drain current consumption. Or it can be left open. Gate control input access for first stage distributed amplifier structure. It can be connected directly to the amplifier access by a small bonding wire. Die Bottom GND Die must be connected to HF and DC Ground VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 4 /4

5 Die on RF probes measurement results using external biasing conditions: VD=+6V, VG2=+2.5V, VG1B=Left open, ID=162mA, T=25 C. S21 (db) Group Delay (ps): S11 (db): S22 (db): P1dB: PSAT: VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 5 /4

6 VWA_ _AA mounted in a K connector housing using Internal Biasing Circuit: Note : This configuration with external inductor help to ensure applications from 30 KHz to up to 40GHz. For application from 2GHz to 40GHz, an external capacitor can be used instead of external inductors. Blue curve: VD=+6V, VG2=+2.5V, VG1B=left open, ID=162mA, T=25 C. Green curve: VD=+5V, VG2=+1.6V, ID=70mA, VG1B=-11V, T=25 C. Gain measurement of the VWA_ _AA mounted in a K connector housing using Internal Biasing Circuit: S21 (db): VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 6 /4

7 Return loss measurement of the VWA_ _AA mounted in a K connector housing using Internal Biasing Circuit: S11 (db): S22 (db): VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 7 /4

8 Power measurement of the VWA_ _AA mounted in a K connector housing using Internal Biasing Circuit: VD=+6V, VG2=+2.5V, VG1B=left open, ID=162mA, T=25 C. P1dB: PSAT: Power measurement of the VWA_ _AA mounted in a K connector housing using Internal Biasing Circuit: VD=+5V, VG2=+1.6V, ID=70mA, VG1B=-11V, T=25 C. P1dB: PSAT: VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 8 /4

9 28GBps Telecoms measurements of the VWA_ _AA mounted in a K connector housing using Internal Biasing Circuit: Measure on Agilent 86100C, without precision time base and with 50GHz electronic head. 28GBps Input Eye diagram: 0.6Vpp Intput Eye diagram: Time scale 20ps/div, Amplitude scale =150mV/div. 28GBps Output Eye diagram: VD=+3V, VG2=+1V, VG1=left open, ID=75mA. 2.2Vpp Output Eye diagram: Time scale 20ps/div, Amplitude scale =400mV/div. VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 9 /4

10 50GBps Telecoms measurements of the VWA_ _AA mounted in a K connector housing using Internal Biasing Circuit: Measure on Agilent 86100C, without precision time base and with 50GHz electronic head. 50GBps Input Eye diagram: 0.7Vpp Intput Eye diagram: Time scale 10ps/div, Amplitude scale =150mV/div. 50GBps Output Eye diagram: VD=+3V, VG2=+1V, VG1=left open, ID=75mA. 3Vpp Output Eye diagram: Time scale 10ps/div, Amplitude scale =500mV/div. VWA AA DS Rev1.0 VectraWave Proprietary information subject to change without notice April 2016 p 10 /4