CHA2093 RoHS COMPLIANT

Transcription

1 CHA93 RoHS COMPLIANT -3GHz Low Noise Amplifier GaAs Monolithic Microwave IC Description Vd The CHA93 is a two-stage wide band monolithic low noise amplifier. The circuit is manufactured with a standard phemt process:.5µm gate length, via holes through the substrate, air bridges and electron beam gate lithography. It is supplied in chip form. IN 5 Vg 1 Vg 5 OUT Main Features Broad band performance -3GHz.dB noise figure, -3GHz 15dB gain, ±.5dB gain flatness Low DC power consumption, 5mA dbm 3rd order intercept point Chip size: 1.7 x 1.3 x.1mm Gain ( db ) Frequency ( GHz ) Noise Figure ( db ) On wafer typical measurements. Main Characteristics Tamb = +5 C Symbol Parameter Min Typ Max Unit NF Noise figure, -3GHz. 3. db G Gain db G Gain flatness ±.5 ± 1. db ESD Protections : Electrostatic discharge sensitive device observe handling precautions! Ref. : DSCHA Oct 3 1/ Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 1 - B.P Orsay Cedex France Tel. : +33 () Fax : +33 ()

2 CHA93-3GHz Low Noise Amplifier Electrical Characteristics Tamb = +5 C, Vd = +V Id=5mA Symbol Parameter Min Typ Max Unit Fop Operating frequency range 3 Ghz G Gain (1) db G Gain flatness (1) ±.5 ± 1. db NF Noise figure (1). 3. db VSWRin Input VSWR (1) 3.:1 VSWRout Ouput VSWR (1) 3.:1 IP3 3rd order intercept point dbm P1dB Output power at 1dB gain compression 13 dbm Id Drain bias current 5 ma (1) These values are representative of on-wafer measurements that are made without bonding wires at the RF ports.when the chip is attached with typical.15nh input and output bonding wires, the indicated parameter values should be improved. Absolute Maximum Ratings (1) Tamb = +5 C Symbol Parameter Values Unit Vd Drain bias voltage 5. V Pin Maximum peak input power overdrive () + dbm Top Operating temperature range - to +5 C Tstg Storage temperature range -55 to +15 C (1) Operation of this device above anyone of these paramaters may cause permanent damage. () Duration < 1s. Ref. : DSCHA Oct 3 / Specifications subject to change without notice Route Départementale 1, B.P ORSAY Cedex - FRANCE Tel.: +33 () Fax : +33 ()

3 -3GHz Low Noise Amplifier CHA93 Typical Results Chip Typical Response (On wafer Sij) Tamb = +5 C Bias Conditions : Vd = +V Id=5mA Freq GHz MS11 db PS11 MS1 db PS1 MS1 db PS1 MS db PS Ref. : DSCHA Oct 3 3/ Specifications subject to change without notice Route Départementale 1, B.P ORSAY Cedex - FRANCE Tel.: +33 () Fax : +33 ()

4 CHA93-3GHz Low Noise Amplifier Typical Results Chip Typical Response ( On wafer Sij ) : Tamb = +5 C Vd = V ; Id = 5mA 15 Gain, RLoss ( db ) DBS11 DBS Gain Frequency ( GHz ) Typical Gain and Matching measurements on wafer. Gain, NF ( db ) Gain NF Gab Frequency ( GHz ) Typical Gain and Noise Figure measurements on wafer Ref. : DSCHA Oct 3 / Specifications subject to change without notice Route Départementale 1, B.P ORSAY Cedex - FRANCE Tel.: +33 () Fax : +33 ()

5 -3GHz Low Noise Amplifier CHA93 Typical Results Tamb = +5 C Vd = V ; Id = 5mA F=GHz Output power (dbm) Gass (db) Pout Gain Input power (dbm) F=3GHz 1 1 Output power (dbm) 1 1 Pout Gain 1 1 Gass (db) Input power (dbm) Typical Output Power and Gain measurements in test jig (included losses of the jig) Ref. : DSCHA Oct 3 5/ Specifications subject to change without notice Route Départementale 1, B.P ORSAY Cedex - FRANCE Tel.: +33 () Fax : +33 ()

6 CHA93-3GHz Low Noise Amplifier Typical Chip Assembly To Vd DC Drain supply feed pf IN OUT pf pf To Vg1 DC Gate supply feed To Vg DC Gate supply feed Mechanical data Ref. : DSCHA Oct 3 / Specifications subject to change without notice Route Départementale 1, B.P ORSAY Cedex - FRANCE Tel.: +33 () Fax : +33 ()

7 -3GHz Low Noise Amplifier CHA93 Chip Biasing This chip is a two stage amplifier, and flexibility is provided by the access to number of pads. The internal DC electrical schematic is given in order to use these pads in a safe way. Vd 5 5 IN OUT Vds1 Vds The two requirements are: Vg 1 Vg N 1: Not exceed Vds = 3.5V (internal Drain to Sour ce voltage) N : Not biased in such a way that Vgs becomes posi tive. (internal Gate to Source voltage) We propose two standard biasing: Low Noise and low consumption: Vd = 3.5V and Id = 3mA ( Vg1=Vg) Low Noise and high output power: Vd =.V and Id = 5mA. A separate access to the gate voltages of the first and the output stage is provided. Nominal bias is obtained for a typical current of 3mA for the output stage and 15 ma for the first stage. The first step to bias the amplifier is to tune the Vg1 =-1V and Vg to drive 3mA for the full amplifier. Then Vg1 is reduced to obtain 5 ma of current through the amplifier. Ref. : DSCHA Oct 3 7/ Specifications subject to change without notice Route Départementale 1, B.P ORSAY Cedex - FRANCE Tel.: +33 () Fax : +33 ()

8 CHA93-3GHz Low Noise Amplifier Ordering Information Chip form : CHA93-99F/ Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use as critical components in life support devices or systems without express written approval from United Monolithic Semiconductors S.A.S. Ref. : DSCHA Oct 3 / Specifications subject to change without notice Route Départementale 1, B.P ORSAY Cedex - FRANCE Tel.: +33 () Fax : +33 ()