15W Power Packaged Transistor. GaN HEMT on SiC

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1 Gain (db), Pout (dbm) & PAE (%) Drain Current (A) CHK15A-QIA Description The CHK15A-QIA is an unmatched packaged Gallium Nitride High Electron Mobility Transistor. It offers general purpose and broadband solutions for a variety of RF power applications. It is well suited for multi-purpose applications such as radar and telecommunication. The CHK15A-QIA is developed on a.5µm gate length GaN HEMT process. It requires an external matching circuitry. It is proposed in low cost plastic package providing low parasitic and low thermal resistance. GaN HEMT on SiC Main Features Wide band capability: up to 6GHz Pulsed and CW operating modes High power: > 15W High Efficiency: up to 7% DC bias: Id=1mA Low cost package: 14L-DFN3x4 MTTF > 1 6 Tj=2 C V DS = 5V, I D_Q = 1mA, Freq = 2.9GHz Pulsed mode (1µs, 1%) Pout PAE ID Gain Input Power (dbm) Performances on S-band Evaluation Board Main Electrical Characteristics Tcase= + C, Pulsed mode, F = 3GHz, V DS =5V, I D_Q =1mA Symbol Parameter Min Typ Max Unit Gain Linear Gain 18 2 db Pout Output Power 15 2 W PAE Max Power Added Efficiency 6 % G PAE_MAX Associated Gain at Max PAE 16 db Ref. : DSCHK15A-QIA Dec 15 1/18 Specifications subject to change without notice United Monolithic Semiconductors S.A.S.

2 CHK15A-QIA Recommended DC Operating Ratings Tcase= + C Symbol Parameter Min Typ Max Unit Conditions V DS Drain to Source Voltage 5 V V GS_Q Gate to Source Voltage -1.9 V V D =5V. I D_Q =1mA I D_Q Quiescent Drain Current.1.35 A V D =5V I D_MAX Drain Current.65 (1) A V D =5V. compressed mode I G_MAX Gate Current (forward 24 ma Compressed mode mode) T j_max Junction temperature (1) 2 C (1) Power dissipation must be considered DC Characteristics Tcase= + C Symbol Parameter Min Typ Max Unit Conditions V P Pinch-Off Voltage V V D =5V. I D = I DSS /1 I D_SAT Saturated Drain Current 2.7 (1) A V D =7V. V G =2V I G_leak Gate Leakage Current -.8 ma V D =5V. V G =-7V (reverse mode) V BDS Drain-Source 18 V V G =-7V. I D =2mA Break-down Voltage R TH Thermal Resistance (2) 6 C/W CW (1) For information, limited by I D_MAX. see on Absolute Maximum Ratings (2) CW mode, reference = package back-side RF Characteristics Tcase= + C. Pulsed mode Symbol Parameter Min Typ Max Unit Conditions G SS Small Signal 3GHz Small Signal 6GHz db db V D =5V. I D_Q =1mA P SAT Saturated Output Power 15 2 W V D =5V. I D_Q =1mA PAE G PAE_MAX Max 3GHz Max 6GHz Associated Gain at Max 6GHz % % db db V D =5V. I D_Q =1mA V D =5V. I D_Q =1mA These values are the intrinsic performance of the packaged device. They are deduced from measurements and simulations. They are considered in the reference plane defined by the leads of the package, at the connection interface with the PCB. The typical performance achievable in more than 1% frequency band around 3GHz was demonstrated using the reference board presented hereafter. Ref. : DSCHK15A-QIA Dec 15 2/18 Specifications subject to change without notice

3 CHK15A-QIA Absolute Maximum Ratings (1) (2) (3) Tcase= + C Symbol Parameter Rating Unit Note V DS Drain-Source Biasing Voltage 6 V V GS_Q Gate-Source Biasing Voltage V I G_MAX Maximum Gate Current (forward 48 ma mode) I G_MIN Minimum Gate Current (reverse -2 ma mode) I D_MAX Maximum Drain Current 2 A (4) P IN Maximum Input Power (5) T j Junction Temperature 22 C T STG Storage Temperature -55 to +15 C T Case Case Operating Temperature See note C (4) (1) Operation of this device above anyone of these parameters may cause permanent damage. (2) Duration < 1s. (3) The given values must not be exceeded at the same time even momentarily for any parameter, since each parameter is independent from each other. Otherwise deterioration or destruction of the device may take place. (4) Max junction temperature must be considered (5) Linked to and limited by I G_MAX & I G_MIN values. Maximum input power depends on frequency. Simulated Source and Load Impedances V DS = 5V. I D_Q = 1mA Zs Zl Frequency Zs Zl Pout (W) PAE (%) (MHz) j j j j j j j j j j j j The impedances are chosen as a trade-off between Output Power. PAE and Stability of the device. These values are given in the reference plane defined by the connection between the transistor leads and the PCB according to the footprint above mentioned Ref. : DSCHK15A-QIA Dec 15 3/18 Specifications subject to change without notice

4 CHK15A-QIA Typical Simulated Package Sij parameters Tamb. = + C. V DS = 5V. I D_Q = 1mA Freq (GHz) S11 (db) PhS11 ( ) S12 (db) PhS12 ( ) S21 (db) PhS21 ( ) S22 (db) PhS22 ( ) These values are given in the reference plane defined by the connection between the transistor leads and the PCB according to the footprint previously mentioned Ref. : DSCHK15A-QIA Dec 15 4/18 Specifications subject to change without notice

5 S parameters (db) S parameters (db) CHK15A-QIA Typical Simulated S-parameters Tcase = + C. CW mode. V DS =5V. I D_Q =1mA S11 S Frequency (GHz) S21 S12+2dB Frequency (GHz) Ref. : DSCHK15A-QIA Dec 15 5/18 Specifications subject to change without notice

6 MSG/MAG (db) K Factor CHK15A-QIA Simulated Maximum Gain & Stability Characteristics Tcase= + C. CW mode. V DS =5V. I D_Q =1mA 35 3 MSG/MAG K Frequency (GHz) Ref. : DSCHK15A-QIA Dec 15 6/18 Specifications subject to change without notice

7 Gain (db), Pout (dbm) & PAE (%) Drain Current (A) Gain (db), Pout (dbm) & PAE (%) Drain Current (A) CHK15A-QIA Typical Performance on Evaluation Board (ref 61522) Calibration and measurements are done on the connector access planes of the evaluation boards. Tamb. = + C. Pulsed Mode (1). V DS =5V. I D_Q =1mA Pout. PAE. Gain & Freq=2.9GHz Pout PAE ID Gain Input Power (dbm) Pout. PAE. Gain & Pin=27dBm Pout PAE ID Gain Frequency (GHz) (1) Input RF and gate voltage are pulsed. Conditions are 1µs width. 1% duty cycle and 1µs offset between DC and RF pulse. Ref. : DSCHK15A-QIA Dec 15 7/18 Specifications subject to change without notice

8 Gain (db), Pout (dbm) & PAE (%) Drain Current (A) CHK15A-QIA Typical Performance on Evaluation Board (ref 61522) Calibration and measurements are done on the connector access planes of the evaluation boards. Tamb. = + C. Pulsed Mode (1). V DS =5V. I D_Q =1mA Pout. PAE. Gain & Pin=3dBm Pout PAE ID Gain Frequency (GHz) (1) Input RF and gate voltage are pulsed. Conditions are 1µs width. 1% duty cycle and 1µs offset between DC and RF pulse. Ref. : DSCHK15A-QIA Dec 15 8/18 Specifications subject to change without notice

9 Sij (db) CHK15A-QIA Typical Performance on Evaluation Board (ref 61522) Calibration and measurements are done on the connector access planes of the evaluation boards. Tamb. = + C. CW mode. V DS =5V. I D_Q =1mA S parameters versus frequency S21 S11 S Frequency (GHz) Ref. : DSCHK15A-QIA Dec 15 9/18 Specifications subject to change without notice

10 Gain (db), Pout (dbm) & PAE (%) Drain Current (A) Gain (db), Pout (dbm) & PAE (%) Drain Current (A) CHK15A-QIA Typical Performance in Temperature (on Evaluation Board) Calibration and measurements are done on the connector access planes of the evaluation boards. Tamb. = -4 C, +8 C, Pulsed Mode (1), V DS =5V, I D_Q =1mA Pout, PAE, Gain & 2.9GHz & -4 C C Pout PAE ID Gain Input Power (dbm) Pout, PAE, Gain & 2.9GHz & +8 C C Pout PAE ID Gain Input Power (dbm) (1) Input RF and gate voltage are pulsed. Conditions are 1µs width, 1% duty cycle and 1µs offset between DC and RF pulse. Ref. : DSCHK15A-QIA Dec 15 1/18 Specifications subject to change without notice

11 Input Return Loss (db) Linear Gain (db) CHK15A-QIA Typical Performance in Temperature (on Evaluation Board) Calibration and measurements are done on the connector access planes of the evaluation boards. Tamb. = -4 C, + C, +85 C, CW mode. V DS =5V, I D_Q =1mA + C) Linear Gain versus temperature with ID_Q each temperature (1mA) 2 15 C -4 C 1 85 C Frequency (GHz) Input Return Loss versus temperature with I D_Q each temperature (1mA) -4 C -5 C 85 C Frequency (GHz) Ref. : DSCHK15A-QIA Dec 15 11/18 Specifications subject to change without notice

12 Output Return Loss (db) CHK15A-QIA Typical Performance in Temperature (on Evaluation Board) Calibration and measurements are done on the connector access planes of the evaluation boards. Tamb. = -4 C, + C, +85 C, CW mode. VDS=5V, ID_Q=1mA + C) Output Return Loss versus temperature with I D_Q each temperature (1mA) C -4 C C Frequency (GHz) Ref. : DSCHK15A-QIA Dec 15 12/18 Specifications subject to change without notice

13 CHK15A-QIA Demonstration Amplifier Low Frequency Equivalent Schematic (Ref ) Vg + + Vd J IN Q1 OUT J J3 16 Demonstration Amplifier Bill of Materials (Ref ) Designator Type Value - Description Qty 24 Capacitor 1pF. +/-.1pF Capacitor 4.7pF. +/-.pf Capacitor 3.9pF. +/-.pf Capacitor 2pF. +/- 5% Capacitor 1pF. +/- 5% Capacitor 1nF. +/- 5% Capacitor 1µF. +/- 1% Capacitor 68µF. +/- 2% 1 Resistor 49.9Ω. +/- 1% Resistor 3Ω +/- 1% Resistor 1Ω +/- 1% J1 Connector CMS 6cts 1 J2. J3 Connector SMA 2 Q1 Packaged Transistor CHK15A-QIA 1 - PCB TACONIC RF35P h=.23mm - Ref. : DSCHK15A-QIA Dec 15 13/18 Specifications subject to change without notice

14 CHK15A-QIA Demonstration Amplifier Circuit Outline (Ref ) Ref. : DSCHK15A-QIA Dec 15 14/18 Specifications subject to change without notice

15 CHK15A-QIA Demonstration Amplifier Circuit (Ref ) Ref. : DSCHK15A-QIA Dec 15 15/18 Specifications subject to change without notice

16 CHK15A-QIA Package outline Tcase (A) ( C) Matte tin. Lead Free (Green) 1- Nc 6- Nc 11- D2 Units : mm 2- Nc 7- Nc 12- D1 From the standard : JEDEC MO G1 8- Gnd 13- Nc 4- G2 9- Nc 14- Gnd 15- Gnd 5- G3 1- D3 (A) Tcase locates the reference point used to monitor the device temperature. This point has been taken at the device / system interface to ease system thermal design. Ref. : DSCHK15A-QIA Dec 15 16/18 Specifications subject to change without notice

17 CHK15A-QIA Notes Ref. : DSCHK15A-QIA Dec 15 17/18 Specifications subject to change without notice

18 CHK15A-QIA Recommended package footprint Refer to the application note AN17 available at for package foot print recommendations. SMD mounting procedure For the mounting process standard techniques involving solder paste and a suitable reflow process can be used. For further details, see application note AN17. Recommended environmental management UMS products are compliant with the regulation in particular with the directives RoHS N 211/65 and REACh N 197/26. More environmental data are available in the application note AN19 also available at Recommended ESD management Refer to the application note AN2 available at for ESD sensitivity and handling recommendations for the UMS package products. Ordering Information DFN 3x4 package: CHK15A-QIA/XY Stick: XY = 2 Tape & reel: XY = 21 Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use as critical components in life support devices or systems without express written approval from United Monolithic Semiconductors S.A.S. Ref. : DSCHK15A-QIA Dec 15 18/18 Specifications subject to change without notice