A Jitter Attenuating Timing Chain

Transcription

1 In preparation for submission to ASYNC 7. Please do not distribute A Jitter Attenuatg Timg Cha Suwen Yang, Student, IEEE, and Mark R. Greenstreet, Member {swyang, mrg}@cs.ubc.ca Φ long wire long wire... Φ Fig.. Forwardg a clock through a cha of verters 35 Abstract A long cha of verters and wire segments will amplify clock jitter and drop timg pulses due to tersymbol terference. We present jitter attenuatg buffer based on surfg techniques. Our buffer circuit consists of a few verters with variable put strength. We show how this implements a simple, low-ga DLL. Chas of these surfg buffers attenuate jitter and reliably propagate timg pulses. As with traditional DLLs, our design can be used to generate multiple, evenly spaced clock phases for multi-phase clocked circuits, precharged logic, and other high speed logic families. I. INTRODUCTION Consider the problem of forwardg a clock signal through a cha of buffers and long wire segments as shown Figure. Such chas can be used clock distribution networks or for clock forwardg for source-synchronous communication. A fundamental problem for such a design is jitter accumulation along the cha. Even if all of the verters are of the same design, and all of the wires are of the same length, random variations due to power-supply noise, crosstalk, temperature variation, and tra-chip parameter variation add jitter at each, and this jitter is cummulative. Furthermore, tersymbol terference (ISI) effects (aka draftg []) are known to be jitter amplifyg []. Thus, a sufficiently long buffer cha will drop clock pulses even when operatg at low clock frequencies. Figure shows the maximum length cha through which a clock signal can propagate reliably as a function of clock frequency. Similar problems occur when usg asynchronous signallg. Simple handshakg protocols cur large penalties cycle time due to the round trip delay for sendg the data forward and an acknowledgment back. To avoid these disadvantages, we would like to use credit-based protocols where the sender can transmit up to K values before receivg an acknowledgment. In this case, the requests from the transmitter form pulses that can be dropped due to timg variations and ISI just as the synchronous case. Phase-locked loops (PLLs) and delay-locked loops (DLLs) overcome the limitations of simple buffer chas by actively compensatg for jitter. Unfortunately, these circuits require much more power and lay area than simple verters. Thus, it is not practical, for example, to forward a clock for a sourcesynchronous lk usg a PLL or DLL at each repeater. This work was supported by grants from Intel, SUN Microsystems, and NSERC. Please note that this is an early draft. Comments and suggestions are very welcome. Fig.. Number of repeaters before clock pulses are dropped Clock frequency (GHz) WARNING: This plot is completely made up! We ve seen behaviour like this some of our design We ll perform the SPICE simulations and get real data before submittg the paper to ASYNC 7. Forwardg a clock through a cha of verters In this paper, we show how a very simple modification to the verter cha design produces a low-ga DLL at each. This is sufficient to prevent jitter accumulation. Furthermore, asynchronous applications, the same design can be used to wavepipele request and acknowledge pulses reliably, enablg the use of credit based protocols. Our design is based on the surfg techniques troduced [3]; it is power efficient and fully static. Thus, we expect our approach to scale well to deep-submicron processes and provide a practical solution to forwardg clocks designs with multiple timg domas, and forwardg handshakg signals asynchronous designs. We will start the paper with a brief troduction ab surfg theory and then troduce the revised surfg verter. In section III, we proposed a simple delay-locked loop and compared it with the traditional delay-locked loop. In section IV, we formulated a high precision timg cha and studied its workg frequency. II. SURFING Surfg is a variation on wavepipelg [4] where each logic element the pipele is modified to have a put (see Figure 3). When is asserted, the delay of the gate is lower than when is not. A surfg pipele also cludes a timg cha that propagates a pulse for the signals. The key ideas behd surfg is to design the logic elements and the timg cha delays so that the maximum delay of a logic element when is asserted is less than the delay of

2 Data Path: Timg Cha: data_ Φ D Q D Q data_ Φ 8.78 Fig. 3. A Surfg Pipele the correspondg of the timg cha. This ensures that events the data path do not propagate slower than the high terval of the pulse. Conversely, the mimum delay of a logic element when is not asserted must be greater than the delay of the timg cha. This ensures that events the data path do not propagate er than the low terval of the pulse. Together, these two conditions ensure that events the data path are attracted to the risg edge of the timg pulse. This limits the uncertaty the delays the data path, and allows arbitrarily long, latchless pipeles to be implemented. Surfg refers to the way that events the data path propagate on the risg edge of the timg pulse wave. Surfg was first proposed [3], [5] where the delay variation for the logic elements was achieved by pre-switchg, effectively creatg a small fight between the put of the gate and a source follower to shift the gate put slightly anticipation of the next transition. This approach was demonstrated a test chip described [6] where a twelve surfg rg was fabricated and tested Two, dependent, surfg waves of computation were propagated around the rg for over 48 hours, with any errors. However, pre-switchg is power tensive. Thus, [6] also proposed an energy efficient approach to achievg surfg by usg charge sharg domo circuits. More recently, [7] presented a fully static approach to surfg for terconnect application. In this case, surfg is achieved by usg an ordary verter and a tri-state verter parallel. When the tri-state verter is enabled, the delay of the the verter is reduced compared with when the verter is the only element drivg the put. Our surfg clock buffer is a simple modification of the design from [7]. Figure 4 shows our design. We simulated this surfg verter with a.3pf capacitive load usg TSMC.8µ process and plotted the delay curve as shown Figure 5. Let t denote the time of a transition on the = put of the surfg verter; let t denote the time of a transition on the put; and let t denote the time of the resultg transition on the put. The vertical axis is the delay, d: d = t t The horizontal axis is the time separation, t s, from the arrival of the signal to the arrival of the signal: t s = t t [t s,m,t s,max ] defes the stable surfg terval. If we cha surfg verters together and an put event falls to this region, then subsequent events along the cha will stay this region. As long as the period of is between d max and d m, the put of a cha of this surfg verters will be attracted to have the same frequency as. Fig. 4. Fig. 5. delay(s) The Surfg Inverter x d max 3.6 t s,m delay of the surfg verter.4x +.47e operatg pot ts,max dm separation time(s) x The Delay of the Surfg Inverter III. DELAY-LOCKED LOOP Figure 6 is a textbook delay locked loop(dll). It is composed of three parts: the variable delay le, phase detector and loop filter. This DLL suffer from the jitter peakg problem( [8]) because it cannot distguish between put clock jitter and put clock jitter. The type DLL shown Figure 7 uses another reference clock to avoid the jitter peakg problem. With a surfg verter, we are able to build a simple delaylocked loop as shown Figure 8. The size of the surfg verter is the same as that Figure 4. The delay element is just a cha of the same verters. The size of the NMOS is.48µ and PMOS.96µ respectively. Here, is a delayed version of the put. Because the clock s risg and fallg events are terleavg, we use the current event to predict when the next put event should happen. To lock the delay, the previous event must fall the stable surfg region of the next put event. With this constrat, we can derive the followg equation for the put period quite easily: (d m + t s,max + D) P max((d max + t s,m + D), ) () where D is the delay of the delay element. Takg the delay curve as shown Figure 5 as an example, the simple circuit can work with the period rangg from (D -5 )ps to (76 + D)ps. Assume that the circuit is now operatg at the pot labelled by the star Figure 5. Then from the delay curve,

3 3 with t s with -73ps to 8ps, we can model the delay curve as a lear function d = αt s + 43ps with α equal to.4. Under small disturbance, the circuit is characterized with the followg equation: reference phase detector put clock loop filter t = α t + ( α) t () Assume that the first event of is disturbed by t and elsewhere. We use s i to denote the i th event on signal s. We only start to number the events followg the put disturbance. Then with some simple mathematics, the put disturbance is a sequence t i, = ( α) i α t (3) The summation of the sequence is t. However, the circuit spread the disturbance the subsequent events. The jitter the circuit degraded as a ratio of ( α). Figure fig:dlloper shows the operation of a surfg DLL. The DLL works at.ns. One pulse comes 44ps later than the expected time. After 6 events, the DLL get the delay locked. We summarized the advantages of the surfg DLL as follows: ) The surfg verter combes the function of phase detector and variable delay element. It is very simple ) It takes use of the fact that for a clock signal, s and s are terleavg. We use the surfg verter to correctly predict when the next event should happen. 3) It avoids jitter peakg because α is less than. However, this affects the trackg bandwidth and lock time. With lear approximation, the period variation of the type surfg DLL is ( α)(t s,max t s,m ). 4) It removes the loop filer because α is less than. The type surfg DLL is straightforward. It is shown Figure 9. Here, the reference clock and put clock has a phase shift greater than 8 o to correctly predict the terleavg risg and fallg events. Due to the extra surfg verter, the jitter this circuit attenuated as a ratio of ( α). We can also construct a phase-locked loop as shown Figure. Because of the surfg effect, the frequency of the put are tracked to the frequency of the signal. We use the subscript c to denote the current state and f to the fal state. If current circuit works with period P c, to ensure the phase get locked, the circuit has to work the lear region of the delay curve. This imposes the followg constrat on the period the circuit can be locked: Fig. 6. Fig. 7. Type DLL clock source reference Type DLL phase detector put clock loop filter Figure shows the operation of a surfg PLL. At first, the period of the is.5ns and then adjusted to.7ns. After 9 events, the frequency of the put is locked to that of the signal. It may be misunderstood that this surfg PLL should have the same workg frequency as the surfg DLL Figure 6. The difference is that: that surfg DLL use the current event to predict when the next put event should happen. Hence the current signal must fall to the stable surfg region of the put event. However, the surfg PLL use the current put event and current event to generate the next put event. IV. PIPELINED TIMING WITH LOCAL FEEDBACK A pipeled timg cha can be used to crease the throughput of a wire by allowg multiple bits to be flight at the same time. We can use the surfg DLL to implement each of such a pipele, as shown Figure 4. The mimum period of the clock is limited by the right side of equation. If P satisfies that constrat and D is large enough, unlike the delay element P f,m = P c +(t s,c t s,max ) P f P c +(t s,c t s,m ) = P f,max Fig. 8. (4) Then the sequence of the separation time between the put and signal will be t s,i = t,i t,i = t s,f + ( α) i (t s,c t s,f ) (5) The period attenuates at the rate of α. With some calculation, we found that: P f,m (d m + D) and P f,max (d max + D) given any P c rangg from (d m + D) to (d max + D). Hence the circuit works with period satisfies the followg constrat: (d m + D) P f (d max + D) (6) Fig. 9. Type Surfg DLL Type Surfg DLL reference

4 4 4 x with supply noise with supply noise * vcha deviation of the delay(s) Fig put event arrival time(s) Jitter Attenuation of the Surfg DLL x 8 voltage(v) Voltages (l).. m 9m 8m 7m 6m 5m 4m 3m m delay element m Fig.. A Surfg PLL 39n 39n 39n 393n 394n 395n 396n 397n 398n 399n Time (l) (TIME) time(s) verter cha, this timg cha can propagate the pulses with losg any pulse: We put a constrat on D because here the draftg effect (ISI) plays an important role. The draftg effect pulls consecutive risg and fallg clock edges together and causes pulses to be lost. In contrast, the surfg effect works to mata uniform separation of edges. For very small clock periods, the draftg effect domates the surfg effect, and clock pulses will be lost the timg pipele. Thus, the maximum operatg frequency is the one at which draftg and surfg are balance. To obtta a periodic put, the clock s period should not exceed (d max + t s,m + D). At lower frequencies, the cha will propagate all clock events, but it no longer preserves uniform spacg. Thus, jitter will grow with pipele length if the clock period is too large. Due to the surfg effect, the surfg verter cha is less sensitive to power supply noise than a simple verter cha. We simulated the verter cha with PMOS size equal to 9.7µ and NMOS 3.6µ respective. In Figure 3, the solid period(s) Fig x time(s) Period Lockg of the Surfg PLL put x 8 Fig. 3. The Simulation of Inverter Cha clock source clock clock clock3 Fig. 4. The Sgle Phase Surfg Pipele Timg Cha curve is the put of the th with no power supply noise and the dashed curve is the put of the same but with % power supply noise. With no power supply noise, the verter cha can propagate the pulses till s at 5MHZ with losg pulses. However, with % power supply noise, the cha loses pulses. We also apply % power supply noise to the surfg verter cha. Figure 5 shows the put of the th with and with power supply noise. We simulated a -s cha for 5n. We measured both the absolute jitter and the relative jitter: the absolute jitter is measured with respect to a perfectly periodic reference signal; the absolute jitter refers to the period-toperiod variation. Along the cha, the maximum relative jitter is 6.% and the standard deviation of the relative jitter is.8%. The surfg cha can only reduce the relative jitter but not the absolute jitter. If the current event comes later, because of the surfg effect, it will push the next event comg later. Many high speed logic families such as OPL [9] and surfg gates [6] require several tightly spaced clock phases to control prechargg and other operations. It is difficult and power tensive to generate these phases globally and distribute them through a separte clock network for each phase. This motivates

5 5 with supply noise with supply noise * dllcha with power supply noise voltage(v) Voltages (l) Fig m 9m 8m 7m 6m 5m 4m 3m m m -m 4n 43n 44n 45n 46n 47n 48n 49n 5n Time (l) (TIME) time(s) The simulation of the Sgle Phase Surfg Pipele Timg Cha developg ways to locally generate the required clock phases for these logic families. Fairbanks [] used an analog C- element to build micropipele rgs for evenly high precision timg. However, power consumption and robustness were not examed. We can use surfg verters to build a pipeled timg cha as shown Figure 6. The cha has three channels to simplify the analysis because it is symmetric. Every is a delay-locked loop, similar to that shown Figure 6. However D is not constant any more. Suppose that the cha reaches a stable state and number the events on a of all three channels by a particular event time. We use T n,j to denote the time ofthe j th event of n. Assume that a one unit disturbance happens on the first event on put of and no other disturbance elsewhere. Then T n,j = C n n+j αn ( α) j t (7) Also the summation of T n,j is equal to. Thus, the cha spreads the disturbance to every and event. For every, the maximum disturbance happens at the k th event alpha alpha where k is equal to n. When n and k are large enough, we can use the followg approximation to calculate the disturbance: T n,k = αn.5 π( α) (8) The cha works for periods rangg from 6(d max + D + t s,m ) to 6(d m + D + t s,max ). Compared to the one Fig. 6. The Multiple Phase Surfg Pipele Timg Cha channel cha, the trackg bandwidth creases by 4(d m d max + t s,mmax t s,m ) if D is the same. With the lear approximation, the clock s period P = 6(( α)t s +D +D) where D is a constant. Usg the surfg verter as shown Figure 4, the cha works with the period from.8ns to.7ns and the cha works with 4.5% of sgle pulse disturbance. As before, we applied a sgle event disturbance to the cha. The disturbance is equal to % of the period. With the period equal to.3ns, we simulated a - surfg cha for 5ns. Figure 7 is the relative jitter of every, and Figure 8 plots the maximum absolute jitter along the cha. The Matlab simulation of the cha calculated with Equation 7 by settg α to.5 is the red curve Figure 7. Before 5 th, the hspice simulation result matches quite well with the Matlab simulation result. After that, the cha is not settled at.3ns while the disturbance propagated there. Figure 9 the logarithmic scale of the maximum absolute jitter along s. When n is large enough, we may use a le with slope equal to.53 to approximate the maximum absolute jitter. This matches very well with Equationeq:approx. We have also performed Matlab simulations of the surfg cha where the put clock has jitter. As noted above, the disturbance for each event is spread around the s of a cha. The total jitter at any arises from the sum of the contributions from the jitter for each cycle of the put clock. Assumg that these are dependent random variables, we fd that the total jitter at each decreases with the number of s. Figure shows the attenuation of relative jitter when a three-channel timg cha is driven from a clock with a.ns period and % jitter. Absolute jitter also decreases with the number of s, but at a somewhat slower rate. Figure (fig:maxerrpow) shows the maximum absolute jitter of the timg cha under % power supply noise. As described above, the cha does not attenuate absolute jitter, and we see this grow learly with the length of the cha. However, the relative jitter is controlled by the cha. We observed a maximum relative jitter of 8.7%, and its standard deviation is.86%. This suggests that our surfg timg cha can be used reliably for clock forwardg for on-chip, sourcesynchronous communication. The accumulation of absolute jitter must be taken to account when designg deskew or synchronization circuits at the receivg end of the lk.

6 6 Fig. 7. disturabce(s) x The Relative Jitter with Sgle Event Disturbance channel channel channel 3 log of disturbance matlab simulation with a =.5 hspice simulation.53log(n).79 disturbance(s).4 x hspice simulation matlab simulation with a =.5 The Maximum Absolute Error with One Sgle Event Distur- Fig. 9. bance(ii) log of s Fig The Maximum Absolute Jitter with One Sgle Event Disturbance(I) V. CONCLUSIONS We troduced a surfg verter. This verter combes the role of phase detector and variable delay element. With this surfg verter, we built a simple delay-locked loop. This DLL only contas a surfg verter and the delay element. By settg the lear slope α less than, the DLL can reach a stable frequency and avoid the jitter peakg problem associated with the type DLL. For one channel timg cha, with only the surfg verters, with the frequency range, we can propagate the clock signal fately. Though the draftg effect tries to pull the events together, the surfg effect pushes the events away. For multi-channel timg cha, we generated evenly spaced clockd with high resolution. We built the mathematic model and analysed its workg frequency. REFERENCES [] A. J. Wstanley, A. Garivier, and M. R. Greenstreet, An event spacg experiment, Proceedgs of the Eighth International Symposium on Asynchronous Circuits and Systems, Manchester, UK, Apr., pp [] G. Balamurugan and N. Shanbhag, Modelg and mitigation of jitter multigbps source-synchronous I/O lks, st International Conference on Computer Design, 3, pp [3] B. D. Wters and M. R. Greenstreet, A negative-overhead, self-timed pipele, Proceedgs of the Eighth International Symposium on Asynchronous Circuits and Systems, Manchester, UK, Apr., pp [4] W. P. Burleson, M. Ciesielski, et al., Wave-pipelg: a tutorial and research survey, IEEE Transactions on VLSI Systems, vol. 6, no. 3, pp , Sept disturbance(s) Fig.. Fig.. disturbance(s).8 x channel channel 3 channel 5 5 Attenuation of a Clock Jitter 7 x The Maximum Absolute Error with Power Supply Noise

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