Design an EEG front end according to the following specifications

Transcription

1 Problem set 2 Due in class April 3 Design an EEG front end according to the following specifications. The amplitude of the EEG signal will go up to 2 microvolts and contain features of interest between Hz and Hz. 2. Remember that the electrodes will probably have a contact potential between and 3 mv. 3. Your front end system should act as an input to a 6 bit analog to digital converter with a maximum Voltage swing of ±2.5 Volts (note: this is different than I suggested on the blackboard in class.) 4. If you need a frequency filter, I recommend a second order Sallen-Key design. 5. You will be using an INA4 instrumentation amplifier, and as may TL72 opamps as you need for your filters. I have attached data sheets for these devices. Have fun. You will learn a lot by doing this. Resources Guide to Opamps (really good) Filter design tool: er/filter.html The OpenEEG project

2 INA4 INA4 INA4 Precision INSTRUMENTATION AMPLIFIER FEATURES! LOW OFFSET VOLTAGE: 5µV max! LOW DRIFT:.25µV/ C max! LOW INPUT BIAS CURRENT: 2nA max! HIGH COMMON-MODE REJECTION: 5dB min! INPUT OVER-VOLTAGE PROTECTION: ±4V! WIDE SUPPLY RANGE: ±2.25 to ±8V! LOW QUIESCENT CURRENT: 3mA max! 8-PIN PLASTIC AND SOL-6 APPLICATIONS! BRIDGE AMPLIFIER! THERMOCOUPLE AMPLIFIER! RTD SENSOR AMPLIFIER! MEDICAL INSTRUMENTATION! DATA ACQUISITION 7 V+ DESCRIPTION The INA4 is a low cost, general purpose instrumentation amplifier offering excellent accuracy. Its versatile 3-op amp design and small size make it ideal for a wide range of applications. A single external resistor sets any gain from to,. Internal input protection can withstand up to ±4V without damage. The INA4 is laser trimmed for very low offset voltage (5µV), drift (.25µV/ C) and high common-mode rejection (5dB at G = ). It operates with power supplies as low as ±2.25V, allowing use in battery operated and single 5V supply systems. Quiescent current is 3mA maximum. The INA4 is available in 8-pin plastic and SOL-6 surface-mount packages. Both are specified for the 4 C to +85 C temperature range. (3) 2 V IN (4) (2) R G 8 (5) + 3 V IN (5) Over-Voltage Protection Over-Voltage Protection A 25k! 25k! A 2 25k! 25k! INA4 25k! A 3 25k! Feedback (2) 6 () 5 () DIP Connected Internally Ref V O G = + 5k! R G DIP 4 V (7) (SOIC) International Airport Industrial Park Mailing Address: PO Box 4, Tucson, AZ Street Address: 673 S. Tucson Blvd., Tucson, AZ 8576 Tel: (52) 746- Twx: Internet: FAXLine: (8) (US/Canada Only) Cable: BBRCORP Telex: FAX: (52) Immediate Product Info: (8) INA4 992 Burr-Brown Corporation PDS-42D Printed in U.S.A. March, 998 SBOS4

3 SPECIFICATIONS ELECTRICAL At T A = +25 C, V S = ±5V, R L = 2k!, unless otherwise noted.! Specification same as INA4BP/BU. NOTE: () Temperature coefficient of the 5k! term in the gain equation. INA4BP, BU INA4AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS INPUT Offset Voltage, RTI Initial T A = +25 C ± + 2/G ±5 + /G ±25 + 3/G ±25 + 5/G µv vs Temperature T A = T MIN to T MAX ±. +.5/G ± /G ± /G ± + /G µv/ C vs Power Supply V S = ±2.25V to ±8V.5 + 2/G 3 + /G!! µv/v Long-Term Stability ±.2 +.5/G! µv/mo Impedance, Differential 6!! pf Common-Mode 6!! pf Input Common-Mode Range ± ±3.5!! V Safe Input Voltage ±4! V Common-Mode Rejection V CM = ±V, "R S = k! G = db G = db G = 2 6 db G = db BIAS CURRENT ±.5 ±2! ±5 na vs Temperature ±8! pa/ C OFFSET CURRENT ±.5 ±2! ±5 na vs Temperature ±8! pa/ C NOISE VOLTAGE, RTI G =, R S =! f = Hz 5! nv/#hz f = Hz! nv/#hz f = khz! nv/#hz f B =.Hz to Hz.4! µvp-p Noise Current f=hz.4! pa/#hz f=khz.2! pa/#hz f B =.Hz to Hz 8! pap-p GAIN Gain Equation + (5k!/R G )! V/V Range of Gain!! V/V Gain Error G = ±. ±.5!! % G = ±.2 ±.4! ±.5 % G = ±.5 ±.5! ±.7 % G = ±.5 ±! ±2 % Gain vs Temperature G = ±2 ±! ± ppm/ C 5k! Resistance () ±25 ±!! ppm/ C Nonlinearity G = ±. ±.! ±.2 % of FSR G = ±.5 ±.2! ±.4 % of FSR G = ±.5 ±.2! ±.4 % of FSR G = ±.2 ±.! ±.2 % of FSR OUTPUT Voltage I O = 5mA, T MIN to T MAX ±3.5 ±3.7!! V V S = ±.4V, R L = 2k! ± ±.5!! V V S = ±2.25V, R L = 2k! ± ±.5!! V Load Capacitance Stability! pf Short Circuit Current +2/ 5! ma FREQUEY RESPONSE Bandwidth, 3dB G =! MHz G =! khz G =! khz G =! khz Slew Rate V O = ±V, G =.3.6!! V/µs Settling Time,.% G = 8! µs G = 2! µs G = 2! µs G =! µs Overload Recovery 5% Overdrive 2! µs POWER SUPPLY Voltage Range ±2.25 ±5 ±8!!! V Current V IN = V ±2.2 ±3!! ma TEMPERATURE RANGE Specification 4 85!! C Operating 4 25!! C $ JA 8! C/W The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. INA4 2

4 PIN CONFIGURATIONS P Package R G V IN V + IN V U Package Top View 8-Pin DIP R G V+ V O Ref SOL-6 Surface-Mount Top View ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. R G V IN V + IN V R G V+ Feedback V O Ref PACKAGE/ORDERING INFORMATION PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER () RANGE INA4AP 8-Pin Plastic DIP 6 4 C to +85 C INA4BP 8-Pin Plastic DIP 6 4 C to +85 C INA4AU SOL-6 Surface-Mount 2 4 C to +85 C INA4BU SOL-6 Surface-Mount 2 4 C to +85 C NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS () Supply Voltage... ±8V Input Voltage Range... ±4V Output Short-Circuit (to ground)... Continuous Operating Temperature... 4 C to +25 C Storage Temperature... 4 C to +25 C Junction Temperature C Lead Temperature (soldering, s) C NOTE: () Stresses above these ratings may cause permanent damage. 3 INA4

5 TYPICAL PERFORMAE CURVES At T A = +25 C, V S = ±5V, unless otherwise noted. Gain (V/V) k GAIN vs FREQUEY Common-Mode Rejection (db) COMMON-MODE REJECTION vs FREQUEY G =, k G = G = k G = G = G = k k k M Frequency (Hz) k k k M Frequency (Hz) Common-Mode Voltage (V) INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE Limited by A + Output Swing A 3 Output Swing Limit Limited by A 2 Output Swing V D/2 V D/2 V CM + + (Any Gain) Output Voltage (V) Limited by A 2 + Output Swing V O A 3 + Output Swing Limit Limited by A Output Swing Power Supply Rejection (db) POSITIVE POWER SUPPLY REJECTION vs FREQUEY k k k M Frequency (Hz) G = G = G = G = Power Supply Rejection (db) NEGATIVE POWER SUPPLY REJECTION vs FREQUEY G = G = G = k k k M Frequency (Hz) G = Input-Referred Noise Voltage (nv/! Hz) k INPUT-REFERRED NOISE VOLTAGE vs FREQUEY G =, k Frequency (Hz) G = G = G = BW Limit k INA4 4

6 TYPICAL PERFORMAE CURVES (CONT) At T A = +25 C, V S = ±5V, unless otherwise noted. 2 SETTLING TIME vs GAIN 6 OFFSET VOLTAGE WARM-UP vs TIME Settling Time (µs) %.% Offset Voltage Change (µv) G! Gain (V/V) Time from Power Supply Turn-on (s) Input Bias and Input Offset Current (na) ±I B INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE I OS Temperature ( C) Input Bias Current (ma) G = INPUT BIAS CURRENT vs DIFFERENTIAL INPUT VOLTAGE G = G = G = Differential Overload Voltage (V) Input Bias Current (ma) Over-Voltage Protection One Input INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE Both Inputs Normal Operation I b + I b Common-Mode Voltage (V) Both Inputs One Input Over-Voltage Protection Peak-to-Peak Amplitude (V) MAXIMUM OUTPUT SWING vs FREQUEY G =, G = G = k k k M Frequency (Hz) 5 INA4

7 TYPICAL PERFORMAE CURVES (CONT) At T A = +25 C, V S = ±5V, unless otherwise noted.. SLEW RATE vs TEMPERATURE 3 OUTPUT CURRENT LIMIT vs TEMPERATURE Slew Rate (V/µs) Short Circuit Current (ma) I CL I CL Temperature ( C) Temperature ( C) 2.8 QUIESCENT CURRENT vs TEMPERATURE 2.6 QUIESCENT CURRENT AND POWER DISSIPATION vs POWER SUPPLY VOLTAGE 2 Quiescent Current (ma) Quiescent Current (ma) Power Dissipation Quiescent Current Power Dissipation (mw) Temperature ( C) ±3 ±6 ±9 ±2 ±5 ±8 Power Supply Voltage (V) 6 4 POSITIVE SIGNAL SWING vs TEMPERATUE (R L = 2k!) V S = ±5V 6 4 NEGATIVE SIGNAL SWING vs TEMPERATUE (R L = 2k!) V S = ±5V Output Voltage (V) V S = ±.4V V S = ±2.25V Output Voltage (V) V S = ±.4V V S = ±2.25V Temperature ( C) Temperature ( C) INA4 6

8 TYPICAL PERFORMAE CURVES (CONT) At T A = +25 C, V S = ±5V, unless otherwise noted. LARGE SIGNAL RESPONSE, G = SMALL SIGNAL RESPONSE, G = +V +mv V 2mV LARGE SIGNAL RESPONSE, G = SMALL SIGNAL RESPONSE, G = +V +2mV V 2mV INPUT-REFERRED NOISE,. to Hz.µV/div s/div 7 INA4

9 APPLICATION INFORMATION Figure shows the basic connections required for operation of the INA4. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 5! in series with the Ref pin will cause a typical device to degrade to approximately 8dB CMR (G = ). SETTING THE GAIN Gain of the INA4 is set by connecting a single external resistor, R G : G = + 5 k! R G () Commonly used gains and resistor values are shown in Figure. The 5k! term in equation () comes from the sum of the two internal feedback resistors. These are on-chip metal film resistors which are laser trimmed to accurate absolute val- ues. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA4. The stability and temperature drift of the external gain setting resistor, R G, also affects gain. R G s contribution to gain accuracy and drift can be directly inferred from the gain equation (). Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance which will contribute additional gain error (possibly an unstable gain error) in gains of approximately or greater. NOISE PERFORMAE The INA4 provides very low noise in most applications. For differential source impedances less than k!, the INA3 may provide lower noise. For source impedances greater than 5k!, the INA FET-input instrumentation amplifier may provide lower noise. Low frequency noise of the INA4 is approximately.4µvp-p measured from. to Hz. This is approximately one-tenth the noise of low noise chopper-stabilized amplifiers. V+.µF Pin numbers are for DIP packages. 7 V IN R G 2 Over-Voltage Protection A 25k! 25k! INA4 25k! 6 A 3 + V O = G (V IN V IN ) G = + 5k! R G 8 25k! Load + V O + V IN 3 Over-Voltage Protection A 2 25k! 25k! 5 4.µF DESIRED R G NEAREST % R G GAIN (!) (!) No Connection No Connection 2 5.k 49.9k 5 2.5k 2.4k 5.556k 5.62k k 2.6k 5.2k.2k V Also drawn in simplified form: V IN R G INA4 V O V + Ref IN FIGURE. Basic Connections. INA4 8

10 OFFSET TRIMMING The INA4 is laser trimmed for very low offset voltage and drift. Most applications require no external offset adjustment. Figure 2 shows an optional circuit for trimming the output offset voltage. The voltage applied to Ref terminal is summed at the output. Low impedance must be maintained at this node to assure good common-mode rejection. This is achieved by buffering trim voltage with an op amp as shown. Microphone, Hydrophone etc. 47k! 47k! INA4 V IN R G + V IN INA4 Ref V O V+ µa /2 REF2 Thermocouple k! INA4 OPA77 ±mv Adjustment Range k!!! INA4 FIGURE 2. Optional Trimming of Output Offset Voltage. INPUT BIAS CURRENT RETURN PATH The input impedance of the INA4 is extremely high approximately!. However, a path must be provided for the input bias current of both inputs. This input bias current is typically less than ±na (it can be either polarity due to cancellation circuitry). High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current if the INA4 is to operate properly. Figure 3 shows various provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the common-mode range of the INA4 and the input amplifiers will saturate. If the differential source resistance is low, bias current return path can be connected to one input (see thermocouple example in Figure 3). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better common-mode rejection. INPUT COMMON-MODE RANGE µa /2 REF2 The linear common-mode range of the input op amps of the INA4 is approximately ±3.75V (or.25v from the power supplies). As the output voltage increases, however, the linear input range will be limited by the output voltage swing of the input amplifiers, A and A 2. The commonmode range is related to the output voltage of the complete amplifier see performance curve Input Common-Mode Range vs Output Voltage. V FIGURE 3. Providing an Input Common-Mode Current Path. A combination of common-mode and differential input signals can cause the output of A or A 2 to saturate. Figure 4 shows the output voltage swing of A and A 2 expressed in terms of a common-mode and differential input voltages. Output swing capability of these internal amplifiers is the same as the output amplifier, A 3. For applications where input common-mode range must be maximized, limit the output voltage swing by connecting the INA4 in a lower gain (see performance curve Input Common-Mode Voltage Range vs Output Voltage ). If necessary, add gain after the INA4 to increase the voltage swing. Input-overload often produces an output voltage that appears normal. For example, an input voltage of +2V on one input and +4V on the other input will obviously exceed the linear common-mode range of both input amplifiers. Since both input amplifiers are saturated to nearly the same output voltage limit, the difference voltage measured by the output amplifier will be near zero. The output of the INA4 will be near V even though both inputs are overloaded. INPUT PROTECTION Center-tap provides bias current return. The inputs of the INA4 are individually protected for voltages up to ±4V. For example, a condition of 4V on one input and +4V on the other input will not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. To provide equivalent protection, series input resistors would contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe value (approximately.5ma). The typical performance curve Input Bias Current vs Common-Mode Input Voltage shows this input 9 INA4

11 current limit behavior. The inputs are protected even if no power supply voltage is present. OUTPUT VOLTAGE SENSE (SOL-6 package only) The surface-mount version of the INA4 has a separate output sense feedback connection (pin 2). Pin 2 must be connected to the output terminal (pin ) for proper operation. (This connection is made internally on the DIP version of the INA4.) The output sense connection can be used to sense the output voltage directly at the load for best accuracy. Figure 5 shows how to drive a load through series interconnection resistance. Remotely located feedback paths may cause instability. This can be generally be eliminated with a high frequency feedback path through C. Heavy loads or long lines can be driven by connecting a buffer inside the feedback path (Figure 6). V CM G V D 2 V+ V D2 Over-Voltage Protection A 25k! 25k! INA4 25k! G = + 5k! R G R G A 3 V O = G V D V D2 25k! V CM Over-Voltage Protection A 2 25k! 25k! V CM + G V D 2 V FIGURE 4. Voltage Swing of A and A 2. Surface-mount package version only. Surface-mount package version only. V IN V IN + R G INA4 Output Sense Ref C pf Load V IN V IN + R G INA4 Output Sense Ref 8! OPA633 R L I L : ±ma Equal resistance here preserves good common-mode rejection. FIGURE 5. Remote Load and Ground Sensing. FIGURE 6. Buffered Output for Heavy Loads. V IN V IN + Shield is driven at the common-mode potential.! OPA62 22.k! 22.k! 5! For G = R G = 5! // 2(22.k!) effective R G = 55! INA4 Ref V O FIGURE 7. Shield Driver Circuit. INA4

12 V+ V+ Equal line resistance here creates a small common-mode voltage which is rejected by INA4. REF2 µa RTD R G INA4 V O 2 Ref 3 R Z Resistance in this line causes a small common-mode voltage which is rejected by INA4. V O = V at R RTD = R Z FIGURE 8. RTD Temperature Measurement Circuit. V+ 2.V 6 REF2 R 27k! R4 8.6k! 4 K N448 () Cu Cu R2 5.23k! (2) R7 M! INA4 Ref V O R3! R5 5! R6! Zero Adj SEEBECK ISA COEFFICIENT R 2 R 4 TYPE MATERIAL (µv/ C) (R 3 =!) (R 5 + R 6 =!) E Chromel k! 56.2k! Constantan J Iron k! 64.9k! Constantan K Chromel k! 8.6k! Alumel T Copper k! 84.5k! Constantan NOTES: () 2.mV/ C at 2µA. (2) R 7 provides down-scale burn-out indication. FIGURE 9. Thermocouple Amplifier With Cold Junction Compensation. INA4

13 2.8k! RA LA R G/2 INA4 V O 2.8k! Ref G = RL 39k! 39k! /2 OPA264 k! /2 OPA264 FIGURE. ECG Amplifier With Right-Leg Drive. +V V IN + R G INA4 Ref R V O Bridge G = 5 C.µF M! R G! INA4 Ref V O OPA62 f 3dB = 2"R C =.59Hz FIGURE. Bridge Transducer Amplifier. FIGURE 2. AC-Coupled Instrumentation Amplifier. V IN + R G INA4 Ref R I B I O = V IN R G A Load I O A OPA77 OPA62 OPA28 I B Error ±.5nA pa 75fA FIGURE 3. Differential Voltage-to-Current Converter. INA4 2

14 PACKAGE OPTION ADDENDUM 22-Oct-27 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty INA4AP ACTIVE PDIP P 8 5 Green (RoHS & INA4APG4 ACTIVE PDIP P 8 5 Green (RoHS & INA4AU ACTIVE SOIC DW 6 48 Green (RoHS & INA4AU/K ACTIVE SOIC DW 6 Green (RoHS & INA4AU/KE4 ACTIVE SOIC DW 6 Green (RoHS & INA4AUE4 ACTIVE SOIC DW 6 48 Green (RoHS & INA4AUG4 ACTIVE SOIC DW 6 48 Green (RoHS & INA4BP ACTIVE PDIP P 8 5 Green (RoHS & INA4BPG4 ACTIVE PDIP P 8 5 Green (RoHS & INA4BU ACTIVE SOIC DW 6 48 Green (RoHS & INA4BU/K ACTIVE SOIC DW 6 Green (RoHS & INA4BU/KE4 ACTIVE SOIC DW 6 Green (RoHS & INA4BUE4 ACTIVE SOIC DW 6 48 Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Level-3-26C-68 HR Level-3-26C-68 HR Level-3-26C-68 HR Level-3-26C-68 HR Level-3-26C-68 HR Level-3-26C-68 HR Level-3-26C-68 HR Level-3-26C-68 HR Level-3-26C-68 HR () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on Addendum-Page

15 PACKAGE OPTION ADDENDUM 22-Oct-27 incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

16 PACKAGE MATERIALS INFORMATION 4-Oct-27 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A (mm) B (mm) K (mm) P (mm) W (mm) Pin Quadrant INA4BU/K DW 6 SITE Q Pack Materials-Page

17 PACKAGE MATERIALS INFORMATION 4-Oct-27 Device Package Pins Site Length (mm) Width (mm) Height (mm) INA4BU/K DW 6 SITE Pack Materials-Page 2

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security RFID Telephony Low Power Video & Imaging Wireless Wireless Mailing Address: Texas Instruments, Post Office Box 65533, Dallas, Texas Copyright 27, Texas Instruments Incorporated

19 Low Power Consumption Wide Common-Mode and Differential Voltage Ranges Low Input Bias and Offset Currents Output Short-Circuit Protection Low Total Harmonic Distortion....3% Typ description/ordering information SLOS8J! SEPTEMBER 978! REVISED MARCH 25 Low Noise V n = 8 nv/ Hz Typ at f = khz High Input Impedance... JFET Input Stage Internal Frequency Compensation Latch-Up-Free Operation High Slew Rate... 3 V/µs Typ Common-Mode Input Voltage Range Includes V CC+ The JFET-input operational amplifiers in the TL7x series are similar to the TL8x series, with low input bias and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL7x series ideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single monolithic chip. The C-suffix devices are characterized for operation from C to 7 C. The I-suffix devices are characterized for operation from!4 C to 85 C. The M-suffix devices are characterized for operation over the full military temperature range of!55 C to 25 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 25, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

20 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 description/ordering information (continued) TA C to 7 C VIOmax AT 25 C PDIP (P) ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 5 TL7CP TL7CP Tube of 5 TL72CP TL72CP PDIP (N) Tube of 25 TL74CN TL74CN SOIC (D) Tube of 75 Reel of 25 Tube of 75 Reel of 25 TL7CD TL7CDR TL72CD TL72CDR mv Tube of 5 TL74CD 6 mv 3 mv Reel of 25 TL74CDR TL7C TL72C TL74C SOP (NS) Reel of 2 TL74CNSR TL74 SOP (PS) Reel of 2 TL7CPSR TL7 Reel of 2 TL72CPSR T72 Reel of 2 TL72CPWR T72 TSSOP (PW) Tube of 9 TL74CPW PDIP (P) Reel of 2 TL74CPWR T74 Tube of 5 TL7ACP TL7ACP Tube of 5 TL72ACP TL72ACP PDIP (N) Tube of 25 TL74ACN TL74ACN SOIC (D) Tube of 75 Reel of 25 Tube of 75 Reel of 25 Tube of 5 Reel of 25 TL7ACD TL7ACDR TL72ACD TL72ACDR TL74ACD TL74ACDR 7AC 72AC TL74AC SOP (PS) Reel of 2 TL72ACPSR T72A SOP (NS) Reel of 2 TL74ACNSR TL74A PDIP (P) Tube of 5 TL7BCP TL7BCP Tube of 5 TL72BCP TL72BCP PDIP (N) Tube of 25 TL74BCN TL74BCN SOIC (D) Tube of 75 Reel of 25 Tube of 75 Reel of 25 Tube of 5 Reel of 25 TL7BCD TL7BCDR TL72BCD TL72BCDR TL74BCD TL74BCDR 7BC 72BC TL74BC SOP (NS) Reel of 2 TL74BCNSR TL74B Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 description/ordering information (continued) SLOS8J! SEPTEMBER 978! REVISED MARCH 25 ORDERING INFORMATION TA VIOmax AT 25 C PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (P) Tube of 5 TL7IP TL7IP Tube of 5 TL72IP TL72IP PDIP (N) Tube of 25 TL74IN TL74IN Tube of 75 TL7ID!4 C C to 85 C 6 mv Reel of 25 TL7IDR!55 C to 25 C SOIC (D) Tube of 75 Reel of 25 Tube of 5 Reel of 25 TL72ID TL72IDR TL74ID TL74IDR TL7I TL72I TL74I CDIP (JG) Tube of 5 TL72MJGB TL72MJGB 6 mv CFP (U) Tube of 5 TL72MUB TL72MUB LCCC (FK) Tube of 55 TL72MFKB TL72MFKB CDIP (J) Tube of 25 TL74MJB TL74MJB 9 mv CFP (W) Tube of 25 TL74MWB TL74MWB LCCC (FK) Tube of 55 TL74MFKB TL74MFKB Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at POST OFFICE BOX DALLAS, TEXAS

22 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 OFFSET N IN! IN+ V CC! TL7, TL7A, TL7B D, P, OR PS PACKAGE (TOP VIEW) V CC+ OUT OFFSET N2 TL72, TL72A, TL72B D, JG, P, PS, OR PW PACKAGE (TOP VIEW) OUT IN! IN+ V CC! OUT IN! IN+ V CC! TL72 U PACKAGE (TOP VIEW) V CC+ 2OUT 2IN! 2IN+ V CC+ 2OUT 2IN! 2IN+ TL74A, TL74B D, J, N, NS, OR PW PACKAGE TL74... D, J, N, NS, PW, OR W PACKAGE (TOP VIEW) OUT IN! IN+ V CC+ 2IN+ 2IN! 2OUT OUT 4IN! 4IN+ V CC! 3IN+ 3IN! 3OUT TL7 FK PACKAGE (TOP VIEW) TL72 FK PACKAGE (TOP VIEW) TL74 FK PACKAGE (TOP VIEW) IN! IN OFFSET N V CC! OFFSET N2 V CC+ OUT IN! IN OUT VCC IN+ V CC! 2OUT 2IN! IN+ V CC+ 2IN+ 2IN! IN! 2OUT OUT 3OUT 4OUT 3IN! 4IN! IN+ V CC! 3IN+! No internal connection symbols OFFSET N TL7 TL72 (each amplifier) TL74 (each amplifier) IN+ IN! +! OUT IN+ IN! +! OUT OFFSET N2 4 POST OFFICE BOX DALLAS, TEXAS 75265

23 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 schematic (each amplifier) VCC+ IN+ IN! 64 Ω 28 Ω OUT 64 Ω C 8 pf 8 Ω 8 Ω VCC! OFFSET N OFFSET N2 TL7 Only All component values shown are nominal. COMPONENT TYPE COMPONENT COUNT TL7 TL72 TL74 Resistors Transistors JFET Diodes 2 4 Capacitors 2 4 epi-fet 2 4 Includes bias and trim circuitry POST OFFICE BOX DALLAS, TEXAS

24 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (see Note ): V CC V V CC! !8 V Differential input voltage, V ID (see Note 2) ±3 V Input voltage, V I (see Notes and 3) ±5 V Duration of output short circuit (see Note 4) Unlimited Package thermal impedance, θ JA (see Notes 5 and 6): D package (8 pin) C/W D package (4 pin) C/W N package C/W NS package C/W P package C/W PS package C/W PW package (8 pin) C/W PW package (4 pin) C/W U package C/W Package thermal impedance, θ JC (see Notes 7 and 8): FK package C/W J package C/W JG package C/W W package C/W Operating virtual junction temperature, T J C Case temperature for 6 seconds: FK package C Lead temperature,6 mm (/6 inch) from case for seconds: J, JG, or W package C Storage temperature range, T stg !65 C to 5 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC!. 2. Differential voltages are at IN+, with respect to IN!. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 5 V, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. 5. Maximum power dissipation is a function of TJ(max), θja, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max)! TA)/θJA. Operating at the absolute maximum TJ of 5 C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD Maximum power dissipation is a function of TJ(max), θjc, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max)! TC)/θJC. Operating at the absolute maximum TJ of 5 C can affect reliability. 8. The package thermal impedance is calculated in accordance with MIL-STD POST OFFICE BOX DALLAS, TEXAS 75265

25 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 electrical characteristics, V CC± = ±5 V (unless otherwise noted) TL7C TL7AC TL7BC TL7I PARAMETER TEST CONDITIONS TA TL72C TL72AC TL72BC TL72I TL74C TL74AC TL74BC TL74I UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 25 C VIO Input offset voltage VO =, RS = 5 Ω Full range mv Temperature α VIO coefficient of input offset voltage IIO Input offset current VO = IIB Input bias current VO = VO =, RS = 5 Ω Full range µv/ C 25 C pa Full range na 25 C pa Full range na Common-mode VICR input voltage range!2!2!2!2 25 C ± to ± to ± to ± to V Maximum peak RL = kω 25 C ±2 ±3.5 ±2 ±3.5 ±2 ±3.5 ±2 ±3.5 VOM output voltage RL kω ±2 ±2 ±2 ±2 V swing Full range RL 2 kω ± ± ± ± V Large-signal AVD differential voltage VO = ± V, RL 2 kω amplification 25 C Full range V/mV B Unity-gain bandwidth 25 C MHz ri Input resistance 25 C Ω CMRR Common-mode VIC = VICRmin, rejection ratio VO =, RS = 5 Ω Supply-voltage VCC = ±9 V to ±5 V, ksvr rejection ratio VO =, RS = 5 Ω ( VCC ±/ VIO) Supply current ICC (each amplifier) 25 C db 25 C db VO =, No load 25 C ma VO/VO2 Crosstalk attenuation AVD = 25 C db All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = C to 7 C for TL7_C,TL7_AC, TL7_BC and is TA =!4 C to 85 C for TL7_I. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. POST OFFICE BOX DALLAS, TEXAS

26 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 electrical characteristics, V CC± = ±5 V (unless otherwise noted) TL7M TL74M PARAMETER TEST CONDITIONS TL72M TA MIN TYP MAX MIN TYP MAX UNIT 25 C VIO Input offset voltage V VO =, RS = 5 Ω mv Full range 9 5 αv IO Temperature coefficient of input offset voltage IIO Input offset current VO = IIB Input bias current VO = VICR VOM AVD Common-mode input voltage range Maximum peak output voltage swing Large-signal differential voltage amplification VO =, RS = 5 Ω Full range 8 8 µv/ C 25 C 5 5 pa Full range 2 2 na 25 C pa 25 C ±!2 to na RL = kω 25 C ±2 ±3.5 ±2 ±3.5 RL kω RL 2 kω VO = ± V, V, RL 2 kω Full range ±!2 to 5 ±2 ±2 V ± ± 25 C B Unity-gain bandwidth TA = 25 C 3 3 MHz ri Input resistance TA = 25 C 2 2 Ω CMRR ksvr ICC Common-mode rejection VIC = VICRmin, ratio VO =, RS = 5 Ω Supply-voltage rejection VCC = ±9 V to ±5 V, ratio ( VCC±/ VIO) VO =, RS = 5 Ω Supply current (each amplifier) V V/mV 25 C db 25 C db VO =, No load 25 C ma VO/VO2 Crosstalk attenuation AVD = 25 C 2 2 db Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible. All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA =!55 C to 25 C. 8 POST OFFICE BOX DALLAS, TEXAS 75265

27 operating characteristics, V CC± = ±5 V, T A = 25 C SLOS8J! SEPTEMBER 978! REVISED MARCH 25 SR tr Vn In THD PARAMETER Slew rate at unity gain VI = V, CL = pf, TEST CONDITIONS RL = 2 kω, See Figure TL7xM ALL OTHERS MIN TYP MAX MIN TYP MAX UNIT V/µs Rise-time overshoot VI = 2 mv, RL = 2 kω,.. µs factor CL = pf, See Figure 2% 2% Equivalent input noise voltage Equivalent input noise current Total harmonic distortion RS = 2 Ω f = khz 8 8 nv/ Hz f = Hz to khz 4 4 µv RS = 2 Ω, f = khz.. pa/ Hz VIrms = 6 V, RL 2 kω, f = khz AVD =, RS kω,.3 %.3% PARAMETER MEASUREMENT INFORMATION! kω VI + CL = pf VO RL = 2 kω VI kω! + RL VO CL = pf Figure. Unity-Gain Amplifier Figure 2. Gain-of- Inverting Amplifier IN! IN+! + TL7 N kω N2 OUT.5 kω VCC! Figure 3. Input Offset-Voltage Null Circuit POST OFFICE BOX DALLAS, TEXAS

28 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 TYPICAL CHARACTERISTICS Table of Graphs FIGURE IIB Input bias current vs Free-air temperature 4 VOM AVD Maximum output voltage Large-signal differential voltage amplification vs Frequency 5, 6, 7 vs Free-air temperature 8 vs Load resistance 9 vs Supply voltage vs Free-air temperature vs Frequency 2 Phase shift vs Frequency 2 Normalized unity-gain bandwidth vs Free-air temperature 3 Normalized phase shift vs Free-air temperature 3 CMRR Common-mode rejection ratio vs Free-air temperature 4 ICC Supply current vs Supply voltage 5 vs Free-air temperature 6 PD Total power dissipation vs Free-air temperature 7 Normalized slew rate vs Free-air temperature 8 Vn Equivalent input noise voltage vs Frequency 9 THD Total harmonic distortion vs Frequency 2 Large-signal pulse response vs Time 2 VO Output voltage vs Elapsed time 22 POST OFFICE BOX DALLAS, TEXAS 75265

29 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 TYPICAL CHARACTERISTICS IIB! Input Bias Current! na. VCC± = ±5 V INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE VOM V OM! Maximum Peak Output Voltage! V ±5 ±2.5 ± ±7.5 ±5 ±2.5 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUEY VCC± = ±5 V VCC± = ± V VCC± = ±5 V RL = kω TA = 25 C See Figure 2.!75!5! TA! Free-Air Temperature! C Figure 4 k k k M M f! Frequency! Hz Figure 5 VOM V! Maximum Peak Output Voltage! V ±5 ±2.5 ± ±7.5 ±5 ±2.5 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUEY VCC± = ±5 V VCC± = ± V VCC± = ±5 V RL = 2 kω TA = 25 C See Figure 2 VOM V! Maximum Peak Output Voltage! V ±5 ±2.5 ± ±7.5 ±5 ±2.5 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUEY TA = 25 C TA = 25 C TA =!55 C VCC± = ±5 V RL = 2 kω See Figure 2 k k k f! Frequency! Hz M M k 4 k k 4 k M 4 M M f! Frequency! Hz Figure 6 Figure 7 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS 75265

30 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 TYPICAL CHARACTERISTICS VOM V! Maximum Peak Output Voltage! V ±5 ±2.5 ± ±7.5 ±5 ±2.5!75 MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE VCC± = ±5 V See Figure 2 RL = kω RL = 2 kω!5! VOM V! Maximum Peak Output Voltage! V ±5 ±2.5 ± ±7.5 ±5 ±2.5. MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTAE VCC± = ±5 V TA = 25 C See Figure TA! Free-Air Temperature! C RL! Load Resistance! kω Figure 8 Figure 9 MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE VOM V OM! Maximum Peak Output Voltage! V ±5 ±2.5 ± ±7.5 ±5 ±2.5 RL = kω TA = 25 C A AVD! Large-Signal Differential Voltage Amplification! V/mV VCC± = ±5 V VO = ± V RL = 2 kω !75!5! VCC±! Supply Voltage! V TA! Free-Air Temperature! C Figure Figure Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 2 POST OFFICE BOX DALLAS, TEXAS 75265

31 A AVD! Large-Signal Differential Voltage Amplification SLOS8J! SEPTEMBER 978! REVISED MARCH 25 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUEY Phase Shift VCC± = ±5 V to ±5 V RL = 2 kω TA = 25 C Differential Voltage Amplification Phase Shift k k k M f! Frequency! Hz Figure 2 8 M.3 NORMALIZED UNITY-GAIN BANDWIDTH AND PHASE SHIFT vs FREE-AIR TEMPERATURE.3 Normalized Unity-Gain Bandwidth.2 Unity-Gain Bandwidth !75 Phase Shift VCC± = ±5 V RL = 2 kω f = B for Phase Shift!5! TA! Free-Air Temperature! C Figure Normalized Phase Shift Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

32 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE CMRR! Common-Mode Rejection Ratio! db VCC± = ±5 V RL = kω ICC! Supply Current Per Amplifier! ma ICC± TA = 25 C No Signal No Load 83!75!5! TA! Free-Air Temperature! C VCC±! Supply Voltage! V Figure 4 Figure 5 ICC! Supply Current Per Amplifier! ma ICC± SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE VCC± = ±5 V No Signal No Load PD P D! Total Power Dissipation! mw TOTAL POWER DISSIPATION vs FREE-AIR TEMPERATURE TL7 TL72 VCC± = ±5 V No Signal No Load TL74!75!5! TA! Free-Air Temperature! C 25!75!5! TA! Free-Air Temperature! C 25 Figure 6 Figure 7 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 4 POST OFFICE BOX DALLAS, TEXAS 75265

33 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 TYPICAL CHARACTERISTICS Normalized Slew Rate! V/µs VCC± = ±5 V RL = 2 kω CL = pf NORMALIZED SLEW RATE vs FREE-AIR TEMPERATURE V Vn n! Equivalent Input Noise Voltage! nv/hz Hz EQUIVALENT INPUT NOISE VOLTAGE vs FREQUEY VCC± = ±5 V AVD = RS = 2 Ω TA = 25 C.85!75!5! TA! Free-Air Temperature! C k 4 k k 4 k k f! Frequency! Hz Figure 8 Figure 9 THD! Total Harmonic Distortion! % TOTAL HARMONIC DISTORTION vs FREQUEY VCC± = ±5 V AVD = VI(RMS) = 6 V TA = 25 C V I and V O! Input and Output Voltages! V 6 4 2!2!4 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE Output Input VCC± = ±5 V RL = 2 kω CL = pf TA = 25 C. 4 k 4 k k 4 k k f! Frequency! Hz! t! Time! µs 3.5 Figure 2 Figure 2 POST OFFICE BOX DALLAS, TEXAS

34 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 TYPICAL CHARACTERISTICS 28 OUTPUT VOLTAGE vs ELAPSED TIME V VO O! Output Voltage! mv !4 Overshoot % 9% tr VCC± = ±5 V RL = 2 kω TA = 25 C t! Elapsed Time! µs Figure POST OFFICE BOX DALLAS, TEXAS 75265

35 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 APPLICATION INFORMATION Table of Application Diagrams APPLICATION DIAGRAM PART NUMBER FIGURE.5-Hz square-wave oscillator TL7 23 High-Q notch filter TL7 24 Audio-distribution amplifier TL khz quadrature oscillator TL72 26 AC amplifier TL7 27 RF = kω VCC+ 3.3 kω CF = 3.3 µf f 2 R C F F! + 5 V TL7!5 V 3.3 kω kω 9. kω Output Input R C3 C R2 R3 C2! TL7 + VCC! Output R R2 2R3.5 M C C2 C3 pf 2 f O khz 2 R C Figure Hz Square-Wave Oscillator Figure 24. High-Q Notch Filter VCC+ MΩ VCC+ +! TL74 Output A! VCC! Input µf + TL74! VCC+ kω VCC! kω + TL74 Output B µf kω kω VCC+! VCC! VCC+ TL74 Output C + VCC! Figure 25. Audio-Distribution Amplifier POST OFFICE BOX DALLAS, TEXAS

36 SLOS8J! SEPTEMBER 978! REVISED MARCH 25 APPLICATION INFORMATION 8 pf 6 sin ωt N448 8 kω (see Note A)!5 V VCC+ 8 pf kω 88.4 kω! + TL kω! VCC+ TL72 6 cos ωt 8 pf VCC! + VCC! N448 kω 8 kω (see Note A) 5 V 88.4 kω NOTE A: These resistor values may be adjusted for a symmetrical output. Figure 26. -khz Quadrature Oscillator VCC+. µf kω IN! kω! MΩ 5 Ω TL7 OUT IN+ + N2. µf kω N kω Figure 27. AC Amplifier 8 POST OFFICE BOX DALLAS, TEXAS 75265

37 PACKAGE OPTION ADDENDUM 6-Dec-26 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) 8234HA OBSOLETE TBD Call TI Call TI 82352A ACTIVE LCCC FK 2 TBD POST-PLATE 8235HA ACTIVE CFP U TBD A42 SNPB 8235PA ACTIVE CDIP JG 8 TBD A42 SNPB 82362A ACTIVE LCCC FK 2 TBD POST-PLATE 8236CA ACTIVE CDIP J 4 TBD A42 SNPB 8236DA ACTIVE CFP W 4 TBD A42 SNPB JM385/95BPA ACTIVE CDIP JG 8 TBD A42 SNPB JM385/96BCA OBSOLETE CDIP J 4 TBD Call TI Call TI TL7ACD ACTIVE SOIC D 8 75 Green (RoHS & TL7ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL7ACDR ACTIVE SOIC D 8 25 Green (RoHS & TL7ACDRE4 ACTIVE SOIC D 8 25 Green (RoHS & TL7ACP ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7ACPE4 ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7BCD ACTIVE SOIC D 8 75 Green (RoHS & TL7BCDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL7BCDR ACTIVE SOIC D 8 25 Green (RoHS & TL7BCDRE4 ACTIVE SOIC D 8 25 Green (RoHS & TL7BCP ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7BCPE4 ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7CD ACTIVE SOIC D 8 75 Green (RoHS & TL7CDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL7CDR ACTIVE SOIC D 8 25 Green (RoHS & TL7CDRE4 ACTIVE SOIC D 8 25 Green (RoHS & TL7CP ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7CPE4 ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7CPSR ACTIVE SO PS 8 2 Green (RoHS & TL7CPSRE4 ACTIVE SO PS 8 2 Green (RoHS & Addendum-Page

38 PACKAGE OPTION ADDENDUM 6-Dec-26 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TL7CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TL7ID ACTIVE SOIC D 8 75 Green (RoHS & TL7IDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL7IDR ACTIVE SOIC D 8 25 Green (RoHS & TL7IDRE4 ACTIVE SOIC D 8 25 Green (RoHS & TL7IJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL7IP ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7IPE4 ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL7MFKB OBSOLETE LCCC FK 2 TBD Call TI Call TI TL7MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL7MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI TL72ACD ACTIVE SOIC D 8 75 Green (RoHS & TL72ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL72ACDR ACTIVE SOIC D 8 25 Green (RoHS & TL72ACDRE4 ACTIVE SOIC D 8 25 Green (RoHS & TL72ACJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL72ACP ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL72ACPE4 ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL72ACPSR ACTIVE SO PS 8 2 Green (RoHS & TL72ACPSRE4 ACTIVE SO PS 8 2 Green (RoHS & TL72BCD ACTIVE SOIC D 8 75 Green (RoHS & TL72BCDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL72BCDR ACTIVE SOIC D 8 25 Green (RoHS & TL72BCDRE4 ACTIVE SOIC D 8 25 Green (RoHS & TL72BCP ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL72BCPE4 ACTIVE PDIP P 8 5 Pb-Free (RoHS) TL72CD ACTIVE SOIC D 8 75 Green (RoHS & TL72CDE4 ACTIVE SOIC D 8 75 Green (RoHS & Addendum-Page 2