SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS
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1 SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SDAS022C DECEMBER 1982 REVISED JANUARY 1995 High Capacitive-Drive Capability ALS804A Has Typical Delay Time of 4 ns (C L = 50 pf) and Typical Power Dissipation of 3.4 mw Per Gate AS804B Has Typical Delay Time of 2.6 ns (C L = 50 pf) and Typical Power Dissipation of Less Than 9 mw Per Gate Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These devices contain six independent 2-input NAND drivers. They perform the Boolean functions Y = A B or Y = A + B in positive logic. The SN54ALS804A and SN54AS804B are characterized for operation over the full military temperature range of 55 C to 125 C. The SN74ALS804A and SN74AS804B are characterized for operation from 0 C to 70 C. logic symbol FUNCTION TABLE (each driver) INPUTS OUTPUT A B Y H H L L X H X L H SN54ALS804A, SN54AS804B...J PACKAGE SN74ALS804A, SN74AS804B... DW OR N PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y 3A 3B 3Y GND logic diagram (positive logic) V CC 6B 6A 6Y 5B 5A 5Y 4B 4A 4Y SN54ALS804A, SN54AS804B... FK PACKAGE (TOP VIEW) 2A 2B 2Y 3A 3B 1Y 1B 1A Y GND 4Y 4A V CC 4B 6B 6A 6Y 5B 5A 5Y 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B & Y 2Y 3Y 4Y 5Y 6Y 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B Y 2Y 3Y 4Y 5Y 6Y This symbol is in accordance with ANSI/IEEE Std and IEC Publication PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1995, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS
2 SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SDAS022C DECEMBER 1982 REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Operating free-air temperature range, T A : SN54ALS804A C to 125 C SN74ALS804A C to 70 C Storage temperature range C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS804A SN74ALS804A UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current ma TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS804A SN74ALS804A MIN TYP MAX MIN TYP MAX VIK VCC = 4.5 V, II = 18 ma V VOH VOL VCC =45V 4.5 VCC = 4.5 V to 5.5 V, IOH = 0.4 ma VCC 2 VCC 2 IOH = 3 ma VCC = 4.5 V IOH = 12 ma 2 IOH = 15 ma 2 IOL = 12 ma IOL = 24 ma II VCC = 5.5 V, VI = 7 V ma IIH VCC = 5.5 V, VI = 2.7 V µa IIL VCC = 5.5 V, VI = 0.4 V ma IO VCC = 5.5 V, VO = 2.25 V ma ICCH VCC = 5.5 V, VI = ma ICCL VCC = 5.5 V, VI = 4.5 V ma All typical values are at VCC = 5 V, TA = 25 C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. UNIT V V 2 POST OFFICE BOX DALLAS, TEXAS 75265
3 SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS switching characteristics (see Figure 1) SDAS022C DECEMBER 1982 REVISED JANUARY 1995 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pf, RL = 500 Ω, TA = MIN to MAX SN54ALS804A SN74ALS804A MIN MAX MIN MAX tplh AorB Y tphl For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Operating free-air temperature range, T A : SN54AS804B C to 125 C SN74AS804B C to 70 C Storage temperature range C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS804B SN74AS804B MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current ma TA Operating free-air temperature C These high sink- or source-current devices are not recommended for use above 40 MHz. POST OFFICE BOX DALLAS, TEXAS
4 SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SDAS022C DECEMBER 1982 REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS804B SN74AS804B MIN TYP MAX MIN TYP MAX VIK VCC = 4.5 V, II = 18 ma V VOH VOL VCC =45V 4.5 VCC = 4.5 V to 5.5 V, IOH = 2 ma VCC 2 VCC 2 IOH = 3 ma VCC = 4.5 V IOH = 40 ma 2 IOH = 48 ma 2 IOL = 40 ma IOL = 48 ma II VCC = 5.5 V, VI = 7 V ma IIH VCC = 5.5 V, VI = 2.7 V µa IIL VCC = 5.5 V, VI = 0.4 V ma IO VCC = 5.5 V, VO = 2.25 V ma ICCH VCC = 5.5 V, VI = ma ICCL VCC = 5.5 V, VI = 4.5 V ma All typical values are at VCC = 5 V, TA = 25 C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) UNIT V V PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pf, RL = 500 Ω, TA = MIN to MAX SN54AS804B SN74AS804B MIN MAX MIN MAX tplh AorB Y tphl For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns 4 POST OFFICE BOX DALLAS, TEXAS 75265
5 SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SDAS022C DECEMBER 1982 REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES VCC 7 V RL = R1 = R2 S1 RL From Output Under Test CL (see Note A) RL Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R1 R2 Test Point LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS Timing Input 3.5 V High-Level Pulse 3.5 V Data Input tsu th 3.5 V Low-Level Pulse tw 3.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) Waveform 1 S1 Closed (see Note B) tpzl tphz tplz 3.5 V 3.5 V VOL tpzh Waveform 2 VOH S1 Open (see Note B) 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS Input In-Phase Output Out-of-Phase Output (see Note C) tplh tphl tphl 3.5 V VOH VOL tplh VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS
6 PACKAGE OPTION ADDENDUM 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type RA ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type RA ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SN54ALS804AJ ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SN54AS804BJ ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SN74ALS804ADW ACTIVE SOIC DW Green (RoHS & SN74ALS804ADWE4 ACTIVE SOIC DW Green (RoHS & SN74ALS804ADWG4 ACTIVE SOIC DW Green (RoHS & SN74ALS804ADWR ACTIVE SOIC DW Green (RoHS & SN74ALS804ADWRE4 ACTIVE SOIC DW Green (RoHS & SN74ALS804ADWRG4 ACTIVE SOIC DW Green (RoHS & SN74ALS804AN ACTIVE PDIP N Pb-Free (RoHS) SN74ALS804ANE4 ACTIVE PDIP N Pb-Free (RoHS) SN74AS804BDW ACTIVE SOIC DW Green (RoHS & SN74AS804BDWE4 ACTIVE SOIC DW Green (RoHS & SN74AS804BDWG4 ACTIVE SOIC DW Green (RoHS & SN74AS804BDWR ACTIVE SOIC DW Green (RoHS & SN74AS804BDWRE4 ACTIVE SOIC DW Green (RoHS & SN74AS804BDWRG4 ACTIVE SOIC DW Green (RoHS & SN74AS804BN ACTIVE PDIP N Pb-Free (RoHS) SN74AS804BNE4 ACTIVE PDIP N Pb-Free (RoHS) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type SNJ54ALS804AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54ALS804AJ ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SNJ54AS804BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54AS804BJ ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SNJ54AS804BW ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1
7 PACKAGE OPTION ADDENDUM 9-Oct-2007 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
8 PACKAGE MATERIALS INFORMATION 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74ALS804ADWR DW 20 SITE Q1 SN74AS804BDWR DW 20 SITE Q1 Pack Materials-Page 1
9 PACKAGE MATERIALS INFORMATION 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74ALS804ADWR DW 20 SITE SN74AS804BDWR DW 20 SITE Pack Materials-Page 2
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12 MECHANICAL DATA MLCC006B OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) (9,09) (7,80) (9,09) A SQ B SQ (11,23) (16,26) (18,78) (23,83) (28,99) (11,63) (16,76) (19,32) (24,43) (29,59) (10,31) (12,58) (12,58) (21,6) (26,6) (11,63) (14,22) (14,22) (21,8) (27,0) (0,51) (0,25) (2,03) (1,63) (0,51) (0,25) (1,40) (1,14) (1,14) (0,89) (0,71) (0,54) (1,27) (1,14) (0,89) / D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX DALLAS, TEXAS 75265
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15 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. 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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Dependable Texas Instruments Quality and Reliability description/ordering information These devices contain six independent inverters. SN5404... J PACKAGE SN54LS04, SN54S04... J OR W PACKAGE SN7404, SN74S04...
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input exclusive-or
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-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
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Functionally Equivalent to AMD s AM29821 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State
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SCLS107E DECEMBER 1982 REVISED SEPTEMBER 2003 Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL
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Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
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