Efficient real-time blind calibration for frequency response mismatches in twochannel

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1 LETTER IEICE Electronics Express, Vol.15, No.12, 1 12 Efficient real-time blind calibration for frequency response mismatches in twochannel TI-ADCs Guiqing Liu, Yinan Wang a), Xiangyu Liu, Husheng Liu, and Nan Li b) College of Electronic Science, National University of Defense Technology, Changsha , People s Republic of China a) wangyinan@nudt.edu.cn b) linan@nudt.edu.cn Abstract: This paper proposes an efficient full-parallel real-time blind calibration algorithm for frequency response mismatches in two-channel time-interleaved analog-to-digital converters (TI-ADCs). To make the algorithm compatible for high-speed and real-time scenarios, the algorithm is designed with full-parallel structure, where all the filters adopted in the algorithm are realized by using fast FIR algorithm (FFA). In order to reduce the computational complexity, we present a downsampling signed-fxlms method to estimate the mismatch parameters, which can substantially save the resource consumption. Furthermore, the proposed calibration algorithm can provide low latency due to the utilization of FFA. Finally, we demonstrate the performance and efficiency of the proposed algorithm through simulations. Keywords: TI-ADCs, real-time, full-parallel calibration, frequency response mismatches, resource-saving Classification: Circuits and modules for electronic instrumentation References [1] W. C. Black and D. A. Hodges: Time interleaved converter arrays, IEEE J. Solid-State Circuits 15 (1980) 1022 (DOI: /JSSC ). [2] C. Vogel: The impact of combined channel mismatch effects in timeinterleaved ADCs, IEEE Trans. Instrum. Meas. 54 (2005) 415 (DOI: / TIM ). [3] X. Liu, et al.: An efficient blind calibration method for nonlinearity mismatches in M-channel TIADCs, IEICE Electron. Express 14 (2017) (DOI: /elex ). [4] M. Seo, et al.: Blind correction of gain and timing mismatches for a twochannel time-interleaved analog-to-digital converter, ACSSC (2005) 3394 (DOI: /ACSSC ). [5] S. Huang and B. C. Levy: Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs, IEEE Trans. Circuits Syst. I, Reg. Papers 53 (2006) 1278 (DOI: /TCSI ). [6] H. Liu and H. Xu: A calibration method for frequency response mismatches in 1

2 M-channel time-interleaved analog-to-digital converters, IEICE Electron. Express 13 (2016) (DOI: /elex ). [7] C. Vogel and H. Johansson: Time-interleaved analog-to-digital converters: Status and future directions, ISCAS (2006) 3385 (DOI: /ISCAS ). [8] C. Vogel and S. Mendel: A flexible and scalable structure to compensate frequency response mismatches in time-interleaved ADCs, IEEE Trans. Circuits Syst. I, Reg. Papers 56 (2009) 2463 (DOI: /TCSI ). [9] S. Saleem and C. Vogel: Adaptive blind background calibration of polynomial-represented frequency response mismatches in a two-channel time-interleaved ADC, IEEE Trans. Circuits Syst. I, Reg. Papers 58 (2011) 1300 (DOI: /TCSI ). [10] H. Johansson: A polynomial-based time-varying filter structure for the compensation of frequency-response mismatch errors in time-interleaved ADCs, IEEE J. Sel. Topics Signal Process. 3 (2009) 384 (DOI: / JSTSP ). [11] S. Liu, et al.: Adaptive blind timing mismatch calibration with low power consumption in M-channel time-interleaved ADC, Circuits Syst. Signal Process. 1 (2018) 1 (DOI: /s ). [12] D. A. Parker and K. K. Parhi: Area-efficient parallel FIR digital filter implementations, ASAP (1996) 93 (DOI: /ASAP ). [13] H. Johansson, et al.: Least-squares and minimax design of polynomial impulse response FIR filters for reconstruction of two-periodic nonuniformly sampled signals, IEEE Trans. Circuits Syst. I, Reg. Papers 54 (2007) 877 (DOI: /TCSI ). [14] U. Meyer-Baese: Digital Signal Processing with Field Programmable Gate Arrays (Springer, Florida, 2007) 3rd ed [15] Y. Wang, et al.: Joint blind calibration for mixed mismatches in two-channel time-interleaved ADCs, IEEE Trans. Circuits Syst. I, Reg. Papers 62 (2015) 1508 (DOI: /TCSI ). [16] H. Johansson and O. Gustafsson: Linear-phase FIR interpolation, decimation and mth-band filters utilizing the farrow structure, IEEE Trans. Circuits Syst. I, Reg. Papers 52 (2005) 2197 (DOI: /TCSI ). [17] H. Johansson and L. Wanhammar: Two-stage polyphase interpolators and decimators for sample rate conversions with prime numbers, EUSIPCO (1996) 1. [18] B. Parhami: Computer Arithmetic: Algorithms and Hardware Designs (Oxford University Press, New York, 1999) 1st ed [19] H. Johansson and Z. U. Sheikh: A class of wide-band linear-phase FIR differentiators using a two-rate approach and the frequency-response masking technique, IEEE Trans. Circuits Syst. I, Reg. Papers 58 (2011) 1827 (DOI: /TCSI ). 1 Introduction Since Black and Hodges firstly proposed the concept of time-interleaved analog-todigital converters (TI-ADCs) in 1980 [1], this high-speed sampling architecture has become a focus in the field of modern mixed signal processing. As shown in Fig. 1, the two sub-adcs have the same sampling rate but different sampling phases, consequently, they cooperate as one single converter with a sampling rate of two 2

3 Fig. 1. Two-channel TI-ADCs model. times higher than each sub-adc. Due to the differences between the two channels, various mismatch errors are introduced, such as gain, offset, timing, bandwidth mismatches and nonlinearity mismatches [2, 3]. These mismatch errors introduce modulated spectral components and degrade the dynamic performance of the overall sampling system, which greatly limit the applicability of TI-ADCs. With the gain, offset and timing mismatch studied thoroughly [4, 5], much work has been focused on the calibration of frequency response mismatches [6, 7, 8, 9, 10]. In [8], a flexible and scalable frequency response mismatches compensation structure has been proposed. According to the compensation structure in [8], the author proposed an adaptive calibration algorithm for frequency response mismatches in two channel TI-ADCs [9]. The algorithm can effectively calibrate the frequency response mismatches, it is however not designed for real-time application scenarios. Due to the structural limitation of the algorithm, the clock frequency of the digital background calibration algorithm must be the same as the overall sampling frequency of TI-ADCs. Therefore, the digital signal processing devices, that are adopted to implement the calibration algorithms, become the bottleneck to achieve real-time calibration for the high-speed TI-ADCs. Aiming at the real-time application scenarios, this paper proposes an efficient full-parallel and real-time blind calibration algorithm for frequency response mismatches in two-channel TI-ADCs. Firstly, we realize the calibration algorithm by utilizing the full-parallel structure, where all the filters adopted in the algorithm are designed and implemented with the fast FIR algorithm (FFA). This can effectively mitigate the requirements of clock performance and make the proposed calibration algorithm compatible for high-speed and real-time scenarios. In order to further reduce the computational complexity, a downsampling signed-fxlms method is presented to estimate the channel mismatch parameters. With the estimated mismatch coefficients, we compensate the frequency response mismatches by using digital differentiators. Finally, we demonstrate the performance of the proposed algorithm by simulations. Compared with the calibration method in [9], the proposed algorithm can save nearly 40% resource consumption and a half latency by achieving the comparative performance as in [9]. It is mentioned that we during the preparation of this paper aware of a related work described in [11]. In [11], M-channel timing mismatches are calibrated by adaptive calibration algorithm. However, this paper calibrates the frequency response mismatch. Compared to timing mismatch, the calibration of the frequency response mismatch is more general for high-speed wide-band applications and 3

4 more complex to implement. In addition, this paper ultilizes the FFA to effectively mitigate the requirements of clock performance and make the proposed calibration algorithm compatible for high-speed and real-time scenarios. The outline of this paper is as follows. In section 2, we introduce the mismatch model and the calibration strategy. In section 3, we present the full-parallel and real-time blind calibration algorithm. Section 4 discusses the performance of the algorithm with simulations. Section 5 analyzes and compares the resource consumption. Section 6 concludes the paper. 2 Mismatches model and calibration strategy 2.1 Frequency response mismatches model As depicted in Fig. 1, the discrete-time frequency response of the two-channels TI- ADCs is H 0 ðe j! Þ and H 1 ðe j! Þ, respectively. The ideal output of a two channel TI- ADCs is denoted as xðnþ. The discrete-time Fourier transform (DTFT) of xðnþ is Xðe j! Þ. Thus, the DTFT of the TI-ADC s output yðnþ can be given as [8, 9] where Yðe j! Þ¼ H 0 ðe j! ÞXðe j! Þþ H 1 ðe jð! Þ ÞXðe jð! Þ Þ H 0 ðe j! Þ¼ 1 2 ðh 0ðe j! ÞþH 1 ðe j! ÞÞ H 1 ðe j! Þ¼ 1 2 ðh 0ðe j! Þ H 1 ðe j! ÞÞ ð1þ ð2þ If the two channels have no mismatch, i.e., H 0 ðe j! Þ¼H 1 ðe j! Þ. The desired output can be given as Xðe j! Þ¼ H 0 ðe j! ÞXðe j! Þ. In order to separate the desired output from the error signal eðnþ, we can rewrite (1) as where Yðe j! Þ¼ H 0 ðe j! ÞXðe j! Þþ Qðe jð! Þ ÞXðe jð! Þ Þ H 0 ðe jð! Þ Þ ð3þ Qðe j! H Þ¼ 1 ðe j! Þ ð4þ H 0 ðe j! Þ From the above frequency-domain expressions, we can obtain the equivalent model with frequency response mismatches as shown in Fig. 2. Here, xðtþ is the analog input signal. xðnþ represents the desired TI-ADCs output without frequency response mismatches. yðnþ denotes the TI-ADCs output with frequency response mismatches. Fig. 2. Equivalent model of a two-channel TI-ADCs with frequency response mismatches. 4

5 Fig. 3. Calibration strategy of frequency response mismatches. 2.2 Adaptive blind calibration strategy The basic idea of the calibration is to obtain an estimation of the mismatch, which is denoted as ^eðnþ, and then eliminate it from yðnþ to approximate xðnþ. The structure in Fig. 3 can significantly improve the output signal yðnþ by using the normalized filter Qðe j! Þ defined in (4) [8]. According to [10], it s reasonable to model the Qðe j! Þ with a Pth-order polynomial in j! as Qðe j! Þ¼ XP c p D p ðe j! Þ p¼0 where c p is the pth coefficient of polynomial series and ð5þ D p ðe j! Þ¼ðj!Þ p <!< ð6þ is the discrete-time representation of a bandlimited pth order continuous-time differentiator. In general, it s accurate enough to make P equal to 2 or 3 [9, 10]. As long as we obtain the estimation ^c p of the polynomial series c p, frequency response mismatches can be compensated according to the calibration structure in Fig. 3, by replacing Qðe j! Þ with its estimation ^Qðe j! Þ. In order to estimate c p,we assume a special band as shown in Fig. 4, in which the input signal is absent but mismatch signal appears. Consequently, this method needs a slight oversampling of typically 10% 20%, which anyhow is commonly adopted in practical applications to accommodate filter transition bands [13]. A high-pass filter fðnþ is adopted to extract the mismatch signal eðnþ located in the input-free band from yðnþ. Finally, we minimize the filtered error energy "ðnþ by finding the estimates ^c p of the coefficients c p. When "ðnþ converges to its minimum value, the calibrated output ^xðnþ approximates the desired output xðnþ. Fig. 4. Output frequency spectrum with a input-free band dominated by mismatch error signal. 5

6 3 Low-complexity and full-parallel adaptive blind calibration algorithm In order to effectively eliminate the mismatch error signal, the algorithm in [9] requires that the clock frequency of the digital calibration devices must be the same as the overall sampling frequency of TI-ADCs. Limited by the maximum clock frequency, the digital signal processing devices is difficult to achieve real-time calibration as the increase of TI-ADCs sampling frequency. Thus, this paper proposes an efficient full-parallel real-time blind calibration algorithm. Taking advantage of the fast FIR algorithm, the FIR filters, as marked in Fig. 5, are converted into parallel form. Furthermore, to save resource consumption and parallelize the LMS structure, we present a downsampling signed-fxlms method which saves a third resources of a normal FFA filter. Fig. 5. Adaptive blind calibration structure. 3.1 Full-parallel calibration structure Aiming at parallelizing the algorithm as shown in Fig. 5, we firstly parallelize all the FIR filters, including the differentiator d 1 ðnþ and the high-pass filter fðnþ. The polyphase representation of a 2-parallel high-pass filter fðnþ can be given as Y 0 ðz 2 ÞþY 1 ðz 2 Þz 1 ¼ðX 0 ðz 2 ÞþX 1 ðz 2 Þz 1 ÞðH 0 ðz 2 ÞþH 1 ðz 2 Þz 1 Þ where H is the transfer function of the high-pass filter fðnþ. X and Y represent the Z-transform of the input signal xðnþ and the output signal yðnþ, respectively. The subscript 0 and subscript 1 represent the Z-transform of the even coefficients and the odd coefficients, respectively. For example, X 0 is the Z-transform of xð2kþ, whereas X 1 denotes the Z-transform of xð2k þ 1Þ. Y 0 is the Z-transform of yð2kþ, whereas Y 1 denotes the Z-transform of yð2k þ 1Þ. To separate the even output yð2kþ and the odd output yð2k þ 1Þ, we can rewrite Eq. (7) as [12] ð7þ Y 0 ¼ H 0 X 0 þ Z 2 H 1 X 1 ð8þ Y 1 ¼ H 0 X 1 þ H 1 X 0 ¼ðH 0 þ H 1 ÞðX 0 þ X 1 Þ H 0 X 0 H 1 X 1 According to Eq. (8), the two-parallel high-pass filter fðnþ can be realized according to the structure given in Fig. 6. Correspondingly, the modulated differentiator ð 1Þ n d 1 ðnþ is also designed with the 2-parallel structure. 6

7 Fig. 6. The structure of 2-parallel high-pass filter fðnþ. Fig. 7. The structure of 2-parallel adaptive blind calibration algorithm. According to the 2-parallel filter structure, the structure of the proposed adaptive blind calibration algorithm is depicted in Fig. 7. The sampled output yðnþ of the two-channel TI-ADCs is first divided into two groups as y e ðnþ ¼yð2kÞ and y o ðnþ ¼yð2k þ 1Þ. As illustrated in Fig. 7, y 0e ðnþ and y 0o ðnþ are the output of 0th-order differentiator (i.e., the delayed output of y e ðnþ and y o ðnþ to consider the casual implementation of the calibration algorithm). y 1e ðnþ and y 1o ðnþ are the output of the 1st-order differentiator, whereas y 2e ðnþ and y 2o ðnþ are the output of the 2nd-order differentiator. The even outputs y 0e ðnþ, y 1e ðnþ, y 2e ðnþ are multiplied by the corresponding coefficients to generate the estimated error signal ^e e ðnþ. Similarly, the odd output y 0o ðnþ, y 1o ðnþ, y 2o ðnþ are adopted with the estimated coefficients to generate ^e o ðnþ. Then we use the two groups of mismatch signal y e ðnþ and y o ðnþ to subtract the estimated error signal ^e e ðnþ and ^e o ðnþ to obtain the estimation ^x e ðnþ and ^x o ðnþ of xð2kþ and xð2k þ 1Þ, respectively. We utilize the parallel outputs of the differentiators and the estimated signals ^x e ðnþ and ^x o ðnþ as the input of the high-pass filters fðnþ. The filtered outputs are used to derive the LMS algorithm to obtain the mismatch coefficients of ^c 0 ðnþ, ^c 1 ðnþ and ^c 2 ðnþ. Moreover, it is worth noting that one can implement the 4-parallel or 8-parallel calibration structure based on 4-parallel or 8-parallel FIR filter [12] to further reduce the requirements of the clock performance. 3.2 Downsampling signed-fxlms estimation method As indicated above, we use FxLMS algorithm to converge the mismatch parameters. The coefficient updating expression is given as ^cðnþ ¼ ^cðn 1Þþ "ðnþy f d ðnþ The differentiator s outputs are filtered by the high-pass filter fðnþ to generate y f d ðnþ. The estimated signal ^x eðnþ and ^x o ðnþ are filtered by the high-pass filter fðnþ ð9þ 7

8 to generate "ðnþ. When updating the coefficients using Eq. (9), the coefficient ^cðnþ may not converge in the case of fixed-point operations due to the two successive multiplication [14]. Therefore, to make the coefficients convergent, we adopt the sign of y f d ðnþ and "ðnþ to realize the iteration function as ^cðnþ ¼ ^cðn 1Þþsignð"ðnÞÞ signðy f d ðnþþ ð10þ For signed-fxlms algorithm, the iteration step of ^cðnþ is a fixed value. In order to reduce the computational complexity, we propose a downsampling signed- FxLMS estimation structure for the mismatch coefficients, which is illustrated in Fig. 8. Here, # M denotes M times extraction. The high-pass filter spectrally separates the desired signal xðnþ from the error signal eðnþ by attenuating the xðnþ out of the input-free band, therefore, one can use the extracted error signal to drive the signed-fxlms algorithm, which does not affect the convergence of the mismatch coefficients. The decimation ratio M is determined by the adopted parallel number of the FFA. For this paper, we use 2-parallel structure, M is thus equal to 2. Benefited from downsampling process, it is not necessary to calculate the odd output (yð2k þ 1Þ shown in Fig. 6) of the high-pass filter f 0 ðnþ, f 1 ðnþ, f 2 ðnþ and fðnþ. That is to say, the filter H 0 þ H 1 of 2-parallel structure can be saved. The improved 2-parallel high-pass filter fðnþ is shown in Fig. 9, which saves a third resources of a normal FFA filter. We adopt the XOR logic operation of the sign bit of the "ðnþ with the sign bit of the downsampled y f d ðnþ. Then, the XOR s result is used to drive a lookup table (LUT) with outputs of μ or. The output of the LUT is connected to an accumulator to estimate the mismatch coefficients. As shown in Fig. 8, in general, we have fðnþ ¼f 0 ðnþ ¼f 1 ðnþ ¼f 2 ðnþ. In order to further reduce the algorithm complexity, one can replace the f 0 ðnþ with k delay units, where k is the group delay of fðnþ. Furthermore, it is feasible to replace Fig. 8. Downsampling signed-fxlms algorithm for mismatch coefficient estimation. Fig. 9. Improved 2-parallel high-pass filter fðnþ. 8

9 the f 1 ðnþ and f 2 ðnþ with f d ðnþ and s delay units, where s is the difference of the group delay between the filter fðnþ and f d ðnþ. The filter f d ðnþ is designed as a high-pass filter with a lower order than the fðnþ that remains unchanged. 4 Simulation results In order to verify the proposed algorithm, we construct the behavior model of the algorithm in MATLAB. We verify the performance of the calibration algorithm with various input signals. In the simulations below, we introduce different kinds of channel mismatches, including gain, timing and bandwidth mismatch. Thus, the two channel frequency response H n ðjþ, n ¼ 0; 1, are modeled as g n e jt sd n H n ðjþ ¼ 1 þ j ¼ ð1 þ n Þ c g n e jt sd n 1 þ jt s f s 2f c ð1 þ n Þ ð11þ where f s ¼ 1=T s denotes the sampling frequency. f c and c denote the 3-dB cutoff frequency and angular frequency, respectively. g n and d n are the relative gain mismatch and timing mismatch, respectively. n represents the deviations from c. The cutoff frequency of high-pass filter is set as 0:82. The order of the differentiator is 16. The orders of the high-pass filters f d ðnþ and fðnþ are 16 and 40, respectively. Example 1: we consider a multitone input signal consisting of 41 sinusoids with constant amplitudes, uniformly spaced frequencies, and random phases. Moreover, the signal is quantized to 16 bits. The cutoff frequency of the channel frequency response is set equal to the sampling frequency, i.e., f s ¼ f c. As the setting in [9], the values of g n are [ ], the values of d n are ½0:01 0:02Š and of n are ½ 0:004 0:004Š. The power spectrum of the uncalibrated output is shown in Fig. 10.1a. Before calibration, the SNDR is 31.4 db and the largest spur is 28.5 dbc. By using the proposed calibration method, the SNDR is improved to 77.2 db, and the SFDR increases to 70.2 dbc. The power spectrum of calibrated signal ^xðnþ is shown in Fig. 10.1b. As shown in the Fig. 11, the convergence curves precisely tend to the preset values. 1 Example 2: To demonstrate the versatility of the calibration method with different types of input signal, we consider a signal containing 15, 9 and 15 sinusoids, respectively. Moreover, the signal was quantized to 14 bits. The cutoff frequency is taken equal to the sampling frequency i.e., f s ¼ f c. In this example, the mismatch values are set as g n ¼½1:00 1:02Š, d n ¼½0:02 0:02Š, n ¼ ½ 0:005 0:005Š. The power spectrum of the uncalibrated output yðnþ is shown in Fig. 10.2a. Before calibration, the SNDR is db and the largest spur is 26.7 dbc. By using the proposed calibration method, the SNDR is improved to db, and the SFDR increases to 63.6 dbc. The power spectrum of the calibrated signal ^xðnþ is shown in Fig. 10.2b. 1 The preset values of c 0, c 1, c 2 are -1.49e-02, 1.53e-02, e-05 respectively. Since c 2 is much smaller than c 0 and c 1, its influence on the frequency spectrum is weak and can be covered by the noise floor. Therefore, the estimation results for c 2 may not be as accurate as for c 0 and c 1. 9

10 Fig. 10. (1) Calibration results with multi-tone input signal. (2) Calibration results with Multiple subbands input signal. Fig. 11. Convergence curves in Example 1. The line indicates the preset value. The red, blue and green curves indicate the estimation results of ^c 0, ^c 1 and ^c 2, respectively. 5 Resource consumption and performance analysis This section discusses the resource consumption of the proposed method. First, we use even orders to implement the digital differentiator, since the performance of the differentiator with odd orders are worse than even orders [19]. We assume the the order of the differentiator is N d, then the 2-parallel differentiator consumes ðn d =2Þ3 þ 2 multipliers and ðn d =2Þ3 þ 3 adders. Due to the adoption of the the downsampling signed-fxlms, the high-pass filter fðnþ with order of N h consumes N h þ 1 multipliers and N h adders. Furthermore, the proposed algorithm consumes 6 multipliers and 9 adders except for the FIR filters. It is worth indicating that the high-pass filter used for the differentiator s output, i.e., y 0e ðnþ, y 1e ðnþ, and y 2e ðnþ, can be designed with a lower order (denoted as N dh ) than the high-pass filter for the estimation ^x e ðnþ. The total resources consumption is given in Table I, where N d is the order of differentiator d 1 ðnþ, N h is the order of high-pass filter fðnþ, N dh is the order of high-pass filter f d ðnþ. Table I. Resources consumption of the proposed algorithm Items Multiplier Adder Differentiator d 1 ðnþ ðn d =2Þ3þ2 ðn d =2Þ3þ3 High-pass filter fðnþ N h þ 1 N h High-pass filter f d ðnþ N dh þ 1 N dh others

11 According to the simulation results in [15], it is sufficient to employ the highpass filters and the FIR differentiators with orders of 40 and 16, respectively, to reach the optimal calibration performance (SFDR of around 75 dbc). Through numerous simulations, it is found that the minimal filter of the high-pass filter f d ðnþ is 16. According to Table I and the proposed calibration structure in Fig. 7, the two differentiators consume 52 multipliers and 54 adders. The two high-pass filters f d ðnþ consume 34 multipliers and 32 adders. We employ one high-pass filter fðnþ, which consumes 41 multipliers and 40 adders. Consequently, the proposed calibration algorithm totally consumes 133 (26 2 þ 17 2 þ 41 þ 6) multipliers and 135 (27 2 þ 16 2 þ 40 þ 9) adders. Then, we consider the calibration method in [9]. The method totally costs 111 (9 2 þ 21 4 þ 9) multipliers and 198 (16 2 þ 40 4 þ 6) adders, where 9 multipliers and 6 adders are used except for the FIR filters. 2 The high-pass filter of this paper and [9] can be replaced with K delay units, however, the convergence speed and accuracy of the coefficients will be reduced. As we indicated above in Section 3, the operation clock frequency for the proposed calibration algorithm is only half of the correction method in [9] due to the adoption of full-parallel structure. Therefore, for a fair comparison, we consider the multiplication rate, which is denoted as the number of multiplications per output sample in the decimator [16, 17]. Let the multiplication rates of [9] is 111, then the multiplication rates of the proposed algorithm is only 133=2 ¼ 66:5. Furthermore, in both algorithms, the latency is mainly determined by the group delay L of the differentiator. In a 2-parallel FIR filter, the group delay of each branch is L=2. Therefore, the proposed algorithm can save half latency compared to [9]. The comparisons of the resources and the latency are shown in Table II. Table II. Resources and latency comparisons Items [9] Proposed algorithm Multiplication Rate Adder Latency L L=2 According to [18], the dynamic power consumption of a clock synchronized system is P ¼ V 2 C f ð12þ where α is the average number of 0-to-1 transitions per clock cycle, V is the supply voltage, C is the capacitance, f is the operation clock frequency. Assuming that α, V is invariable, the adder has a capacitance of C A and the multiplier has a capacitance of C M. The total capacitance of algorithm [9] is 111C M þ 198C A. The total capacitance of the proposed algorithm is 133C M þ 135C A. When the data throughout is the same, the operation clock frequency denoted as f o in [9] is twice of the clock frequency in this paper. Consequently, 2 The symmetric coefficients of linear-phase FIR filter has been considered in the analysis. 11

12 the power consumption of the algorithm in [9] is V 2 f o ð111c M þ 198C A Þ, whereas, the power consumption of the proposed algorithm is V 2 f o ð66:5c M þ 67:5C A Þ, which can save 40% of the multiplication power and 65.9% of the addition power than [9]. 6 Conclusion In this paper, we have proposed an efficient full-parallel real-time blind calibration algorithm for frequency response mismatches in two-channel TI-ADCs, where the clock performance is multiplied and the power consumption is reduced in the case of the same data throughput. Secondly, in order to save resources, we present a downsampling signed-fxlms method to estimate the mismatch parameter. Simulation results confirm the performance of the proposed algorithm. Through the complexity comparison with [9], it is noted that the proposed algorithm can save near 40% of resource consumption and a half latency under the comparative calibrated performance. Acknowledgments This work is supported by the National Natural Science Foundation of China (No ). 12