An Efficient and Flexible Structure for Decimation and Sample Rate Adaptation in Software Radio Receivers

Transcription

1 An Efficient and Flexible Structure for Decimation and Sample Rate Adaptation in Software Radio Receivers 1) SINTEF Telecom and Informatics, O. S Bragstads plass 2, N-7491 Trondheim, Norway and Norwegian University of Science and Technology (NTNU), Department of Physical Electronics, O. S Bragstads plass 2, N-7491 Trondheim, Norway 2) Norwegian University of Science and Technology (NTNU), Department of Telecommunications, O. S Bragstads plass 2, N-7491 Trondheim, Norway The idea of a software defined radio (SDR) receiver is to make as much of the signal processing as possible digital and software-defined. This has several advantages. The most obvious ones are that a single hardware terminal can then accommodate several different air interfaces, services and applications. This opens for a wide range of possibilities with respect to global roaming, backwards and forwards compatibility of radio systems etc. Another possible advantage is that the proper definition of parametrized algorithms for SDR may greatly aid manufacturers in moving from one hardware platform to another as hardware technology develops. For this to take place it is necessary that algortihms are suggested that are parmaetrizable not only with respect to varying air interfaces but also with respect to several possible hardware architectures. Among the several technological challenges faced by the SDR concept, one is the efficient flexible implementation of signal processing following immediately after the A/D converter. Due to the high bandwidth of this signal, the data rate will be very high, and the necessary hardware complexity and power consumption may easily become too high for cheap, portable equipment. The actual signal of interest will normally have a bandwidth significantly lower than the one digitized. Therefore, it is important to perform the channel filtering as close to the A/D converter as possible, thereby reducing the data rate at an early stage provided this operation can be performed at affordable cost. Another critical task is to deal with the mismatch between the actual sample rate of the A/D converter and the symbol/chip rate of the actual air interface. In a general SDR receiver, these can not be expected to be an integer multiple of each other. The process of reducing the sampling rate from the A/D converter to one which is an integer multiple of the symbol/chip rate will be termed (SRC) Included in this will also be the channel filtering. As explained in [3] the problem of sample-rate conversion can be split in an integer part and a fractional part. Because the fractional part is the more complicated one, it could be placed early in the cascade to ease the filter requirements as suggested in [3]. In an actual implementation it is the complexity or power consumption of the total system that matters. This complexity will depend on how well the chosen algorithms matches the available hardware resources. In one hardware platform memory may be scarce and computing resources abundant, in another the opposite may be the case. Often the access to fast multipliers

2 of sufficient wordlength is limited, whereas in some situations this is not a problem. In the following, we will make the quite realistic assumption that a fast multiplier is available, but for the sake of power consumption, one would like it to work at a lowest possible clock rate. An important difference between integer and fractional SRC is that the integer one can be performed by filters with fixed coefficients, while a time-varying filter is needed for fractional SRC (see next section). Hence, the integer part can be implemented without multipliers, for instance using distributed arithmetic. We are thus left with a concept where only the fractional part needs a general multiplier. In order to make the clock rate of this multiplier as low as possible, a solution is presented where the fractional part is placed after the integer part. It will be shown that by using a multirate structure, the filter requirements of the interpolator can be relaxed. This is done at the expense of extra memory for coefficient storage. In Figure 1 the overall structure of the solution is outlined. x (n) x(k) 2 α β y(m) First a sample-rate reduction by a power of two is performed. By choosing this conversion factor, the filter can be implemented by a cascade of linear phase half-band filters, each performing a decimation by two. Because approximately half of the coefficients are zero, the computational load for a given filter order is low. By choosing a sufficient number α of half-band stages, the final time-varying, fractional SRC will be by a factor β in the interval between 1 and 2. The theory and implementation of half-band filters is well known (see for instance [1]). In the remainder of the paper we will therefor concentrate on the fractional interpolator. We will also assume that matched filtering is included in the integer part, so that the only requirement of the fractional part is to suppress spectral images introduce by the interpolation process itself. When interpolating by a given rational number β =, a straight-forward solution can be found by doing an interpolation by followed by a decimation by In the context of SDR, however, we cannot assume that such a rational expression is given. We will therefore treat the problem of fractional interpolation as one involving an arbitrary (possibly irrational) factor β. As explained in [2, 4] the problem of fractional interpolation is complicated by the fact that it results in a digital filter, where the coefficients need to be computed at run-time. To make this computation as simple as possible, the use of interpolation filters (such as Lagrange interplators) is usually preferred. Polynomial interpolators generally have bad properties both with respect to transition bandwidth and stopband attenuation. A way of overcoming this is to use a multirate structure where the interpolation is carried out at a higher sampling frequency. A digital pre-filter is designed to meet the requriements in the passband and stopband. The polynomial filter will have zeros centered at the repeated spectra of the prefilter (see case study in the next section) and cancel the spectral images here. The concept is illustrated in Figure 2 below. x(k) N g(k) h(t) y(m) f s,1 f s,2

3 The polynomial filter is here shown as the simulation of an analog filter with subsequent resampling. Now, it may seem a little awkward to perform an upsampling immediately after a careful decimation to reduce the clock rate. The clue is, of course, to implement the pre-filter as a polyphase filter, and only compute those samples that are necessary to find the output of at the appropriate instances given by the output sampling frequency V2. Together the scheme is equivalent to applying an ideal D/A conversion followed by a filter ( ) = ( ) ( ) and a resampling at the new rate. The scheme was introduced by Ramstad Q and is explained in further detail in [4]. Denoting the input sampling rate V1 = 1/ 1 and the output sampling rate by V2= 1/ 2, the output sequence will be computed at instances... ( 2, 2, ( +1 2,... By using the time resolution of the filter given by τ = 1 /N, the output time instances can be expressed by an integer part P, and a fractional part ε P as follows:... ( P-1+ ε P-1) 1, ( P + ε P ) 1, ( P+1+ ε P+1) 1,... (see Figure 3). An index P = ( P mod ) determines which one out of sub-sets of coefficients for the filter should be used at each instance. denotes the order of the polynomial filter. The fractional part ε indicates where in the interval between two samples the interpolation is to be made. ε m-1 ε m ε m+1 T 1 T 2 Depending on the order of the polynomial filter, one or more multipliers will be needed for its implementation. (Actually, a multiplier-free solution is in principle possible by using a zero order polynomial. In that case the over sampling ratio will have to be large.) To reduce the number of multiplications, the two filters and may be combined to a so-called (see [2]). This solution is shown in Figure 4. x(k) j j j w w 1 w R ε y(m) In the generalized Farrow structure the pre-filter is replaced by sub-filters each of the same order as. Because only one polyphase branch is used at a time, the actual order will be only Again, the index determines which of coefficient sets to use. Note that the use of different coefficient sets does require the use of general multipliers in the sub-filters. If the over-sampling factor is low, several parallel filters may in effect be implemented, all but one being disabled at a given time instance. If distributed arithmetic is used, change of coefficients amounts only to a change of lookup-tables for precomputed sum-of-products.

4 In [3] the fractional part is placed in front of the integer one. In that case it is argued that the anti-aliasing property of the filter is more important than anti-imaging since the images can be made to fall in don t care bands. In the case with fractional part behind, the over-sampling is usually not very large, and don t care bands are of little or no use. In the subsequent design examples, we have assumed an over-sampling of two at the output of the fractional part, and designed the filters and so that sufficient stop band attenuation is obtained, suppressing all images at multiples of the original sampling frequency V1. In the first design example we consider the SINUS air interface. It is assumed that the integer part of the SRC has taken care of the channelisation and that out-of band noise is suppressed. The requirement of the fractional part will then be to suppress sufficiently the spectral images. For the case study we have assumed that a stop band attenuation of 4 db is adequate. Filter requirements are summarised in Table 1 below. Upper passband edge 2.4 MHz Lower stopband edge 7.6 MHz (lower edge of first image) Input sampling frequency V1 1 MHz (after integer decimation by 4) Output sampling frequency V MHz (twice the chip rate) Max. passband ripple.1 db Min. stopband attenuation 4 db The described approach allows the following parameters to be selected to obtain the given requirements Order of polynomial filter. Order of pre-filter. Over-sampling factor of pre-filter. These parameters can be traded off against each other to find an optimal solution for a given hardware platform. The order of the pre-filter will normally be determined by the stop band attenuation. The order of the polynomial filter can be made low by increasing the over-sampling factor. In the first example the pre-filter is designed as an equi-ripple filter with order (4 taps). This gives a stop-band attenuation of 4 db as shown in Figure 5 a). a) b)

5 The frequency range shown in Figure 5 a) is from to V1/2, since the filter operates at the upsampled rate. In in Figure 5 b) the dashed line shows the frequency response of the analog filter We see how the repeated passbands of are suppressed at each multiple of V1, and how the combined response fulfils the stop band requirement. With a generalized Farrow-structure implementation, this design would give two sub-filters, each with four taps. Ten different coefficient sets (or look-up tables using distributed arithmetic) would have to be available. The polynomial filter would require one multiplier working at the lower sampling rate. In the next example we will show how to avoid the multiplier all together. This is done by choosing a zeroorder polynomial filter. To obtain sufficient stop-band attenuation the pre-filter order is now increased to = 139 and an over sampling factor = 4 is used. The synthesis results are shown in Figure 6. a) b) With a zero-order interpolator, the generalized Farrow structure contains only one sub-filter, which is now identical to Even though the filter order is increased, the computational load of the pre-filter is actually less than in the previous example (3-4 coefficients depending on the chosen polyphase branch). In Table 2 the results are summarized together with similar results for two other air interfaces, UTRA-α and GSM. Only zero order and first order interpolators are investigated. In addition to the up sampling rate and filter order of the average number of coefficients included in the computation of each output value is noted for the various implementations. V1 V2 = = 1 1 MHz MHz α 1 MHz MHz khz khz As expected, the complexity of SINUS and UTRA-α are almost identical. However, a slightly smaller complexity is obtained for UTRA-α due to the larger transition band (smaller signal bandwidth) for this air interface. The GSM interface has the lowest filter order of the three since the relative bandwidth is smallest in this case. In all three cases the necessary order of the filters are in the same order of magnitude. This

6 means that a common architecture could be used for implementation in an SDR receiver. The sampling rate is probably prohibitively large for a DSP solution. Therefore a solution using an FPGA or a parametrizable ASIC could be imagined. Using these kinds of technology, choosing distributed arithmetic is often favourable. The average number of involved coefficients gives an indication of the complexity needed for this hardware. It is seen that this is approximately equal for all alternatives. Of course the necessary clock frequency is much smaller in the GSM case. Apart from this, the main difference between the alternatives is the necessary storage capacity, which is proportional with ( + 1) We note that the necessary capacity is only doubled by removing the multiplier (using = in stead of = ). We have then neglected the necessary coefficient wordlength, which will also determine the need of storage. A multirate structure for sample-rate conversion in software radio receivers has been presented. It has been illustrated how adjustment of parameters in the algorithm can give different implementations to fit different hardware architectures. It has been emphasized to reduce the need of general multipliers. Therefore only low order ( =, 1) polynomial interpolators have been investigated. In the studied examples it is seen that one can omit the multiplier by doubling the necessary storage space when using an implementation with distributed arithmetic. In most cases this would be a favourable tradeoff both with respect to area and power consumption. [1] R. E. Crochiere and L. R: Rabiner: Englewood Cliffs, [2] T. A. Ramstad: Proc. EUSIPCO 1998, pp [3] T. Hentschel, M. Henker, and G. Fettweis:, This conference. [4] T. A. Ramstad:, IEEE Trans. Acoust., Speech, Signal Proecessing, 32(3): , June 1984.