School of Computer Engineering, Supelec, Rennes Nanyang Technological University, France SCEE. Singapore

Transcription

1 FLEXIBILITY, HARDWARE REUSE AND POWER CONSUMPTION ISSUES IN THE DIGITAL FRONT-END OF MULTISTANDARD SDR HANDSETS Navin Michael SCEE School of Computer Engineering, Supelec, Rennes Nanyang Technological University, France Singapore

2 FLEXIBILITY VS. ENERGY EFFICIENCY IN 4G 4G core IP network Higher throughput requirement Energy Efficiencies ~1 TOPS/W LTE Seamless Mobility Wimax Wi-Fi Seamless Mobility Standard agnostic terminals enabled by software defined radio Flexibility needed for seamless mobility Flexible hardware less energy efficient _than custom hardware Need to reduce the area and power penalty of flexible portions of the radio

3 ENERGY EFFICIENCY OF DIGITAL PLATFORMS ASIC Gops/W 3 Energy Efficiency (Mops/mW) FPGA Gops/W DSP 1 10 Gops/W GPP Gops/W Flexibility [1] Rabaey JM "Wireless beyond the third generation facing the energy challenge " Low Power Electronics [1] Rabaey, J.M., Wireless beyond the third generation-facing the energy challenge, Low Power Electronics and Design, International Symposium on, 2001., vol., no., pp.1-3, 2001

4 SDR TERMINAL RECEIVER CHAIN : DIGITAL FRONT-END Programmable Analog Front End Programmable ΣΔ ADC Flexible Digital Front-end SDR Baseband Computational load is strongly dependent on the design of the analog front-end and ADC.

5 SDR TERMINAL RECEIVER CHAIN : DIGITAL FRONT-END Programmable Analog Front End Programmable ΣΔ ADC Flexible Digital Front-end SDR Baseband A fixed digitization bandwidth relaxes the flexibility requirement of the analog front-end in multistandard radios

6 FIXED DIGITIZATION BANDWIDTH Coarse band selected by the analog front--end Interferer Channel of interest Standard -1 Interferers Channel of interest Standard -2 Channel of interest Standard -3

7 SDR TERMINAL RECEIVER CHAIN : DIGITAL FRONT-END Programmable Analog Front End Programmable ΣΔ ADC Flexible Digital Front-end SDR Baseband Highly computationally intensive Operates on highly oversampled ADC output Needs to be implemented using a flexible ASIC HW accelerator

8 MULTISTANDARD CHANNELIZATION ACCELERATOR Functions Channel Selection Sample Rate Conversion Interferer Attenuation Pulse Shaped Filteringi

9 MULTISTANDARD CHANNELIZATION ACCELERATOR Variable channel bandwidths and band edge specifications Functions Channel Selection Sample Rate Conversion Interferer Attenuation Pulse Shaped Filtering

10 MULTISTANDARD CHANNELIZATION ACCELERATOR Variable SRC factors (integral or rational) Functions Channel Selection Sample Rate Conversion Interferer Attenuation Pulse Shaped Filtering

11 MULTISTANDARD CHANNELIZATION ACCELERATOR Variable interferer location and power levels Functions Channel Selection Sample Rate Conversion Interferer Attenuation Pulse Shaped Filtering

12 MULTISTANDARD CHANNELIZATION ACCELERATOR Variable roll-off factor Functions Channel Selection Sample Rate Conversion Interferer Attenuation Pulse Shaped Filtering

13 DESIGN SG SPACE OF A FLEXIBLE HW ACCELERATOR Single Mode HW Accelerator Area Power

14 DESIGN SG SPACE OF A FLEXIBLE HW ACCELERATOR Single Mode HW Accelerator Area Behavioral Optimizations Constant propagation Common subexpression elimination Operator strength reduction Power

15 DESIGN SG SPACE OF A FLEXIBLE HW ACCELERATOR Area Single Mode HW Accelerator Flexibility penalty Flexible HW Accelerator Power Reconfiguration latency

16 THE FLEXIBILITY PENALTY Limited silicon area Scalability Battery life and usability Area Power Leakage power in nanoscale CMOS Increased ops/s in emerging standards Seamless mobility Rec. Latency Vertical handover

17 MULTISTANDARD ACCELERATOR PARADIGMS: VELCRO APPROACH Accelerator 1 ADC Accelerator 2 Accelerator 3 Configuration Register

18 MULTISTANDARD ACCELERATOR PARADIGMS: MULTIMODE ASIC / CONFIGURABLE DATAPATHS Y(n) Y(n) Y(n) Y(n) Z -1 Z -1 Z * Y(n) 41 * Y(n) 10 * Y(n) DFG of three single constant integer multipliers Fused DFG Z -1 (19,41,10) * Y(n)

19 MULTISTANDARD ACCELERATOR PARADIGMS: FILTER COPROCESSOR Control o data address bus x(n) coefficient address bus Data Coeff Data Coeff Data Coeff Reg File Reg File Reg File Reg File Reg File Reg File x + x + x + z -1 z -1 z y(n)

20 MULTISTANDARD ACCELERATOR PARADIGMS: FINE-GRAINED RECONFIGURABLE FABRIC Configuration Access Port Interconnect LUT

21 GRANULARITY OF HARDWARE REUSE IN DIFFERENT MULTIMODE HARDWARE ACCELERATORS Reuse of fine-grained bit-level operators Reuse of coarse grained datapath operators Filter coprocessor Fine-grained reconfigurable fabric Multimode ASIC No reuse Velcro based multimode accelerator Finer granularity of reuse

22 GRANULARITY OF HARDWARE REUSE VS. FLEXIBILITY Highly Flexibility Limited Flexibility Flexible Filter coprocessor Fine-grained reconfigurable fabric Multimode ASIC Velcro based multimode accelerator Finer granularity of reuse

23 GRANULARITY OF HARDWARE REUSE VS. RECONFIGURATION DATA Large amount of reconfiguration data Reconfiguration data is a function of the filter length Low reconfiguration data Multimode ASIC Filter coprocessor Fine-grained reconfigurable fabric Velcro based multimode accelerator Finer granularity of reuse

24 GRANULARITY OF HARDWARE REUSE VS. POWER CONSUMPTION High dynamic power consumption Low dynamic power consumption High dynamic power consumption Filter coprocessor Fine-grained reconfigurable fabric Lowest dynamic power consumption Multimode ASIC Velcro based multimode accelerator Finer granularity of reuse

25 DESIGN STRATEGY FOR MULTISTANDARD DIGITAL FRONT-END The area, power and reconfiguration latency overheads need to be minimized without compromising ii on the flexibility to support a new specification. Identify opportunities for reusing hardware at coarser levels of granularity across multiple standards, with low parameterization overheads. The reused hardwired functional blocks should not be a bottleneck for supporting a new standard. Use area/power optimizations to minimize the overheads associated with functional blocks which demand a high degree of flexibility.

26 REUSE OF FILTER STAGES Coprocessor approach and multimode li ASIC approach reuse coarsegrained datapath operators : adders, multipliers, registers, MAC units. All the functionally different channelization tasks of filtering, sample rate conversion, interference attenuation and pulse shaping can be simultaneously performed by a multistage decimation filter. The filter stages in a multistage decimation filter represent a coarser granularity level for investigating hardware reuse, than simple datapath operators.

27 DESIGN OF A FILTER STAGE IN A MULTISTAGE DECIMATION FILTER Consider an arbitrary factorization of the SRC factor, M j j j j M j m1 m2 m3... m j n j ΣΔ ADC Sample rate Symbol rate M jf j H j m j H j j 1 z z m H j z n j j m n j F j Multistage Decimation filter for the jth standard

28 DESIGN OF A FILTER STAGE IN A MULTISTAGE DECIMATION FILTER M j F j pq F j H j k z p q F j F j Filter Stage for decimation by p, at an oversampling rate of pq

29 IDEAL DECIMATION FILTER 0 p 2 p

30 PRACTICALLY REALIZABLE DECIMATION FILTER 0 p 2 p fpass j k fpass j k j A k 0 p 2 p

31 STANDARD DEPENDENT PARAMETERS Passband edge, in a raised cosine pulse shaping system can be given by: Fpass j j F 1 j... 0 j 1 2 Roll-off factor fpass j Fpass j k j j p q F pq 2 1 Depend on the Stopband edge : fstop standard j 2 k j p pq 1 specific j parameters A k and j Stopband Attenuation : j A k

32 ELIMINATING STANDARD SPECIFIC DEPENDENCIES 1 j pq 1 j pq A j 0 pq p pq 2 p A max A j 0 p 2 p

33 OBSERVATION Above stage can be hardwired and reused by the decimation filter of any standard which needs: A decimation by p stage at an OSR of pq Required stopband attenuation for above stage is less than or equal to A max Can we manipulate the factorization of the SRC factor to exploit the above observation?

34 FIXED FACTORIZATION METHOD Fixed factorization method factorizes the SRC factor in a manner, which maximizes the number of filter stages at the same OSR and which decimate by the same factor, for different standards. M j = K j x m 1 x m 2 x.m n-1 x m n

35 FIXED FACTORIZATION METHOD - SUMMARY Fixed factorization ti method factorizes the SRC factor, in a manner, which maximizes the number of filter stages at the same OSR and which decimate by the same factor, for different standards. M j = K j x m 1 x m 2 x.m n-1 x m n Standard dependent rational factor Integral Load : CIC Filter Fractional Load : Transpose Farrow Filter Weakly parameterizable

36 FIXED FACTORIZATION METHOD - SUMMARY Fixed factorization method factorizes the SRC factor, in a manner, which maximizes the number of filter stages at the same OSR and which decimate by the same factor, for different standards. M j = K j x m 1 x m 2 x.m n-1 x m n Fixed integral factors, common to all standards Hardwired FIR filter stages No reconfiguration overheads

37 FIXED FACTORIZATION METHOD - SUMMARY Fixed factorization method factorizes the SRC factor, in a manner, which maximizes the number of filter stages at the same OSR and which decimate by the same factor, for different standards. M j = K j x m 1 x m 2 x.m n-1 x m n Fixed integral factor, common to all standards Programmable FIR filter Incurs reconfiguration latency area, power penalties

38 EXPERIMENTAL SYNTHESIS RESULTS Weakly parameterizable Fixed Fully programmable Standard SRC CIC Transpose Fixed Programmable Factor * Farrow Halfband FIR GSM W-CDMA IEEE a WiMax * A. Rusu, et.al., Reconfigurable ADCs enable smart radios for 4G wireless connectivity, IEEE Circuits Devices Mag., vol. 22, no. 3, pp. 6-11, 2006.

39 CHANNELIZATION ACCELERATOR AREA COMPARISON Standard Cell Area GSM IEEE a WCDMA Wimax Velcro Approach Proposed Multistandard Accelerator Synthesis results obtained from implementation using a TSMC 0.18 μm process pocess

40 OBSERVATIONS Nearly 65% reduction in area, compared to a Velcro approach for 4 standards. Percentage area reduction can be expected to increase with increasing number of supported standard. The fixed and weakly parameterizable portions of the architecture need to be designed for the worst case attenuation requirements. Paradigm is scalable for an arbitrary number of standards with low reconfiguration overheads.

41 REDUCING THE AREA/POWER PENALTY OF THE LAST STAGE FILTER Programmability in the last stage filter necessitates the use of generic MAC units. The last stage filter can be implemented as MAC FIR Filter. a time-shared Power reduction strategies for time-shared MAC based FIR filters have generally focused on reducing the switching activity. In nanoscale CMOS technologies, the leakage power also needs to be taken into account.

42 NANOSCALE CMOS POWER CONSUMPTION COMPONENTS Dependence on supply voltage (V DD ) and threshold voltage (V th ) Subthreshold Leakage Power Increases exponentially with reduced V th. Gate Leakage Power Increases exponentially with increased V DD. Dynamic Power : Increases quadratically with Dynamic Power : Increases quadratically with increased V DD.

43 EFFECT OF PARALLELISM ON OPERATING VOLTAGES Increasing the number of fixed MAC units, results in a reduced operating frequency while maintaining the same throughput. Reduced operating frequency translates to increased timing slack in the critical paths. Timing slack can be exploited for increasing V h or Timing slack can be exploited for increasing V th or reducing V DD.

44 EFFECT OF REDUCED FREQUENCY ON OPERATING VOLTAGES Locus of permissible (V DD,V th ) points for a different frequency constraints Effect of reduced frequency constraints on the permissible (V DD,V th ) points of a 16 bit adder ( TSMC 0.18um CMOS process )

45 NANOSCALE CMOS POWER CONSUMPTION COMPONENTS Dependence on Area Subthreshold h Leakage Power Has a linear dependence on total gate width. Gate Leakage Power Has a linear dependence on total gate width. Dynamic Power : Has a linear dependence on the total physical capacitance. Total Gate width and total physical capacitance are strongly correlated to the total circuit area.

46 PARALLELISM AND AREA-SLACK EFFICIENCY Parallelism trades increased area, for a lower operating frequency and increased timing slack. Increased timing slack can be traded for lower V DD and increased V th, and hence reduced total power consumption. Increased area penalty of parallelism, lowers the possible reduction in total power consumption Area-slack Efficiency : Amount of timing slack increment Amount of area increment

47 FULL PARALLEL DIRECT FORM FILTER OF LENGTH N x(n/f s ) z -1 z -1 z -1 z -1 z -1 x h 0 x h 1 x h 2 x h 3 x h N y(n/f s ) Throughput rate = f s

48 M-MAC BASED TIME-SHARED DIRECT FORM FILTER OF LENGTH N data address bus Nf s /M Control o clock x(n/f s ) coefficient address bus Data Coeff Data Coeff Data Coeff Reg File Reg File Reg File Reg File Reg File Reg File x + x + x + MAC-1 MAC-2 MAC-M z -1 z -1 z y(n/f s )

49 AREA SLACK EFFICIENCY OF A TIME- SHARED DIRECT FORM FILTER Cycle period of a M-MAC MAC based time-shared direct form filter of length: T M M Nf s Extra timing slack obtained by adding P MAC units, each of area A m P TM P TM Nf s Area-slack efficiency of a time-shared direct form filter E DF P Nf 1 PA m A m 1 Nf s Can we design filter structures that have a higher area-slack efficiency?

50 FAST FILTER ALGORITHMS (FFA) STRUCTURES Algorithmic i strength reduction : FFA structures have a lower number of expensive MAC operations at the cost of increased add operations. FFA structures can be derived by exploiting the redundancies in the FIR subfilters of a K-parallel FIR filter. x(2k+1) x(2k+1) Each FIR subfilter is of length N/2

51 FFA BASED TIME-SHARED FILTERS Time shared FFA structures can be obtained by implementing each of the FIR subfilters as a time-shared FIR filter, while implementing the irregular addition network in parallel. A KxK FFA structure of a N-tap filter has S k subfilters of length N/K,, and A k postprocessing/preprocessing p p p g adders. Notation, KxK L used to indicate a structure in which each of thes k subfilters is multiplexed onto L MAC units.

52 AREA-SLACK EFFICIENCY OF FFA BASED TIME-SHARED FILTERS Input sample rate of the subfilters in a KxK FFA is f s /K Cycle period of the MAC units in a KxK L FFA 2 K L TKK L Nf s Extra timing slack obtained by adding P MAC units in each of the S K subfilters K 2 P T KK ( LP) TKK L Nf Area-slack efficiency of a KxK FFA structure E PK 2 1 K FFA E DF Nf s S K PAm S K Am Nf s S K 2 s 1 K 2

53 FFA PARAMETERS K S k A k K 2 K 2 /S k E FFA K S 2 K E DF

54 OBSERVATIONS MAC units in the FFA based time-shared structures have a greater timing slack than a time-shared direct form filter with the same number of MAC units Adding MAC units to a time-shared FFA structure offers greater timing slack increment, than adding the same number of MAC units to a time-shared direct form structure.

55 CONCLUSION Proposed a design strategy for efficient implementation of a channelization accelerator for in a flexible mobile radio. Design has a high degree of hardware reuse across multiple standards. Proposed design strategy is scalable for supporting an arbitrary number of standards. We have investigated strategies for reducing the area/power penalty of the last stage programmable filter.

56 PUBLICATIONS International Journals [1] Navin Michael, A. P. Vinod, Christophe Moy and Jacques Palicot, Flexibility and reusability in the digital front-end of cognitive radio terminals, Circuits, Systems and Signal Processing Journal, Springer, Accepted in August [2] Navin Michael, Christophe Moy, A. P. Vinod and Jacques Palicot, Area-Power tradeoffs for flexible filtering in green radios, Journal of Communications and Networks, vol.12, no.2, pp , April International Conferences [1] Christophe Moy, Wassim Jouini, Navin Michael, Cognitive Radio Equipments Supporting Spectrum Agility, International Workshop on Cognitive Radio and Advanced Spectrum Management (CogART 2010), Italy, 7-10 November [2] Navin Michael, A. P. Vinod, Christophe Moy and Jacques Palicot, Low power, flexible FIR filters in the digital front-end of green radios, Proceedings of IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Istanbul, Turkey, September [3] Navin Michael, A. P. Vinod, Christophe Moy and Jacques Palicot, Area-efficient time-shared FIR filters in nanoscale CMOS, Proceedings of IEEE International Conference on Green Circuits and Systems, Shanghai, China, June [4] Navin Michael, A. P. Vinod, Christophe Moy and Jacques Palicot, Design paradigm for standard agnostic channelization in flexible mobile radios, Proceedings of IEEE International Symposium on Circuits and Systems, Paris, France, May-June [5] Navin Michael, A. P. Vinod, Christophe Moy and Jacques Palicot, Design of low power multimode time-shared filters, Proceedings of 7th IEEE International Conference on Information, Communications and Signal Processing, pp. 1-5, Macau, December [6] Navin Michael and A. P. Vinod, Reconfigurable architecture for arbitrary sample rate conversion in software defined radios, Proceedings of 19th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, pp. 1-6, Cannes, France, September 2008.

57 THANK YOU