Analog & Telecommunication Electronics

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Vanessa Anderson
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1 Test 1 In this amplifier C1, C2 and C3 have negligible impedance at the operating frequency. R1 = 18k R2 =??? Re = 10 k Rc = 8,2 k RL = 22 k Val = 15 V hfe > 400 Vbe = 0,6 V; Vcesat = 0,2 V Vi C1 R1 C2 Rc Vb R2 Re Vc Ve V AL C3 RL Vo a) Evaluate (within 5%) the value of R2 required to get a collector current Ic = 0,5 ma. Find the peak-to-peak output dynamic range without the load RL (ΔVov). Is C1=100 pf an acceptable value if Vi is in the MHz range? Explain your decision. The circuit is a common base amplifier; for biasing the behavior is the same as for CE. Ib = Ic/hFE = 1,25 microa; Ie = Ic (within the 5% approximation specified) gm = Ic/Vt = 19,23 ma/v; hie = 20,8 kohm Ve = Re Ie = 10k x 0,5m = 5 V; Vb = 5 + 0,6 = 5,6 V V(R1) = 15 5,6 = 9,4 V; I(R1)= 9,4/18 = 0,522 ma (>> Ib; same current in R2); R2 = 5,6 / 0,522 = 10,73 kohm (10k) ΔVov = Val (Ve + Vcesat) = 15-(5+0,2) = 9,8 V (p-p) In common base amplifiers the base must be GND for signals; time constant associated with C1-R1-R2 is: tau1 = C1 x R1//R2 = 100 p x 6,7 k = 670 ns; omega = 1,5 Mr/s 0,4 MHz. Base-to-GND impedance has a pole at this frequency; C1 can be considered a short circuit at 200 MHz and higher frequencies. The value C1 = 100 pf is OK b) Find the voltage gain Av = Vo/Vi with the load RL using linear transistor model. Evaluate the peak-to-peak output dynamic range with the load RL (ΔVol). Plot Vo(t) and Vc(t) for sine input signal with 100 mv peak value. Actual load on the collector R c = Rc // RL = 5,97 kohm With the small signal equivalent circuit: Ic = gm Vbe = - Vi gm; Vo = - Ic R c = Vi gm R c Voltage Gain Av = Vo/Vi = gm R c = 19,23 x 5,97 = 114,87 The output dynamic range with load can be evaluated from no-load range and the voltage divider made by the output resistance Rc and RL: ΔVol = ΔVov (RL)/(RL+Rc) = 9,8 x 22/30,2 = 7,14 V (p-p) (V) V C For Vi = 100 mvpeak, the output should go to about 11,5 Vpeak (23 Vpp), out of Vu dynamic range. That drives the BJT out of active region, into saturation and cutoff. Actual output is limited between Val and Ve+Vcesat (see question 1) ,9 9,8V 23V The Vc waveform is a sinewave with 23 Vpp amplitude, DC value Val Ic Rc = 15 8,2 x 0,5 = 10,9V, clipped at 5V and 15V 5 t On the load RL, Vo has the same waveform, with DC component = 0 (DC removed by C3). DDC -ATLCEscris1107c.doc - 21/07/ :28:00 1

2 c) Draw the output signal in the frequency domain (spectrum, in dbc), with sine input Vi = 27,6 mvrms, taking into account the nonlinearity of BE junction. (use linear interpolation for values of In(x) not in the table). 27,6 mvrms 39 mvpeak x = 1,5 This value is in the middle of two lines provided in the table; with linear interpolation the corresponding values are the mean value among the two lines. I2/I1 = (0,433-0,240)/2 = 0,336-9,46 db I3/I1 = 2I3/Io / 2I1/Io = (0,1866+0,035)/(1,395+0,893) = 0,2216/2,288 = 0, ,27 db d) A LC resonant circuit tuned to the input frequency Fi is connected in parallel with Rc. Evaluate the Q required to get at least 50 db separation between fundamental and harmonics on the output Vu, for Vi level as in c). The most critical is the II harmonic (III is lower). The II harmonic level is -9,46 dbc; to get -50 db the tuned circuit must provide 41,5 db additional attenuation. 41,5 db 112,2 X = = Q k 1/k ; Q = 112,2/1,5 = 74,8 Most frequent mistakes - Errors in CB gain evaluation (often < 1, like CC) - not considering Rc//RL for gain evaluation - DDC -ATLCEscris1107c.doc - 21/07/ :28:00 2

3 Test 2 A PLL locks for input signals from 600 to 800 MHz. It uses an analog Phase Detector, based on a 4-quadrant multiplier with Vi signal amplitude 0,4 Vrms, and Km = 0,8 [V -1 ]. The VCO has central frequency For = 700 MHz, gain Ko = 500 MHz/V, 3 kω input impedance at the Vc input, and generates a 3 V (peak to peak) sine wave. The loop filter is a RC cell, with R = 1,5 kω. a) Evaluate Kd F(0) for small values of e (in radians), and evaluate the range (min and max values) of control voltage Vc delivered to the VCO. For PD based on analog multipliers, with linear approximation (small phase error) Kd = Km Vi Vo /2 = 0,8 x 400 x 1,41 x 1,5 /2 = 338 mv/rad Due to the sine characteristic, the output of the PD saturates at Vd = 338 mv (for θe = pi/2 rad) F(0) includes the voltage divider caused by VCO input impedance: 3k/(3k + 1,5k) F(0) = ¾,5 = 0,667 Kd F(0) = 225 mv/rad Since max(sin) = 1, the max value of Vd is 338 mv. Vc comes from Vd through the voltage divider made by the loop filter and VCO input impedance Vcmax = Vdmax x 0,667 = 225 mv (positive and negative, respectively for θe = pi/2 and θe = -pi/2 b) Insert an amplifier in the loop filter, and find the DC gain F(0) required to get a steady state phase error er <= 0,1 rad over the complete operating range ( MHz). Draw the circuit of a suitable loop amplifier, using an Operational Amplifier. At extremes of frequency range ΔF = 100 MHz; since the VCO gain is 500 MHz/V, the required control voltage is Vcm = 100/500 = 200 mv. The VCO control input Vc corresponding to a phase error 0,1 rad is Vc = 0,1 x Kd x F(0) = 22,5 mv; The gain required to raise this signal to 200 mv is F(0) = 200/22,5 = 8,89 If the amplifier uses an Op Amp in noninverting configuration, the voltage partition caused by VCO input impedance is removed, and the actually required gain is 200/33,8 = 5,92 DDC -ATLCEscris1107c.doc - 21/07/ :28:00 3

4 c) Assume the VCO has linear fo(vc) characteristic. Find the value of C in the loop filter which gives a capture range (without the amplifier discussed in b) from 680 to 720 MHz. ΔFc for the capture range: 20 MHz (lock range/5) The required Vc is 1/5 the Vc required to move the VCO to the boundary of the lock range (ΔFl = 100 MHz) The loop filter pole must be placed at Fp = ΔFc/5 = 4 MHz; ωp = 2 pi Fc = 25,13 Mr/s; taup = 39,8 ns = RC; C = tau/r = 39,8n/1,5k = 26,5 pf d) Draw the block diagram and/or the schematic diagram of a suitable VCO circuit A VCO for this frequency range must use LC tuned circuit (sine signal source, e.g. Colpitts or other configurations). The frequency change can be obtained with a variable-capacitance diode. The diagram shows frequency control through the voltage controlled capacitor (Varicap diode) e) The PLL is used to generate the reference signal for a single-branch synchronous AM demodulator. Find the maximum error (% of full scale) at the AM demodulated output when the input signal frequency moves across the operating range. With the amplifier specified in b) the phase error at the extreme of the lock range is θemax = 0,1 rad. The corresponding amplitude error is Eam = 1 cos θemax = 1 0,995 = 0,005 0,5% Without the amplifier the phase error is θemax = 0,889 rad Eam = 1 cos θemax = 1 0,63 = 0,37 3,7% Most frequent mistakes - kd evaluated as for digital PD (supply voltage/pi) - DDC -ATLCEscris1107c.doc - 21/07/ :28:00 4

5 Test 3 An A/D conversion system uses 8 channels, each with a useful bandwidth from DC to 60 khz, and spectral power density flat from DC to 60 khz, then decreasing with a slope 20 db/dec. The ADC has a pipeline architecture, with 3 units based on 4-bit flash ADCs (12 bits total). a) Draw the block diagram of the complete A/D converter, specifying the precision required for each basic flash ADC. Find the total conversion time Tct, the latency Tlat, and the maximum sampling rate Fsm (for each channel) achieved using for each unit: - flash ADC with conversion time Tc = 80 ns - DAC with settling time Tas = 50 ns - S/H with acquisition time Tac = 60 ns. Block diagram in the text page 256 (single-bit stages), and in slides D3 61 (single-bit stage pipeline) and 70 (multibit residue). The precision required by ADCs and DACs depends from the position in the chain. To evaluate correctly the residue, the cell that evaluates MSBs must have a precision corresponding to full resolution (12 bits). Second stage requires 8 bits, and last stage (which does not evaluate residue) only 4. A new result is generated at every conversion time of a single stage; the equivalent conversion time Tct is: ADC conversion time Tc DAC settling time Tst S/H acquisition time Taq 80 ns 50 ns 60 ns Tct = 190 ns Latency is the total time from entrance of the analog sample Ai to availability of the corresponding complete digital value Di; the ADC has 3-stage residue pipeline architecture, but the last stage has no DAC. Latency is 3 times the conversion time of the single stage DAC Tst. Tlat = Tct x 3 Tst = 190 x 3 50 = 520 ns The maximum sampling rate of the ADC+S/H system is Fsc = 1/Tct = 1/190ns = 5,26 Ms/s; for a single channel the maximum sampling rate is Fsm = 5,26 M/8 = 658 ks/s b) The S/H has a sampling jitter Tja = 2 ns. Evaluate the related amplitude error (as % of full scale) and the SNRj = (signal power)/(samplig jitter error power), for triangular wave input with PP amplitude corresponding to half of full scale input range. Amplitude error caused by aperture jitter: Vj = Tj * SRmax SRmax = 2 60 khz S/2 = 188,5 k S ; Vj = 2 ns * 188,5 k S = 0,377 m S = 0,038% S Power of aperture jitter error: Pej = (0,377 m S)^2/12 (flat amplitude distribution) Power of triangular signal with amplitude half of full scale: Ps = (0,5 S)^2/12 SNRj = Ps/Pej = (0,5/0,377)^2 10^6 = 1,759 10^6 = 2, = 62,45 db DDC -ATLCEscris1107c.doc - 21/07/ :28:00 5

6 c) The input filter has a cutoff frequency Fc = 60 khz; Find the number of poles required to get a signal/aliasing noise ratio SNRa = 70 db, with a sampling rate Fs = 400 ks/s (for each channel). If Fs = 400 ks/s and the signal bandwidth Fb = 60 khz, the lowest frequency folded into useful band is = 340 khz. Due to spectral shape specified for the input signal, level at 340 khz is lower than baseband of 60/340 = 0, db. The filter must provide the remaining attenuation = 55 db. A single pole from 60 to 340 kh provides a 15 db attenuation; to get 55 db we need 55/15 = 3,67 4 poles. d) Find the Effective Number Of Bits (ENOB), considering quantization error, sampling jitter as in b), the signal/aliasing noise ratio as in c). With 12 bit SNRq = 12 x 6 + 1,76 = 73,76 db SNRq = 73,76 db SNRj = 62,45 db SNRa = 70 db 23,8 10^6 1,76 10^ ^6 Adding the power of each contribution: Pnt= Ps(1/SNRq + 1/SNRa + 1/SNRj) = Ps 10^-6 (1/23,8 + 1/1,76 + 1/10) = Ps 10^-6(0,710) SNRt = Ps/Pnt = 10^6 x 1,41 1, = 61,49 db ENOB = (61,49 1,76) / 6 = 59,73/6 = 9,95 bit (assuming input signal with flat distribution, the ENOB is only slightly different: 9,93) Most frequent mistakes - Evaluate the parameters requested in a) for a residue architecture (without pipeline). - Numeric errors in evaluation of El power. - Not considering the shape of input signal psectrum. DDC -ATLCEscris1107c.doc - 21/07/ :28:00 6

Telecommunication Electronics

Telecommunication Electronics Test 1 In the circuit shown in the diagram C1, C2 and C3 have negligible impedance at the operating frequency R1 = 120kΩ R2 = 220kΩ Rc = 6,8kΩ Val = 15 V hfe > 500 Vi C1 R1 R2 I1 Rc Ve Re1 Re2 C3 C2 V