HIGH-EFFICIENCY RF AND MICROWAVE POWER AMPLIFIERS: HISTORICAL ASPECT AND MODERN TRENDS. Dr. Andrei Grebennikov

Transcription

1 9 adio and Wireless Week Power Amplifier Symposium HIGH-EFFIIENY F AND MIOWAVE POWE AMPIFIES: HISTOIA ASPET AND MODEN TENDS Dr. Andrei Grebennikov grandrei@ieee.org

2 HIGH-EFFIIENY F AND MIOWAVE POWE AMPIFIES: HISTOIA ASPET AND MODEN TENDS I. POYHAMONI ASS F AND INVESE ASS F POWE AMPIFIES II. SWITHED-MODE ASS E POWE AMPIFIES III. SWITHED-MODE ASS FE POWE AMPIFIES

3 POYHAMONI ASS F AND INVESE ASS F POWE AMPIFIES. lass F: biharmonic and polyharmonic operation modes. lass F with quarterwave transmission line 3. lass F : load networks with lumped elements and transmission lines 4. lass F: DMOSFET power amplifier design examples 5. Inverse lass F: biharmonic and idealized operation modes 6. Inverse lass F: load networks with lumped elements and transmission lines 7. Inverse lass F: DMOSFET power amplifier design examples 8. Practical high-efficiency lass F power amplifiers 3

4 . lass F: biharmonic and polyharmonic operation modes Fourier series for: Third-harmonic peaking ( ωt) v V rectangular voltage waveform + 4 sin ωt + 4 sin 3ωt N n 5,7,... sin nωt n v n, 3 V half-sinusoidal current waveform i ( ωt ) I sin ωt cos ωt 3 n 4,6,... n N cos nω t i n, ωt 3f f I ωt D.. Prince, Vacuum Tubes as Power Oscillators, Part III, Proc. IE, vol., pp , Sept. 93 4

5 . lass F: biharmonic and polyharmonic operation modes v i n, 3, 5 n,, 4 V I ωt ωt 3f 5f f H. J. ound, Wireless Telegraph and Telephone Transmission, U.S. Patent,564,67, Dec. 95 5

6 . lass F: biharmonic and polyharmonic operation modes collector voltage For maximally flat waveforms collector current v/v c..5 n, 3 i/i.5..5 n, / 3/ θ V 9 V 8 cc V 3 V 8 cc optimum values / 3 / θ 4 I I I I 3 3 urrent harmonic Voltage harmonic components compo- nents, 3, 3, 5, 3, 5, 7, 3, 5,, /.5 9/ / / /.637, / /4.75 5/3.78 5/ /3.849,, 4 3/45.7 4/5.8 5/ / /45.95,, 4, 6 8/ / / / /75.93,, 4,, / / /56.9 5/

7 . lass F: idealized operation mode I max I i V cc v Ideal current waveform Ideal voltage waveform ωt I I max 4V V max I I P P V cc cc I max VccI P η P - fundamental current component - fundamental voltage component - dc current component - fundamental output power - dc supply power % - collector/drain efficiency Harmonic impedance conditions: V cc ωt Z Z Z n n 8 V I cc max 8 V I for even n for odd n cc 7

8 . lass F with quarterwave transmission line b V cc Assumptions for transistor: x l ideal switch: no parasitic elements i λ/4 i T v inc i inc v ref i ref i half period is on, half period is off: 5% duty cycle Assumptions for load: v in v sinusoidal current: ideal -circuit tuned to fundamental i(ωt) I sinωt - load current v(ωt) V cc v(ωt + ) i T /I i T (ωt) i T (ωt + ) I sinωt - transmission-line current - collector voltage i(ωt) I (sinωt + sinωt ) collector current ωt, 8

9 3. lass F: second current and third voltage harmonic peaking oad network V cc bypass ImY net (ω ) ImY net (ω ) ImY net (3ω ) Im ( Y ) net Output reactive admittance: ω out ω ω ( ω ) + ω Three harmonic impedance conditions: ( ω out )( ω ) ω out ( 4ω ) + ( 9ω )( 9ω ) 9ω out out Y net o out out Matching circuit with high impedances at harmonics ircuit parameters 5,, 6 ω 3 5 out S, db S simulation (f 5 MHz) Q ind f, GHz 9

10 3. lass F: even current and third voltage harmonic peaking V cc oad network bypass Harmonic impedance conditions at collector (drain): θ θ 3 ImY net (ω ) ImY net (nω ) ImY net (3ω ) θ Y net out Matching circuit with high impedances at harmonics S, S simulation (f 5 MHz) ircuit parameters: θ, θ3 6 θ tan 3 3Zω out f, GHz ideal transmission lines

11 3. lass F: even current and third voltage harmonic peaking oad network with impedance matching θ, degree 3 q V dd bypass 6. 5 m 4.5 λ/4 Z, θ Z 3 λ/ m n out Z net out θ, degree 7 q m Normalized parameters: out q Z m 7 5 m n ω out Z n

12 4. lass F: DMOSFET power amplifier design example 5 MHz lass F power amplifier with lumped elements pf 3 Ω.5 kω 4.5 nh 4 V pf Drain voltage and current waveforms v d, V i d, A Ω 3.6 nh pf 5 nh 5 nh P out P in 3.5 pf 6 pf. pf efficiency, % gain, db P in, dbm Output matching 3 t, nsec DMOSFET: gate length.5 um gate width 7x.44 mm inductance Q-factor efficiency - 8% linear power gain > 6 db inductance Q-factor 3 efficiency - 7% linear power gain > 4 db

13 4. lass F: DMOSFET power amplifier design example 5 MHz lass F power amplifier with transmission lines 4 V Drain voltage and current waveforms v d, V i d, A.5 pf 3 Ω 5 Ω 75.5 kω 5 Ω 3 Ω 9 pf 3 Ω Output matching 5 Ω pf 4 P in 5 Ω 45 3 Ω 3 5 Ω 3 P out 3 t, nsec efficiency, % gain, db DMOSFET: gate length.5 um gate width 7x.44 mm T-matching circuit for output impedance transformation 4 6 output power - 39 dbm (8 W) 4 collector efficiency - 76% P in, dbm linear power gain > 6 db 3

14 5. Inverse lass F: biharmonic and idealized operation modes Inverse voltage and current waveforms i n, 3 Second-harmonic peaking Fourier series for: rectangular current waveform I i ( ωt) I + 4 sin ωt + 4 sin 3ωt N n 5,7,... sin nωt n half-sinusoidal voltage waveform ωt N v( ωt ) cos n sin ωt cos ωt v V 3 n 4,6,... n n, ωt f V f ωt A. I. Kolesnikov, A New Method to Improve Efficiency and to Increase Power of Transmitter (in ussian), Master Svyazi, pp. 7-4, June 94 4

15 i I oncept of inverse lass F mode was reintroduced for low voltage power amplifiers designed for monolithic applications (less collector current) I 5. Inverse lass F: idealized operation mode Dual to conventional lass F with mutually interchanged current and voltage waveforms I V P 4I V V max I max P - fundamental current V V cc - fundamental voltage - fundamental output power I max VccI - dc output power ωt P η P % - ideal collector/drain efficiency v Harmonic impedance conditions: V max V cc ωt Z Z Z n n Vmax V 8 I 8 I for odd n for even n cc 5

16 5. Inverse lass F with quarterwave transmission line device is driven to operate as switch F zero impedances at odd harmonic components f V dd 3f 5f (n + ) f quarterwave transmission line as infinite set of series resonant circuits V dd sinusoidal current: shunt -circuit tuned to fundamental Z, λ/4 quarterwave transmission line as impedance transformer v in Z 6

17 6. Inverse lass F: second current and third voltage harmonic peaking V dd oad network bypass Harmonic impedance conditions at collector (drain): ImY net (ω ) θ θ 3 Z 3 ImY net (ω ) ImY net (3ω ) Z, θ Y net out Matching circuit with high impedances at harmonics S, db S simulation (f 5 MHz) ircuit parameters: θ, θ θ tan Z ω out f, GHz ideal transmission lines 7

18 7. Inverse lass F: DMOSFET power amplifier design example 5 MHz inverse lass F power amplifier with transmission lines 4 V Drain voltage and current waveforms.5 pf 3 Ω 5 Ω 75.5 kω 5 Ω 3 Ω 6 pf 3 Ω 44 5 Ω 63 Output matching 6 pf 6 4 v d, V i d, A..4.7 P in 5 Ω 45 DMOSFET: gate length.5 um gate width 7x.44 mm 5 Ω 45 5 Ω P out - 3 t, nsec -.7 efficiency, % gain, db pf 4 V 8.5 kω P in, dbm P in pf 5 Ω 63 3 Ω 3 Ω 54 5 Ω 3 Ω 65 3 Ω 6 5 Ω 45 9 pf P out output power - 39 dbm or 8 W collector efficiency - 7% oad network with output matching 8

19 Optimum load network resistances at fundamental for different classes of operation lass B : lass F : ( F) 4 cc 4 V I (B) cc V I Vcc P (B) Inverse lass F : (invf) V I cc 8 (F) (B) oad resistance in inverse lass F is the highest (.6 times larger than in lass B) ess impedance transformation ratio and easier matching procedure 9

20 8. Practical high-efficiency F and microwave lass F power amplifiers lass F GaN HEMT power amplifier with input harmonic control V g 4.5 V lass AB biasing with small quiescent current λ/4 λ/4 -circuits at the input for stable operation P in Z, θ Z 3 λ/6 P out characteristic impedance Z and electrical length θ is tuned to form third-harmonic tank with output device capacitance ds Input second-harmonic termination circuit is used to provide input quasi-square voltage waveform minimizing device switching time characteristic impedances Z and Z 3 are chosen to provide conjugate impedance matching at fundamental 85% power-added efficiency for 6.5 W at GHz D. Schmelzer and S. I. ong, A GaN HEMT lass F Amplifier at GHz with > 8% PAE, IEEE J. Solid-State ircuits, vol. S-4, pp. 3-36, Oct, 7.

21 8. Practical high-efficiency F and microwave lass F power amplifiers Inverse lass F DMOSFET power amplifier with quarterwave line lass AB biasing with small quiescent current 5 Ω 3.5 V 6 V -type low-pass 9.85 nh output matching circuit with shunt variable capacitance 3 pf 9.85 nh Z 3 Ω θ 9 Z 5 Ω θ 46.8 P in P out -type input matching circuit with shunt variable capacitance Z 5 Ω θ 4.7 Z 5 Ω θ pf series -circuit is tuned to fundamental pf 6% drain efficiency for 3 W at.78 GHz F. epine, A. Adahl, and H. Zirath, -Band DMOS Power Amplifiers Based on an Inverse lass-f Architecture, IEEE Trans. Microwave Theory Tech., vol. MTT-53, pp. 7-, June 5.

22 II. SWITHED-MODE ASS E POWE AMPIFIES. Effect of detuned resonant circuit. Basic lass E with shunt capacitance 3. Generalized lass E load network with finite dc-feed inductance 4. Parallel-circuit lass E 5. lass E approximation with transmission lines 6. lass E with quarterwave transmission line 7. Broadband lass E circuit design 8. Practical F and microwave lass E power amplifiers

23 . Effect of detuned resonant circuit anode efficiency of 9-93% for resonant-circuit phase angles of 3-4 : inductive impedance at fundamental and capacitive at harmonics resonant frequency f (.4-.5)f f fundamental frequency E. P. Khmelnitsky, Operation of Vacuum-Tube Generator on Detuned esonant ircuit (in ussian), Moskva: Svyazizdat, 96. load current lags collector voltage so that series -circuit must appear inductive at operating frequency pulsed excitation with highest efficiency for conduction angles less than 8 collector efficiency of 94% for W 5 khz bipolar power amplifier with 5% duty cycle G. D. Ewing, High-Efficiency adio-frequency Power Amplifiers, Ph.D. Dissertation, Oregon State University, June

24 . Basic lass E with shunt capacitance F I i i i F V cc v v in V be V cc Idealized assumptions for analysis: transistor has zero saturation voltage, zero on-resistance, infinite off-resistance and its switching action is instantaneous and lossless F choke allows only dc current and has no resistance total shunt capacitance is assumed to be linear reactive elements in load network are lossless loaded quality factor Q of series fundamentally tuned resonant -circuit is infinite to provide pure sinusoidal current flowing into load Idealized optimum or nominal conditions v ( ωt) ω t ( ωt) dv dωt ωt for optimum operation 5% duty cycle is used 4

25 . Basic lass E with shunt capacitance i /I Optimum circuit parameters : oad current ωt ω ω - series inductance - shunt capacitance ollector voltage v/v cc i/i ωt φ tan.5768 P V cc ω out tan - load resistance Optimum phase angle at fundamental seen by switch : ω ω ω o ollector current.5 I I.5 V ωt φ 5

26 . Basic lass E with shunt capacitance F Power loss due to non-zero saturation resistance V cc r sat P P sat out. 365 dc 8 rsatp 3 V cc rsat Non-ideal switch i τ sw i(τ ) τ Power loss due to finite switching time For τ sw P P sw dc τ sw.35 or τ τ +τ only % efficiency loss V cc F Nonlinear capacitance For nonlinear capacitances represented by abrupt junction collector capacitance with γ.5, peak collector voltage increases by % 6

27 3. Generalized lass E load network with finite dc-feed inductance b jx Optimum ideal voltage conditions across switch: i ( ω t) I sin( ω t + ϕ ) V cc - sinusoidal current in load v ( ωt) ( ωt) dv dωt ω t ωt load network consists of dc-feed inductance supplying also dc current, shunt capacitor, series reactance X, bondwire inductance b, series fundamentally tuned resonant circuit, and load shunt capacitor can represent intrinsic device output capacitance and external circuit capacitance active device is considered as ideal switch to provide instantaneous device switching between its on-state and off-state operation conditions series reactance X can be positive (inductance), zero and negative (capacitive) 7

28 3. Generalized lass E load network with finite dc-feed inductance ω ( ) v( ωt) ( ωt) d + b + v cc cos ϕ d ( ωt) V ωi ( ωt + ) - second-order differential equation ( ωt) v V cc q p cos t q where ( qωt) + sin( qωt) + cos ( ω + ϕ ) ( ), q / ω + b p ωi V and coefficients and are defined from initial conditions cc, ω ω b ω / q + + b p / + cos ϕ sin ϕ p - shunt capacitance - dc-feed inductance p + cosϕ sinϕ V P cc out / + b - load resistance 8

29 3. Generalized lass E load network with finite dc-feed inductance Normalized load network parameters versus q /ω, b p ϕ, ω/ X/ q q q.5: close to lass E with shunt capacitance with positive (inductive) series reactance (X > ) ω.5. P out /V cc.5. q.4: parallel-circuit lass E with zero reactance (X ) maximum load resistance q.468: maximum shunt capacitance (maximum operating frequency f max ) with negative (capacitive) reactance (X < ) q.5 9

30 4. Parallel-circuit lass E φ v in V cc V To define three unknown parameters q, ϕ and p, two ideal optimum conditions and third equation for zero reactive part of fundamental Fourier component are applied resulting to system of three algebraic equations: v ( ωt) ω t q.4 p ϕ 5.55 ( ωt) dv dωt. ωt X v t ( ωt) cos( ωt + ϕ) d( ω ) Optimum circuit parameters :.73 ω.685 ω V.365 cc P out - parallel inductance - parallel capacitance - load resistance: highest value in lass E 3

31 4. Parallel-circuit lass E i /I oad current Inductive impedance at fundamental - 4 ωt φ tan I I φ X tan ω I ω v/v cc ollector voltage I X V.5 i/i 8 ωt i /I.5 urrent through capacitance ollector current 8 ωt - 8 ωt 3

32 5. lass E with transmission lines: approximation 3 Two-harmonic collector voltage approximation v/v cc ωt 3 4 Optimum impedance at fundamental seen by device : Z + net o ( j tan 49.5 ) electrical lengths of transmission lines l and l should be of 45 to provide open circuit seen by device at second harmonic MESFET output l Z net out l V cc b transmission-line characteristic impedances are chosen to provide optimum inductive impedance seen by device output at fundamental T. B. Mader and Z. B. Popovic, The Transmission-ine High-Efficiency lass-e Amplifier, IEEE Microwave and Guided Wave ett., vol. 5, pp. 9-9, Sept

33 5. lass E with transmission lines: approximation 3.5 V 5 Ω Transmission-line parallelcircuit lass E GaAs HBT power amplifier for handset application v c /V cc 3 ollector voltage on off on 3 Ω, 8 5 Ω, 6 pf out Z net Z net (ω ) Z net (ω ) Z net (3ω ) 5 pf 4 pf 5 Ω parameters of parallel transmission line is chosen to realize optimum inductive impedance at fundamental output matching circuit consisting of series microstrip line with two shunt capacitors should provide capacitive reactances at second and third harmonics t, nsec i c, A 3 ollector current t, nsec urrent flowing through collector capacitor 33

34 6. lass E with quarterwave transmission line V cc Optimum voltage conditions across switch: i i i λ/4 i T i v ( ωt) ( ωt) dv dωt ω t ωt v v T sinusoidal load current 5% duty cycle di d d i ( ωt) ( ωt) Boundary conditions: d q + i ϕ ( ωt) i ( ) i ( ωt) ( ωt) ωt ω t V cc ω I ( ωt) + I sin( ωt + ) cos ( ϕ ) p ωi V cc - second-order differential equation q.649 p.3 ϕ q / ω 34

35 6. lass E with quarterwave transmission line v/v c i/i.5.5 i /I oad current ωt, ollector voltage ωt, ollector current Optimum circuit parameters : urrent through capacitance i T /I ω.75 ω V.465 cc P i /I.5 out - series inductance - shunt capacitance - load resistance urrent through transmission line ωt, ωt, ωt, 35

36 6. lass E with quarterwave transmission line Optimum impedances at fundamental and harmonics for different lass E load networks lass E load network f (fundamental) nf (even harmonics) (n+)f (odd harmonics) lass E with shunt capacitance lass E with parallel circuit lass E with quarterwave transmission line 36

37 7. Broadband lass E circuit design eactance compensation load network Device output Z in out eactance compensation principle X in ImZ in Input load network admittance Y in jω + + jω + jω ω ω To maximize bandwidth: ω ω ω / d ImY dω ( ω) in ωω ω ω + ω Optimum parameters for series resonant circuit in lass E mode - impedance provided by series resonant circuit - impedance provided by parallel resonant circuit summation of reactances with opposite slopes results in constant load phase over broad frequency range.6 ω / ω 37

38 7. Broadband lass E circuit design Broadband lass E power amplifier with reactance compensation f 8 MHz nf 3 Ω nh 5 Ω.5 kω 6 nh 8 V nf Drain voltage and current waveforms v d, V i d, A nf 5 nh 64 nh pf P out 4.5 P in pf pf pf nh efficiency, % gain, db t, nsec DMOSFET: gate length.5 um gate width 7x.44 mm 7. - drain efficiency > 7% - power gain > 9.5 db input power - W input VSW < f, MHz gain flatness ±.3 38

39 8. Practical F and microwave lass E power amplifiers High power DMOSFET F lass E power amplifier V nh MF83 4: nh 4 nh P in 55 pf pf pf lass B with zero quiescent current series inductance and ferrite 4: transformer is required to match device input impedance P out 5 Ω -type output transformer to match optimum.5 Ω output impedance to 5 Ω load quality factor of resonant circuit was chosen to be sufficiently low ( 5 ) to provide some frequency bandwidth operation and to reduce sensitivity to resonant circuit parameters required value of lass E shunt capacitance is provided by device intrinsic 38 pf capacitance and external 55 pf capacitance 7% drain efficiency for 54 W at 44 MHz H. Zirath and D. B. utledge, An DMOS VHF lass-e Power Amplifier Using a High-Q Novel Variable Inductor, IEEE Trans. Microwave Theory Techn., vol. 47, pp , Dec

40 8. Practical F and microwave lass E power amplifiers Transmission-line low-harmonic GaN HEMT lass E power amplifier -type low-pass input matching P in λ/4 V g lass biasing T Z λ/8 Z 3 λ/ 5 V λ/4 P out short transmission line T provides required series inductive reactance output open-circuit stubs are tuned to be quarterwave at nd and 3 rd harmonics and capacitive at fundamental Input second-harmonic termination circuit is used to provide input quasi-square voltage waveform minimizing device switching time characteristic impedances Z and Z 3 are chosen to provide load matching together with series line T 74% power-added efficiency for.4 W at GHz H. G. Bae,. Negra, S. Boumaiza, and F. M. Ghannouchi, High-Efficiency GaN lasss-e Power Amplifier with ompact Harmonic-Suppression Network, Proc. 37 th European Microwave onf., pp , 7. 4

41 III. SWITHED-MODE ASS FE POWE AMPIFIES. Basic load network and operation principle. oad network parameters and voltage and current waveforms 3. Design approximations with second-harmonic control (lass EF ) and third-harmonic harmonic control (lass E/F 3 ) 4

42 . Basic load network and operation principle V cc V cc b b lass DE lass FE Z, λ/4 lass E idealized optimum conditions applied to lass F mode affected by shunt parasitic capacitance, with added series inductance symmetrizing action of shunt quarterwave line provides its voltage inverter mode resulting in similar waveform as in lass D or lass DE: it stores voltage waveform in traveling wave along its length which returns delayed by one-half fundamental period and inverted due to reflection from short-circuited end Idealized optimum conditions v ( ωt) ω t ( ωt) dv dωt ωt transistor has zero saturation voltage, zero on-resistance, infinite off-resistance and its switching action is instantaneous and lossless 4

43 . Basic load network and operation principle λ/4 switch is turned on i T v/v cc. τ d τ d V cc i Sw v i V V i. ωt i/i switch is turned off 3.. V cc λ/4 i T i Sw v i V V i. ωt i T/I dead time during charging or discharging process when current flow through shunt capacitance half-wave symmetry of transmission-line current waveform: line attempts to do same work in first and second halves of cycle zero initial phase and duty cycle D < ωt i /I i /I ωt ωt 43

44 . oad network parameters and voltage and current waveforms V cc b Optimum circuit parameters : Z, λ/4 τ d ( + cosτ ) sinτ d cosτ d sin τ d d V P cc out ω - load resistance - series inductance τ d - dead time sin τ d ω - shunt capacitance High-efficiency mode f (fundamental) nf (even harmonics) (n+)f (odd harmonics) Optimum impedances at fundamental and harmonics for lass F, lass E and lass FE load networks lass F with quarterwave line lass E with shunt capacitance lass FE with quarterwave line short open short 44

45 3. Design approximations with second-harmonic control (lass EF ) and third-harmonic harmonic control (lass E/F 3 ) lass E F (or F E) power amplifier V dd I i v Idealized optimum conditions v ( ωt) ω t v/v dd ( ωt) dv dωt ωt.. ωt i/i transistor has zero saturation voltage, zero on-resistance, infinite off-resistance and its switching action is instantaneous and lossless 4.. D.35 ωt ideal lass E load network with shunt capacitance series resonant circuit tuned to second harmonic Z. Kaczmarczyk, High-Efficiency lass E, EF and E/F 3 Inverters, IEEE Trans. Industrial Electronics, vol. IE-53, pp , Oct. 6 45

46 3. Design approximations with second-harmonic control (lass EF ) and third-harmonic harmonic control (lass E/F 3 ) lass E/F 3 power amplifier V dd I i v 3 3 Idealized optimum conditions v ( ωt) ω t i/i ( ωt) dv dωt ωt.. ωt v/v dd D ωt transistor has zero saturation voltage, zero on-resistance, infinite off-resistance and its switching action is instantaneous and lossless ideal lass E load network with shunt capacitance series resonant 3 3 circuit tuned to third harmonic Z. Kaczmarczyk, High-Efficiency lass E, EF and E/F 3 Inverters, IEEE Trans. Industrial Electronics, vol. IE-53, pp , Oct. 6 46

47 eferences Andrei Grebennikov F and Microwave Power Amplifier Design McGraw-Hill 4 Andrei Grebennikov and Nathan O. Sokal Switchmode F Power Amplifiers Newnes 7 47