High Speed Mixed Signal IC Design notes set 9. ICs for Optical Transmission

Transcription

1 High Speed Mixed Signal C Design notes set 9 Cs for Optical Transmission Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu , fax

2 Cs for Optical Transmission: topics Systems: block diagrams, eye diagrams, waveforms Transmitters: Laser diodes, diode drivers Optical modulators, modulator drivers Receivers Photodiodes Receiver block diagrams: AGC and limiting AGC amplifier and detector, SNR constraints on limiting amplifier design Limiting amplifiers TA: SNR analysis, topologies DC restoration loops SNR analysis; Personik ntegrals Timing recovery PLLs, phase detectors for data steams, frequency locking Mux and Demux basic structures, timing thereof

3 Digital Optical Fiber Links Typical form of optical link : mux, transmitter, receiver, demux Motivation : Copper wires have high losses at high frequencies (see notes; skin effect) Optical fibers have low losses (~ 0.3 nm, 0.17 nm) Prevalent Mode of operation (2008) : Digital transmission Binary ntensity Modulation (On/Off) ncoherent (power) detection

4 Typical Signal Format: NRZ Modulation n each bit period, ntensity is modulated high / low to communicate1 vs 0 sent. Modulated intensity for "0" is not quite zero Extinction ratio P optical,1 / P optical,0 Eye pattern represents waveform vs. time modulo one bit period. Represents data trajectories for all possible sequences

5 Optical Transmitter: Directly Modulated Laser Diode Diode is driven by superposition of bias and AC drive current. Diode shows a sharp increase in light output when drive current exceeds laser threshold : P optical η( hν / q)( η quantum efficiency, ν optical frequency in Hz th ) Laser diode - V characteristics resemble those of a PN diode, except that forward voltage increases only slowly once threshold current is exceeded.

6 Laser Diode Characteristics Laser small - signal modulation reponse depends upon bias current. Bandwidth increases as bias current increases then saturates, collapses. Response is 2nd - order; damping increases at high currents. Few diode lasers exceed 25 GHz bandwidth (2008). Undesired wavelength modulation (chirp) makes lasers less attractive for long - range high - speed links. Though laser rate equations suggest a more complex model, laser electrical parameters are well - approximated by an ideal diode in series with a small (~ 5-10 Ω) series resistance.

7 Laser Transmitters Basic Form; sometimesuses DC feedback loop to maintain laser bias. Monitor diode generally on laser backside. DC loops not needed with modern low threshold lasers Laser & driver are not on same die. nterconnect is likely long and likely needs series to control line ringing. padding ( Rterm + Rdiode Z 0 )

8 Optical Modulators: EAMs C 1/ R q dp hν dv absorbed control Electro - Absorbion modulators: A reverse - biased PNjunction containing an optical waveguide in the region. Varying the reverse bias varies the optical attenuation. Electrical model is that of a reverse - biased diode, but with a parallel resistance representing the absorbed light. Device is loaded with a 50 Ohm parallel load, and driven with combined DC bias and pulse train.

9 Optical Modulators: Electo-optic Modulators nterferometer : split optical waveguide, give paths a relative phase shift, recombine. Output optical E - field intensity : E Output optical power ( P Voltage induces optical phase shift, changes output intensity / 2) 1 2 out [ + cos( πv / V )] ); cos( φ) ( φ) is ~ 4-6 V for 40 Gb/s modulators: need high - power driver. / 2) [ 1+ cos(2 φ) ] Electro - optic Modulator : Optical waveguide refractive index varies weakly with applied E - field. P V out π ( P in out signal E π out P out E o P in cos 2 ( P in

10 Drivers for Electo-optic Modulators Combination of high bandwidth and high drive (V, ) : Nearly always a distributed amplifier. np HBT or ngaas/np HEMT Single - ended or differential.

11 Optical Receivers: PN Photodiodes Reverse - biased diode with illumination of - region. ηq hν ph P opt ηq Poptical hν hν / q V at λ 1310 nm hν / q V at λ 1550 nm C εa/ D

12 Optical Receiver; with AGC Functions : Transimpedance amplifier : low input noise current, wideband Linear amplifier chain with variable gain; accomodate range of received power Low - pass filter * to bandlimit noise from to ~ 0.75 B (bit rate) (Not shown) AC coupling or DC restore loop : remove DC from signal Comparator toquantize in voltage M/S latch + PLLtoset decision timepoints f low * Filter bandwidth is the minimumsufficient for zero intersymbol so as to minimizenoise withindecision system bandwidth interference,

13 Limiting Optical Receiver Simpler form for highest - speed operation, No AGC; instead, amplifiers limit for stronger input signals. Each amplifier has bandwidth ~ 75% of B; bandlimits noise. As input power isincreased, more stages driven into limiting. Effective voltage comparison point is first limiting stage. Bandwidth exceeding > 0.75 B prior to limiting point degrades sensitivity. Form does not accomodate dispersion compensation AC coupling or DC restore needed ; not shown

14 AGC Amplifier: Bipolar Upper half is basic AGC cell Differential pair with variable current shunt. : Lower half is DC compensation : Adds DC as gain is reduced, compensates current reduction from upper block.

15 AGC Detector: Bipolar DC currents in the 2 BJTs are forced by current sources all to be Analysis (work in lecture) shows that for a inputs much larger than kt/q, Vout Vin, peak peak / 2 kt / q otbit / C 0.

16 Limiting Amplifier Chain: Bipolar Note input level - shift. nterconnect drivers /receivers might be current - steering or TAS/TS. Anticipate multiple TASTS stages; more than shown.

17 Limiting Amplifier Chain: CMOS & NMOS DC levels at Differential Vdd / 2 forms are also feasible; ask me.

18 DC Restoration Loop: nstead of AC Coupling Forward Gain : A OL A Loop Transmission : T v A / src v Reverse Gain : β 1/ src Closed - Loop Gain : A CL 1 β 1 A v T + T jf / 1+ jf f / src low f low Av / src 1+ A / src v where f low A v A v src / Av 1+ src / A / 2πRC v

19 Why TA input stage? S S E E n n E E n n ( f ) 4kTΓ / g ( f ) 2kT / g m m + 4kT ( R + R + 4kT ( R bb Detailed TA noise analysis left to reader; see noise notes. s + R g ex + R ) +... i ) + 2q R b 2 bb + (FET)... (BJT) 1/ 2πf high C in R f (1 + A v ) (Miller effect) S in in ( f ) 4kT / R f + (2πfC in ) 2 S E n E n ( f ) + S E n E n ( f ) / R 2 f / 2πf S high C in R L (need smaller R for same bandwidth) 2 2 ( f ) 4kT / RL + (2πfCin) SE E ( f ) + SE E ( f ) / RL +... in in n n n n (more noise because R is smaller)

20 Wideband TAs: CMOS & NMOS Left 2 designs are low - gain, wideband designs for very high bit rates. Right : Lower - rate design; larger open - loop voltage gain, permits larger R f

21 Wideband TAs: Bipolar Left : low - gain, wideband design for very high bit rates. Right : higher - gain, lower bandwidth design for moderate rates. higher A v larger R f feasible less noise.

22 Wideband TAs: Output DC Level This sequence has DC output levels of ( +φ, 0 V, φ). Consider what input DC levels TASTS chain can accept... Similar level - shifters can be /are used with all TAs shown. Designs Designs with many diodes : slow. with cascaded EF level - shifters : badly damped.

23 Receiver Sensitivity This will be derived in a subsequent notes set. Assume input noise of the form S in in ( f ) a + bf 2 Then P min where : Q SNR 2 n 2 hν Q qη a B for n + b B uncoded bit error rate This assumes channel filters having bandwidth ~ 75% of the bit rate B

24 Timing Recovery Data 3.8 Gb/s decision ckt D Q PLL 3.8 GHz PLL C Q DOD / DFD VCO System synchronizes a VCO to the average pulse period of the incoming data Phase detector must be tolerant of inherent to modulated data. phase reversals

25 Demultiplexer and interface with timing recovery

26 Tree demultiplexer Note that M/S/S latches are required to prevent timing skew.