FAN8811/D. High-Frequency, High Side and Low Side Gate Driver IC FAN8811T MPX

Transcription

1 High-Frequency, High Side and Low Side Gate Driver IC The FAN88 is high side and low side gate-drive IC designed for highvoltage, high-speed, driving MOSFETs operating up to 8. The FAN88 integrates a driver IC and a bootstrap diode. The driver IC features low delay time and matched PWM input propagation delays, which further enhance the performance of the part. The high speed dual gate driver are designed to drive both the high-side and low-side of N-Channel MOSFETs in a half bridge or synchronous buck configuration. The floating high-side driver is capable of operating with supply voltages of up to 8. In the dual gate driver, the high side and low side each have independent inputs which allow maximum flexibility of input control signals in the application. The PWM input signal (high level) can be 3.3, or up to DD logic input to cover all possible applications. The bootstrap diode for the high-side driver bias supply is integrated in the chip. The high-side driver is referenced to the switch node () which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to SS which is typically ground. The functions contained are the input stages, U protection, level shift, bootstrap diode, and output driver stages. Features Drives two N-Channel MOSFETs in High & Low Side Integrated Bootstrap Diode for High Side Gate Drive Bootstrap Supply oltage Range up to 3 A Source, 6 A Sink Output Current Capability Drives nf Load with Typical Rise/Fall Times of 6 ns/4 ns TTL Compatible Input Thresholds Wide Supply oltage Range 7. to 6 (Absolute Maximum 8 ) Fast Propagation Delay Times (Typ. 3 ns) 2 ns Delay Matching (Typical) Under-oltage Lockout (U) Protection for Drive oltage Operating Junction Temperature Range of -4 C to 2 C PACKAGE PICTURE Lead MLP (Molded Leadless Package) MARKING DIAGRAM DD SS LI ZXYTT HI FAN88T MPX Z : Plant Code X : -Digit Year Code Y : -Digit Week Code TT : 2-Digit Die Run Code MP : Package Type (MLP) X : Reel Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this datasheet. Typical Applications Power Supplies for Telecom and Datacom Half-Bridge and Full-Bridge Converters Synchronous-Buck Converters Two-Switch Forward Converters Class-D Audio Amplifiers Semiconductor Components Industries, LLC, 26 Publication Order Number: July 27- Rev. FAN88/D

2 Typical Applications DC L RHGATE Supply oltage DD C IN SS R LGATE C OUT L O A D C FAN88 LI HI PWM Controller FEEDBACK Figure. Application Schematic Synchronous Buck Converter DC R HGATE L O A D PWM Controller HI LI SS FAN88 C DD C IN Supply oltage R LGATE FEEDBACK Figure 2. Application Schematic Half Bridge Converter 2

3 Block Diagram DD 2 U 3 HI 7 LEEL SHIFT 4 LI 8 U SS 9 N.C 6 N.C Figure 3. Simplified Block Diagram 3

4 PIN CONNECTIONS DD FAN88 SS LI HI Figure 4. Pin Assignments Lead MLP (Top iew) PIN DESCRIPTION Pin No. Pin Name Description DD Logic and low-side gate driver power supply voltage 2 High-side floating supply 3 High-side driver output 4 High-voltage floating supply return N.C No Connection 6 N.C No Connection 7 HI Logic input for High-side gate driver output 8 LI Logic input for Low-side gate driver output 9 SS Logic Ground Low-side driver output 4

5 MAXIMUM RATINGS (Note ) All voltage parameters are referenced to SS, unless otherwise noted. Symbol Parameter Min. Max. Units DD Low-Side and Logic Fixed Supply oltage High-Side Floating Supply Offset oltage(note 2) - Repetitive Pulse (< ns)(note 3) -(24 DD) Low-Side Output oltage, Pin -.3 DD +.3 Repetitive Pulse (< ns)(note 3) -2 DD +.3 High-Side Floating Output oltage, Pin Repetitive Pulse (< ns)(note 3) LI, HI Logic Input oltage -.3 DD +.3 High-Side Floating Supply oltage -.3 to Supply oltage T J, Operating Junction Temperature - ºC. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. The negative voltage capability can be calculated using ( )-8 base on, due to its dependence on DD voltage level. 3. erified at bench characterization. ESD Ratings Symbol Parameters ALUE Unit. ESD M Human Body Model,JEDEC JS Electrostatic Discharge Capability ESD CDM Charged Device Model, JESD22-C Thermal Information Symbol Parameter ALUE Units P D Power Dissipation (Note 4) SP with thermal vias (Note).6 S2P with thermal vias (Note 6) 2.4 θ JA Thermal Resistance Junction-Air SP with thermal vias (Note ) 63 S2P with thermal vias (Note 6) 4 4. JEDEC standard: JESD-2, JESD-3. Mounted on 76.2 x 4.3 x.6 mm PCB (FR-4 glass epoxy material).. SP with thermal via: one signal layer with zero power plane and thermal via. 6. S2P with thermal via: one signal layer with two power plane and thermal via. W ºC/W RECOMMENDED OPERATING RANGES (Note 7) All voltage parameters are referenced to SS Sym Parameters Test Condition Min. Max. Unit. DD Supply oltage DC 7. 6 High Side Floating Return DC - 8 Repetitive Pulse (< ns) -(24 DD) oltage on DC d SW/dt oltage Slew Rate on SW /ns T J Operating Temperature -4 2 C 7. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

6 ELECTRICAL CHARACTERISTICS DD= =2, = SS=, T A=T J= -4 C to 2 C, no load on or, unless otherwise noted. Symbol Parameters Test Condition Min. Typ. Max. Unit Power Supply Section I DD DD Quiescent Current HI= ; LI=.7.3 ma I DDO DD Operating Current f SW = khz. 3. ma I Quiescent Current HI= ; LI=..2 ma I O Operating Current f SW = khz.9 3. ma I S to SS Quiescent Current = = 8 µa I SO to SS Operating Current f SW = khz.3. ma DDR DD U Threshold DD Rising DDH DD U Hysteresis.6 R U Threshold Rising H U Hysteresis.4 Input Logic Section IH High Level Input oltage Threshold IL Low Level Input oltage Threshold IHYS Input Logic oltage Hysteresis. R IN Input Pull-down Resistance k Bootstrap Diode FL Forward Low Current I DD- = µa..8 FH Forward High Current I DD- = ma.8. R D Dynamic Resistance I DD- = ma.7. t BS (Note 8) Diode Turn-off Time I F=2 ma, I RE=. A 2 ns Low Side Driver OLL Low Level Output oltage I = ma.6. OHL High Level Output oltage I = - ma, OHL = DD I OHL (Note 8) Peak Pull-up Current = 3 A I OLL (Note 8) Peak Pull-down Current = 2 6 A t R_ Rise Time % to 9%, C AD= nf 6 ns t F_ Fall Time 9% to %, C AD= nf 4 ns t R_ Rise Time 3 to 9, C AD= nf 3 ns t F_ Fall Time 9 to 3, C AD= nf 4 3 ns t LPHL LI=Low Propagation Delay LI Falling to Falling, C AD= ns t LPLH LI=High Propagation Delay LI Rising to Rising, C AD= 3 4 ns High Side Driver OLH Low Level Output oltage I = ma.6. OHH High Level Output oltage I = - ma, OHH = I OHH (Note 8) Peak Pull-up Current = 3 A I OLH (Note 8) Peak Pull-down Current = 2 6 A t R_ Rise Time % to 9%, C AD= nf 6 ns t F_ Fall Time 9% to %, C AD= nf 4 ns t R_ Rise Time 3 to 9, C AD= nf 3 ns t F_ Fall Time 9 to 3, C AD= nf 4 3 ns t HPHL HI=Low Propagation Delay HI Falling to Falling, C AD= ns t HPLH HI=High Propagation Delay HI Rising to Rising, C AD= 3 4 ns Delay Matching t MON HI Turn-OFF to LI Turn-ON 2 ns t MOFF LI Turn-OFF to HI Turn-ON 2 ns Minimum Pulse Width t PW Minimum Pulse Width for HI and LI (Note 8) ns 8. These parameters are guaranteed by design. 6

7 IO - OPERATING CURRENT [ma] HI,LI INPUT THRESLD [] CURRENT [ma] IDDO - OPERATING CURRNET [ma] CURRENT [ma] CURRENT [ma] FAN88 TYPICAL CHARACTERISTICS Typical characteristics are provided at 2 C and DD, = 2 unless otherwise noted IDD I -. IDD I DD () OLTAGE [] Figure. Quiescent Current vs. Temperature Figure 6. Quiescent Current vs. DD () IDDO IO - pf pf 22pF 33pF. FREQUEY [khz] Figure 7. Operating Current vs. Temperature Figure 8. IDD Operating Current vs. Frequency pf pf 22pF 33pF. FREQUEY [khz] Figure 9. I Operating Current vs. Frequency. IH IL. - Figure. Input Threshold vs. Temperature 7

8 OLTAGW [] OLTAGE [] THRESLD [] FORWAD OLTAGW [} HI,LI INPUT THRESLD [] THRESLD [] FAN88 TYPICAL CHARACTERISTICS Typical characteristics are provided at 2 C and DD, = 2 unless otherwise noted IH IL DD OLTAGE [].6.4 DDR.2 DDF - Figure. Input Threshold vs. DD Figure 2. DD U Threshold vs. Temperature R.2 FL.2 F. FH - - Figure 3. U Threshold vs. Temperature Figure 4. Bootstrap Diode F vs. Temperature OL OH..... OL OH. - TEMPERAUTRE [ ] DD OLTAGE [] Figure. OH, OL oltage vs. Temperature Figure 6. OH, OL oltage vs. DD() 8

9 SOURCE CURRENT [A] SINK CURRENT [A] PROPAGATION DELAY [ns] PROPAGATION DELAY [ns] PROPAGATION DELAY [ns] PROPAGATION DELAY [ns] FAN88 TYPICAL CHARACTERISTICS Typical characteristics are provided at 2 C and DD, = 2 unless otherwise noted High Prop delay Low Prop delay High Prop Delay Low Prop Delay - Figure 7. Low Side Propagation Delay vs. Temperature Figure 8. High Side Propagation Delay vs. Temperature High Prop Delay Low Prop Delay High Prop Delay Low Prop Delay DD OLTAGE [] DD OLTAGE [] Figure 9. Low Side Propagation Delay vs. DD Figure 2. High Side Propagation Delay vs SUPPLY OLTAGE [] SUPPLY OLTAGE [] Figure 2., Peak Source Current vs. Supply oltage Figure 22., Peak Sink Current vs. Supply oltage 9

10 Switching Time Definitions Figure 23 shows the switching time waveforms definitions of the turn on and off propagation delay times. HIN (LIN) % % LIN thplh thphl HIN tlplh tlphl 9% 9% () % % tr tf tmon tmoff Figure 23. Timing Diagrams Input to Output Definitions Figure 24 shows an input to output timing diagram for overall operation. DD U period DD DD U threshold voltage : Typ. 6.8 U period DD U Hysteresis DD U Hysteresis U threshold voltage : Typ. 6.3 HI PWM Input Threshold PWM Input Threshold LI Figure 24. Overall Operation Timing Diagram

11 APPLICATIONS INFORMATION The FAN88 are designed for drive the high side and the low side N-channel power MOSFETs in a half bridge or synchronous buck. The bootstrap diode integrates a driver IC for high side driver bias supply. High side and Low side outputs are independently controlled by each of input control signals with TTL or logic compatibly. The floating high side driver can work operate with supply voltage up to 8. The FAN88 functions consist of input stage, level shift, bootstrap diode, The Under-oltage Lockout (U) protection and output stage. The U function is included in both the highand low side. Input Stage The input pins (HI,LI) of gate driver devices are based on a TTL compatible input threshold logic that is independent of the DD supply voltage. Also, the PWM input signal (high level) can be 3.3, or up to DD logic input to cover all possible applications. The input impedance of the FAN88 is kω nominal. The kω is a pull down resistance to ground (GND). The logic level compatible input provides a rising threshold 2.2 and a falling threshold of.7. Level Shift The level shift circuit is the interface from the high side input to the high side driver stage which is referenced to the switch node (). The level shift allows to control of the output referenced to the pin and provides excellent delay matching with the low side driver. To control the High side output drive utilized a widely used technique for high side level shifter circuit is called pulsed latch level translators. When the HI input signal received from the controller, internal pulse generator make two kinds of pulse signal by the rising edge and falling edge. And then, this signal transmits a Latch through noise canceller. At this time, the pulse generator operating referenced to SS (ground), and level shift control of referenced to. Bootstrap Diode The FAN88 integrated high voltage bootstrap diode to generate the high side bias. And it is provided to charge high side gate drive bootstrap capacitor. The diode anode is connected to DD and cathode connected to. The boot capacitor should be connected externally to and the pins, the capacitor charge is refreshed every switching cycle when transitions to ground. The bootstrap diode provides fast recovery times, and low resistance value of.7 Ω Under-oltage Lockout (U) Both high side and low side driver have U protection independently which monitors the DD supply voltage and bootstrap voltage. The DD U disables both high side and low side driver when DD is below the specified threshold. The rise DD threshold is 6.8 with.6 hysteresis. The U disables only the high side driver when the to differential voltage is below the specified threshold. The U rise threshold is 6.3 with.4 hysteresis. Output Stage The FAN88 output stage is able to source/sink about 3. A /6. A typical and interfaces for drive the switching power MOSFETs. High speed switching, low resistance and high current capability of both high side and low side driver allow for efficient switching operation. The low side driver is referenced from DD to SS and the high side is referenced from to. The device logic status shows as below. Table. Status Device Logic Status HI LI L L L L L H L H H L H L H H H H X X L L Select Bootstrap Capacitor The maximum allowable voltage drop across the bootstrap capacitor to ensure enough gate-source voltage is highly dependent to the internal under voltage Lockout level of the gate drive IC, and the voltage level at the source connection of switching node. So, the maximum allowable drop voltage can obtain as (eq. ) DD f, U (eq. ) Where: DD: Gate drive IC supply voltage f : Static forward voltage drop of bootstrap diode.,u: Under-oltage Lockout level.

12 The total charge (Q bs) required by the bootstrap capacitor can be calculated by summing the Q g of the MOSFET and the charge required for the level shifter in the gate drive IC which is negligible quantity to compared Q g of the MOSFET. Q BS Where: Qg ( IS TON ) (eq. 2) Q BS: Total gate charge of bootstrap capacitor Q q: Gate charge of the MOSFET I S: Operating current in High side gate drive IC. T ON: Turning on of MOSFET The guiding criteria for calculating the minimum required bootstrap capacitance can be obtained through (eq. 4). C BOOT MIN Q BS. (eq. 3) Select External Bootstrap Series Resistor The FAN88 utilized high speed gate driving for synchronous buck and half bridge applications. In these applications, the ringing voltage occurred by parasitic inductance of the primary power path, consisting of the input capacitor and switching MOSFETs (C oss). To reduce the ringing phenomenon, the first step is to optimize the PCB layout to reduce parasitic components of the power path. And the second step is adding a series resistor with the bootstrap capacitor to slow down the turn-on transition of the high side MOSFET. Bias Supply Bootstrap Diode Driver LS Driver LS GND RB Input Supply L-D L-S L-D L-S COSS L OUT Figure 2. Application Circuit with Parasitic Components Figure 2 shows the synchronous buck with the parasitic component at the power path. Each of parasitic inductance and low side C OSS of MOSFET made up the ringing phenomenon at the node, when the high side turns on. When the bootstrap series resistor R B installed with bootstrap capacitor, the bootstrap resistor limits the C IN L O A D LCIN current available to charge the gate of the high side MOSFET, increasing the time needed to turn the high side MOSFET on. The increased switching time slows the node rate of rise and can have a significant impact on the peak voltage on the node. The bootstrap resistor recommended that R B is use to less than Ω. I DD f BOOT ( PEAK ) (eq. 4) RB Select Gate Resistor The gate resistor is also sized to reduce ringing voltage of the node by parasitic inductances and capacitances. But, it limits the current capability of the gate driver output by the resistance value. The limited current capability value by the gate resistor can obtain (eq. ). I I I I OHH OLH OHL OLL Where: DD DD DD DD R R R gate R gate gate f f gate OHL OLL OHH OLH (eq. ) I OHH: High side peak source current I OLH: High side peak sink current I OHL: Low side peak source current I OLL: Low side peak sink current f : Bootstrap diode forward voltage drop OHH: High level output voltage drop (high side) OLH: Low level output voltage drop (high side) OHL: High level output voltage drop (low side) OLL: Low level output voltage drop (low side) Gate Driver Power Dissipation The total power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are comprised of the static and dynamic losses related to the switching frequency, output load capacitance on high and low side drivers, and supply voltage, DD. The static losses are due to the quiescent from the voltage supplies DD and ground in low side driver and the leakage current in the level shifting stage in high side driver, which are dependent on the voltage supplied on the pin and proportional to the duty cycle when only the high side power device is turned on. The quiescent 2

13 current is consumed by the device to vias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state. The effect of the static losses within the gate driver can be safely assumed to be negligible due to the FAN88 has low quiescent current.7 ma typically. The dynamic losses are defined as follows: In the low side driver, the dynamic losses are due to two different sources. One is due to whenever a load capacitor is charged or discharged through a gate resistor, half of energy that goes into the capacitance is dissipated in the resistor. The losses in the gate driver resistance, internal and external to the gate driver, and the switching losses of the internal CMOS circuitry. Also, the dynamic losses of the high side driver have two different sources. One is due to the level shifting circuit and one due to the charging and discharging of the capacitance of the high side. The static losses are neglected here because the total IC power dissipation is mainly dynamic losses of gate drive IC and can be estimated as : P DGATE 2 DD W 2C f [ ] (eq.6) L S PCB Layout Guideline First of all, to optimize operation of high side and low side gate driving should be minimize influence of the parasitic inductance and capacitance on the layout. The following should be considered before beginning a PCB layout using the FAN88. The gate driver should be located nearby switching MOSFET as possible. The DD capacitor and bootstrap capacitor should be locate near by the device. In order to reduce ringing voltage of the node, the space both high side source and low side drain of the MOSFET should be close as possible. The exposed pad should be connect to GND plane and use at least four or more vias for better thermal performance. Avoid driver input pulse signal close to the node. One of recommendation layout pattern for the driver is shown in Figure 26. The bootstrap circuit power dissipation is the sum of the bootstrap diode losses and the bootstrap resistor losses if any exist. The bootstrap diode loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to switching frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor, resulting in more losses. IN DD FAN88 SS LI HI GND Figure 26. Layout Recommendation ORDERING INFORMATION Device Output Configuration Temperature Range ( ) Package Shipping FAN88TMPX High-Side and Low-Side -4 to 2 -Lead, 4. mm x 4. mm Molded Leadless Package (MLP) Tape & Reel 3

14 PACKAGE DIMENSIONS 4

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