An AI-Calibrated IF Filter: A Yield Enhancement Method With Area and Power Dissipation Reductions

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1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH An AI-Calibrated IF Filter: A Yield Enhancement Method With Area and Power Dissipation Reductions Masahiro Murakawa, Toshio Adachi, Member, IEEE, Yoshihiro Niino, Yuji Kasai, Eiichi Takahashi, Member, IEEE, Kaoru Takasuka, and Tetsuya Higuchi Abstract We have developed a large-scale integration (LSI) for - intermediate frequency (IF) filters, attaining a 63% reduction in filter area, a 26% reduction in power dissipation, compared with existing commercial products using the same process technology and filter topology, and a yield rate of 97%. The developed chip is calibrated within a few seconds by a genetic algorithm an efficient AI technique for difficult optimization problems. Our calibration method, which can be applied to a wide variety of analog circuits, leads to cost reductions and the efficient implementation of analog LSIs. Index Terms Analog integrated circuits, artificial intelligence, calibration, circuit testing, filters, genetic algorithms. I. INTRODUCTION AN INHERENT problem in implementing analog large-scale integration (LSI) or integrated circuits (ICs) is that the values of manufactured analog circuit components often differ from the precise design specifications. Such discrepancies cause poor yield rates, especially for high-end analog circuits. For example, in intermediate frequency (IF) filters, which are widely used in cellular phones, even a 1% discrepancy from the center frequency is unacceptable. It is, therefore, necessary to carefully examine the analog LSIs and to discard any which do not meet the specifications. In this paper, we propose an artificial intelligence (AI) calibration method which can correct these variations in the analog circuits values by genetic algorithms (GAs). Using this method provides us with three advantages: 1) enhanced yield rates: If an analog LSI is found not to satisfy specifications, then the GA is executed at the wafer-sort testing to alter the defective analog circuit components in line with specifications. Once calibrated, the circuit values are fixed by laser trimming. 2) smaller circuits and less power consumption: The conventional approach to overcome discrepancies of the component values in analog LSIs has been to use large compo- Manuscript received July 25, 2002; revised October 27, This work was supported in part by the Real World Computing Partnership (RWCP), Japan, and the New Energy and Industrial Technology Development Organization (NEDO), Japan. M. Murakawa, Y. Kasai, E. Takahashi, and T. Higuchi are with the MIRAI Project, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki , Japan ( m.murakawa@aist.go.jp). T. Adachi and Y. Niino are with Asahi Kasei Microsystems, Kanagawa , Japan. K. Takasuka is with Asahi Kasei Microsystems, Tokyo , Japan. Digital Object Identifier /JSSC nents. However, this requires larger spaces, which means higher manufacturing costs and greater power consumption. In contrast, with our approach, the area size of the analog circuits can be made smaller, because chip performance can be calibrated after production with the GA software. 3) integration of peripheral circuits to LSIs: As process technology allows for smaller and smaller implementations, it is possible to integrate more peripheral analog circuits in addition to digital signal processing circuits within a single LSI. However, because it is extremely difficult to integrate analog circuits with high-end specifications due to process variations, these analog circuits are usually made as separate components such as ceramic filters. In contrast, with the proposed method, it is possible to integrate these analog circuits on a single LSI, resulting in cost reduction and circuit area reduction. We have applied our method to an integrated - IF filter, where performance can be calibrated by GAs to enhance yield rates. In the developed chip, there are 39 components, which may differ from target values by as much as 10%. However, the GAs effectively absorb the variations in the values through calibration circuits. Although it has been difficult to reduce the size of - IF filters with existing CMOS technology while maintaining acceptable yield rates due to process-dependent variations in device parameters, with our method we have successfully achieved a 63% reduction in filter area and a 97% yield rate. In calibration experiments, we were able to successfully correct 29 out of 30 test chips to satisfy IF filter specifications, although all failed to meet these specification prior to GA calibration. The 63% reduction in filter area also led to a 26% reduction in power dissipation compared with existing commercial products. Existing commercial products and the developed chips have the same filter topology, i.e. an 18th-order linear filter consisting of three cascaded sixth-order cells, and are fabricated with the same technology, i.e., 0.6- m double-poly double-metal N-CMOS process. However, because the existing products adopt a conventional master/slave-based tuning system, the analog components in the chips must be large to achieve acceptable yield rates (over 90%). This paper is organized as follows. In Section II, the calibration method using GAs is described. Section III introduces the developed LSI for IF filters, and Section IV describes the results of calibration experiments. In Section V, future works are discussed before a concluding summary in Section VI /03$ IEEE

2 496 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003 Fig. 1. Calibration method using GAs. II. CALIBRATION METHOD USING GAS FOR ANALOG LSIS A. Analog LSIs Calibrated by GAs In analog LSIs, the characteristics of analog circuits such as resistors and capacitors vary widely due to process variation and environmental influence. As the process technique allows for finer implementations, these variations pose an even greater problem. This is especially problematic for conventional design methods, as it is impractical to incorporate sufficiently large performance margins. Therefore, to improve the yield rate, designers need to have a detailed understanding of circuit behavior and devise dedicated circuits to correct for the variations. However, theoretical design procedures for such correction have yet to be established. As a result, designers depend heavily on accumulated know-how. In order to compensate for these variations, some LSIs are manually adjusted after product, with a method called trimming [1]. In laser trimming, some resistors in the analog LSIs are partially burnt off using laser beams to adjust their values. However, such manual adjustment cannot be applied to mass production if the number of adjustment points is large. Moreover, this kind of manual adjustment method requires the skills of analog experts, who are in scarce supply due to recent advances in digital circuits. To overcome these difficulties, we propose a calibration method using GAs for analog LSIs. We accept that the values of analog components will deviate from specifications and instead of raising operational margins, we include a number of adjustable circuit parameters which are adjusted by GAs in order to calibrate the LSI to specifications. As a first application of our method, we have developed integrated - IF filters. Fig. 1 illustrates the GA calibration method for the developed - IF filter, consisting of 39 amplifiers connected in a cascade fashion. Each amplifier was designed so that its transconductance can be varied by altering a bias current fed to the amplifier. Each bias current can be finely adjusted according to a binary bit string written to a register for the amplifier. Collectively, the 39 binary bits strings that determine the 39 bias currents are referred to as the architecture bits. The optimal architecture bits for a chip is the set of binary bit strings that will minimize the effects of process-dependent variations in the circuit parameters and provide the target filter response. However, because of the sheer size of the search space, representing all possible permutations of the variables, it is impossible to determine manually the optimal architecture bits for each chip. For example, when the bias current control for each amplifier consists of six bits, the search space will represent permutations. GAs, which can be executed on either an LSI tester or a PC, are extremely efficient at solving this kind of difficult optimization problem. B. GAs GAs are robust optimization algorithms which are loosely based on population genetics [2], [3]. GAs can effectively find solutions in huge search spaces within reasonable computational costs. In GA optimization, a set of candidate solutions, represented as binary bit strings, is prepared. Each individual candidate is called a chromosome and the set of candidates is called a population. The problem to be solved is defined in terms of an evaluation function, called a fitness function, which is used to evaluate the chromosomes. Thus, a chromosome evaluated as having a high fitness value is likely to be a good solution of the problem. Let us consider the following function optimization problem as an example of a GA search: find where Max (1) First, the fitness function for this problem is set to be. Next, as shown in Fig. 2, an example population of four 5-bit chromosomes are generated at random. Each chromosome can be decoded to the variable in (1). Pairs of chromosomes are then randomly selected [Fig. 2(a)]. They are mated and undergo genetic operations, such as crossover and mutation, to yield better chromosomes for subsequent generations [Fig. 2(b)]. Chromosomes with lower fitness values tend to be eliminated from the population. This is repeated until approximately half the population has been replaced with new chromosomes. Therefore,

3 MURAKAWA et al.: AI-CALIBRATED IF FILTER 497 Fig. 2. Genetic algorithm. Fig. 4. Ideal frequency response and specifications of an IF filter. Fig. 3. Flowchart of the GA calibration. Fig. 5. Magnification of the graph in Fig. 4. after several generations of GA search, as in Fig. 2(c), relatively high-fitness chromosomes remain in the population [compare with Fig. 2(a)] and the best chromosome is chosen as a solution to (1). For the calibration of analog LSIs, the key is in treating the architecture bits as GA chromosomes. The GA software seeks the optimal architecture bits for each chip after production. Fig. 3 shows a flowchart of the GA calibration for the IF filter chip. Every chromosome is downloaded into the control register in the filter LSI. A fitness function is calculated by giving test inputs to the filter and observing the outputs. Transconductance values are varied to simultaneously optimize gain (frequency response) and group delay. This kind of simultaneous multiobjective optimization, which is an important feature of GAs, is difficult with other approaches. III. IF FILTER LSI FOR GA CALIBRATION This section introduces the developed IF filters in detail. The ideal frequency response [4] and typical specifications for an IF filter for the personal digital cellular (PDC) standard are shown in Figs. 4 and 5. The center frequency is 455 khz with a bandwidth of 21 khz. The frequency response should be attenuated to 30 db at 25 khz and to 60 db at 50 khz from the center. The most severe requirement is that the level of attenuation must be

4 498 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003 Fig. 6. Sixth-order bandpass filter section. TABLE I IDEAL PARAMETER VALUES Fig. 7. System architecture for the developed IF filter. 3 db at the frequencies of khz and khz. This requirement cannot be satisfied if there is so much as a 1% shift from the center frequency. However, by using the GA, it is possible to calibrate the chip to conform to the target specifications and, thus, enhance yield rates. This is achieved by adjusting for the shift in the center frequency due to process variations in order to meet this 3-dB attenuation requirement. A detailed description of the IF filter and how to compensate for such variations using genetic algorithms is given below. A. Filter Architecture Although many filter structures could provide a 455-kHz center frequency and 21-kHz bandwidth, we have adopted an 18th-order linear filter organization consisting of three cascaded structures [5]. Each of the three filter blocks has an all-pole sixth-order - leapfrog structure, shown in Fig. 6. The architecture for the filter is depicted in Fig. 7. As in most - filters, a master/slave approach is used to tune the values, with the master circuit being the filter in a phase-locked loop (PLL). This IF filter has 39 parameters in total, of which 18 are related to the center frequency ( ), 18 for bandwidth ( ), and three for filter gain ( ). Table I shows the target values for these parameters. In the integrated filter circuit, these parameters correspond to the transconductance values of the amplifiers. As the chip was designed to be smaller, the transconductance values can deviate by as much as to 10% from the target values. Although master/slave controllers can be used to correct for variations such as those due to temperature, where all the transconductance values deviate equally from the target values, they are not capable of adjusting for variations in order to satisfy design specifications, where the variations in transconductance values due to the manufacturing process will be random. Moreover, these controllers are unable to correct for group delay, which is in conflict with gain optimization. To overcome these difficulties, the developed chip utilizes GAs to compensate for these variations. While GAs can execute parameter optimization even when the parameters are interdependent, optimization is faster when the parameters are independent. In order to speed up the calibration times for the IF filter, two different kinds of amplifiers, shown in Fig. 8, are used. The designs for amplifiers for bandwidth [Fig. 8(c)] and those for center frequency [Fig. 8(d)] differ with the common-source pair circuits replaced with source-coupled pair circuits. If common-source pair circuits were also used in the amplifiers for bandwidth, it would not be possible to control bandwidth values independently of the center-frequency values, because the input voltages for bandwidth amplifiers would be common to those for the center frequency apmlifiers. Such interdependence would necessitate longer calibration times. B. GA Calibration The GA chromosome for the IF filter is 39 6 bits, with each 6-bit string determining the transconductance value of a amplifier. The six bits correspond to the switches in a digital-to-analog converter (DAC) (Fig. 9). The first bit determines whether the other five bits correspond to either Sw1 Sw5 or Sw6 Sw10 in Fig. 9. These switches subtly vary the bias current (Bias in Fig. 8) fed to a amplifier. Current sources are provided for,,,, and in Fig. 9 (i.e., small currents for calibration that are proportional to the generated at the PLL circuit). The is set to. The chromosome , for example, would set Sw1, Sw2, Sw4, and Sw5 to

5 MURAKAWA et al.: AI-CALIBRATED IF FILTER 499 (a) (b) Fig. 8. frequency. (d) Gm amplifier for bandwidth. (c) (d) Gm amplifiers (AMPs, in the figure). (a) Prototype Gm amplifier. (b) Gm/common-mode feedback (CMFB) amplifier. (c) Gm amplifier for center (3) Fig. 9. DAC for the bias current controlled by GAs. ON, so that the bias current would be raised to be, i.e.. Taking the chromosome as a further example, however, Sw8, Sw9, and Sw10 would be ON with the bias current reduced to, i.e.,. The fitness function for the GA is defined as fitness (2) This fitness function consists of a weighted sum of gain deviations and group delay differences measured around the center frequency. Here, is the ideal gain, and are the gain and the phase obtained by the filter chip at frequency, respectively, and and are the maximum and the minimum of the group delay in the passband. While the group delay requirement for the filters is 20 s, the design estimation for our filter using an 18th-order bandpass filter is 24 s. While this indicates that further calibration is required to meet this specification, it should be noted that even though it is impossible with linear filter theory to obtain optimal solutions for both group delay and frequency response due to their tradeoff relation, GA calibration using the fitness function is capable of satisfying both these specifications. IV. CALIBRATION EXPERIMENTS A. Developed IF Filter Chip The chips were fabricated in a 0.6- m double-poly doublemetal N-CMOS process. The supply voltage is 5.0 V and the

6 500 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003 TABLE II COMPARISON OF THE CIRCUIT AREA (a) Fig. 10. Die microphotograph. die area is mm. Fig. 10 shows a microphotograph of the die. In terms of circuit design, there are a number of important consequences of utilizing of GAs within this IF filter chip. The first is the very compact implementation of the amplifier which GA calibration makes possible. We can reduce current dissipation and the transconductance of the amplifier because the transistor channel width can be shortened. A second related point is that because the center frequency is determined by the ratio of capacitance to value, capacitance is small with smaller amplifiers. Another important point is that because the GA calibration is accomplished using a number of amplifiers, it is possible to achieve satisfactory levels of precision for the current sources with relatively simple bias current circuits. As a result of this new design method employing GA calibration, filter area was reduced by 63% compared with existing commercial products (from 3.36 to 1.26 mm ), resulting in a 26% reduction in power dissipation (from 3.4 to 2.5 ma, 38% reduction for the amplifiers; 58 A 36 A). Because an area of 1.81 mm was initially devoted for the calibration circuits (due to excessive provision of 39 6 bit registers and 39 DACs for calibration) in the test chips referred to above, the total chip area was only reduced to 91% (from 3.36 to 3.07 mm ). However, we have subsequently achieved a 100% yield rate with GA calibration experiments involving 18 parameters (three bits each). As a result, a commercial chip has been designed with adjustment circuitry for 18 3 bit registers and 18 DACs within an area of 0.41 mm. Thus, even including the area required for calibration, the total chip area is reduced 49% (b) Fig. 11. (a) Measured gain/delay response for the developed chip. (b) Magnification of (a). compared with conventional filter designs. This result is summarized in Table II. B. Calibration Results We used a population of 20 chromosomes with chromosome length of 234. The fitness in the GA was defined using the gain obtained by the chip at frequencies 444, 446, 453, 455, 464, and 466 khz. The target response is obtained by root-nyquist conditions; the ideal responses at the six frequencies are 3.7, 1.4, 0, 0, 1.4, and 3.7 db, respectively (see Fig. 5). We conducted calibration experiments for 30 real chips. On average, the GA was able to find an optimal architecture bits and terminate after 100 measurement iterations within a few seconds on an LSI tester. Clearly, GA calibration does not represent an obstacle to mass production. Fig. 11 shows the frequency responses and group delays for the best architecture bits obtained for a chip. In the calibration experiments, 29 out of

7 MURAKAWA et al.: AI-CALIBRATED IF FILTER 501 the 30 test chips could be calibrated to satisfy specifications, although none of these chips conformed prior to calibration (i.e. 97% yield rate), and the remaining chip was successfully calibrated with additional iterations. This result is consistent with statistical simulations for GA calibration, in which 952 out of 1000 virtual chips were successfully calibrated. For comparison, we conducted calibration experiments with a conventional hill-climbing method instead of the GA. A run terminated after fitness was evaluated 100 times. The result of this was that only 17 chips (57%) could meet the specifications. These results suggest the effectiveness of the GA in avoiding the local minimums in the evaluation (fitness) function. V. DISCUSSION This section discusses future problems of the developed chip. Other applications of our proposed method are also discussed. A. Future Problems of the Developed Chip The production cost of analog LSIs consists mainly of the wafer cost, the package cost, and the testing cost. Because the wafer cost is proportional to the mask area, the proposed method can greatly reduce the wafer cost. However, as the proposed method does involve additional calibration time, the overall costs at the testing stage are higher. It is crucial, therefore, to reduce the calibration time for commercial use of the proposed method. We have already further fine-tuned GA parameters (e.g., population size, crossover rate, mutation rate) and weight values of the fitness function. However, because optimal GA parameters are dependent on application, a systematic procedure for such tuning should be developed for a wide use of our method. B. Applications of GA Calibration The basic idea behind GA calibration is to regard the architecture bits of the reconfigurable analog circuits as chromosomes for GAs and to identify optimal configurations by running GAs. This approach can be applied to a wide variety of analog circuits and is not limited to the IF filter LSI. Using this approach, we have projects for image-rejection mixers [6] and clock skew adjustment in ultrahigh-speed digital circuits [7]. In the above applications, the chips are reconfigured only once or only at relatively longer intervals. Reconfiguration in these cases is usually conducted off-line by the chip manufacturers or by the chip user. However, on-line GA calibration could also be useful. This calibration can reconfigure chips on-line at regular intervals by observing the outputs from the chip. This on-line calibrated chip could be used in environments that vary over time (e.g., due to temperature or power supply). In such cases, GA hardware [8] should be incorporated into the chips, especially for analog LSIs in embedded systems. The GA hardware can handle self-reconfiguration without host-machine control. VI. CONCLUSION We have developed IF filter LSIs which can correct discrepancies in analog LSI implementations. The LSI includes current-adjustment circuits that employ the genetic algorithm to correct for deviations from the target frequency response due to variations in the values of analog devices. Using our method, 97% of the chips tested are successfully calibrated to conform to the specifications, although none of them satisfied specifications prior to calibration. Moreover, the filter area was reduced by 63%, resulting in a 27% reduction in power dissipation. The commercial version of the developed chip has been mass produced. This method has great potential, particularly for system-on-chip implementations, where one major obstacle has been the poor yield rates associated with analog circuit integration. ACKNOWLEDGMENT The authors would like to thank Dr. Hirose, ASRC, Prof. Sakurai, University of Tokyo, Dr. Yamashina, NEC, and Dr. Nakagawa, AIST, for their helpful suggestions. They also give special thanks to Dr. Otsu, AIST, for his consistent encouragement and advice. REFERENCES [1] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, [2] J. H. Holland, Adaptation in Natural and Artificial Systems. Ann Arbor, MI: Univ. of Michigan Press, [3] D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, MA: Addison Wesley, [4] J. Proakis, Digital Communications. Englewood Cliffs, NJ: Prentice- Hall, [5] T. Adachi, A. Ishikawa, K. Tomioka, S. Hara, K. Takasuka, H. Hisajima, and A. Barlow, A low noise integrated AMPS IF filter, in Proc. IEEE Custom Integrated Circuits Conf., 1994, pp [6] Y. Kasai, H. Sakanashi, M. Murakawa, S. Kiryu, N. Marston, and T. Higuchi, Initial evaluation of an evolvable microwave circuit, in Proc. 3rd Int. Conf. Evolvable Systems, 2000, pp [7] E. Takahashi, M. Murakawa, K. Toda, and T. Higuchi, An evolvablehardware-based clock timing architecture toward GHz digital systems, in Proc. 1st Genetic and Evolutionary Computation Conf. (GECCO99), 1999, pp [8] I. Kajitani, T. Hoshino, D. Nishikawa, H. Yokoi, S. Nakaya, T. Yamauchi, T. Inuo, N. Kajihara, and T. Higuchi, A gate-level EHW chip An implementation of hardware for GA operations and reconfiguable hardware on a single LSI, in Proc. 2nd Int. Conf. Evolvable Systems, 1998, pp Masahiro Murakawa received the B.E., M.E., and Ph.D. degrees in mechano-informatics engineering from the University of Tokyo, Tokyo, Japan, in 1994, 1996, and 1999, respectively. He is currently a Researcher with the National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan. His research interests include evolutionary algorithms, adaptive systems, and reinforcement learning. Dr. Murakawa received the Best Paper Award at the Second International Conf. Evolvable Systems, the Tsukuba Encouragement Prize for 2000, and the IEEJ Millennium Best Paper Award. He is a member of the Institute of Electrical Engineers of Japan (IEEJ).

8 502 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003 Toshio Adachi (M 87) was born in Osaka, Japan, in He received the M.S. degree in physics from Osaka University in He joined Asahi Kasei in 1979, where he initially worked on amorphous silicon devices. Since 1983, he has been with Asahi Kasei Microsystems, Kanagawa, Japan, where he is involved in CMOS analog integrated circuit design. Mr. Adachi is a Member of the Japan Society of Applied Physics and the Institute of Electronics, Information and Communication Engineers. Eiichi Takahashi (M 00) was born in Ibaraki, Japan, in He received the B.E. degree in electronic engineering and the M.E. and Ph.D. degrees in information engineering from the University of Tokyo, Tokyo, Japan, in 1987, 1989, and 1993, respectively. He is currently a Senior Researcher with the National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan. His research interests are computer architecture and digital circuits. Dr. Takahashi is a Member of the Institute of Electronics, Information and Communication Engineering and the Information Processing Society of Japan. Yoshihiro Niino was born in Kanagawa, Japan, in He received the B.S. and M.S. degrees in material physics from Osaka University, Osaka, Japan, in He joined the Design and Development Center, Asahi Kasei Microsystems Corporation, Kanagawa, Japan, in Since then, he has been engaged in the research and development of CMOS mixed-signal LSIs. Kaoru Takasuka was born in Hiroshima, Japan, in He received the B.S. and M.S. degrees in instrumentation engineering from the Kyushu Institute of Technology, Kitakyushu, Japan, in 1970 and 1972, respectively. He joined Asahi Kasei in Since 1983, he has been engaged in the design of custom CMOS LSIs. He is currently the Vice President CTO of Asahi Kasei Microsystems, Tokyo, Japan. Mr. Takasuka was a corecipient of the Award for Technical Excellence from the Society of Instrument and Control Engineers of Japan in Yuji Kasai was born in Yamanashi, Japan, in He received the B.Eng. and M.Eng. degrees in materials science from the University of Tsukuba, Tsukuba, Japan, in 1985 and 1987, respectively. He is currently a Senior Researcher with the National Institute of Advanced Industrial Science and Technology, Tsukuba. His research interests are electric circuits and evolvable hardware systems. Mr. Kasai received the Institute of Electrical Engineers of Japan Millennium Best Paper Award. He is a member of the Institute of Electrical Engineers of Japan, the Japan Society of Applied Physics, and the Japan Solar Energy Society. Tetsuya Higuchi received the B.E., M.E., and Ph.D. degrees from Keio University, Kanagawa, Japan, all in electrical engineering. He heads the New Circuits/System Technology group of the MIRAI Project, National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan. His research interests include evolvable hardware systems, parallel processing architecture in artificial intelligence, and adaptive systems. He is also a Professor with the University of Tsukuba. Dr. Higuchi received the Ichimura Award in 1994, the ICES Best Paper Award in 1998, and the Institute of Electrical Engineers of Japan Millennium Best Paper Award in He is a Member of the Japanese Society for Artificial Intelligence.