An Analysis of Interleaved Boost Converter with LC Coupled Enhanced Soft Switching

Transcription

1 American Journal of Applied Sciences, (4): , 3 ISSN: R. Vijayabhasker et al., This open access article is distributed under a Creatie Commons Attribution (CC-BY) 3. license doi:.3844/ajassp Published Online (4) 3 ( An Analysis of Interleaed Boost Conerter with LC Coupled Enhanced Soft Switching Vijayabhasker, R., 3 S. Palaniswami, V. Venkatesa Kumar and M. Newlin Raj Kumar Department of Electronics and Communication Engineering, Department of Computer Science and Engineering, Faculty of Information and Communication Engineering, Anna Uniersity, Regional Centre, Coimbatore, India 3 Electrical Engineering, Faculty of Electrical Engineering, Goernment College of Engineering, Bodinayakkanur, India Receied 3-4-8, Reised 3-4-8; Accepted ABSTRACT An enhanced soft switching technique for an interleaed boost conerter with Zero Current Switching (ZCS) and Zero Voltage Switching (ZVS) during OFF and ON conditions of the main switches, that can drie large loads operated in duty cycle greater than.5 is proposed in this study. In this topology, auxiliary ciuit is composed of resonant tank which is used to decrease the oltage stress on the main switches and a coupling capacitor is added additionally with minimum resonance which in-turn increases the life of operation of the conerter. In this model, faster switching and suitable impedance matching is achieed with reduction in auxiliary ciuit reactance that has contributed much increase in the oerall performance. Coupled inductor in the boosting stage helps higher current sharing between the switches. The oerall ripple and Total harmonics distortions are reduced in this technique without sacrificing the performance and efficiency of the conerter. A simulation module constructed using MATLAB Simulink illustrates the better results of the proposed conerter. Keywords: Interleaed Boost Conerter, Zero Voltage Switching, Zero Current Switching, Duty Cycle. INTRODUCTION The boost conerter is a popular choice for most power electronic systems to sere as a pre-regulator, due to adantages of simplicity and high performance (Pan et al., 9). Howeer, as the power rating increase, it is often required to associate conerters in series or in parallel. In high-power applications, interleaing of two boost conerters is ery often employed to improe performance and to reduce the size (Gallo et al., ). Because interleaing effectiely doubles the switching frequency and also partially cancels the input and output ripples, the size of the energy-storage inductors and differential-mode EMI filter in interleaed implementations can be reduced (Jang and Joanoic, 7). Interleaing reduces the output capacitor ripple current as a function of duty cycle. As the duty cycle approaches, 5 and % duty cycle, the sum of two diode currents approaches dc. At these points, the output capacitor only has to filter the inductor ripple current. It can be shown that by applying different duty cycles to the two phases of an interleaed boost conerter according to oltage- second balance, their oltage gain will be different. The phase with larger duty cycle may hae large oltage gain and operate in Continuous Inductor Current Mode (CICM), while the other will then automatically operate in Discontinuous Inductor Current Mode (DICM). Under this condition, any further additional loading current will be taken up by the phase CICM operation (Wang et al., 8). Hence the analysis of the conerter operated in duty cycle greater than 5% is an efficient approach in interleaed boost conerters. Corresponding Author: Vijayabhasker, R., Department of Electronics and Communication Engineering, Faculty of Information and Communication Engineering, Anna Uniersity, Regional Centre, Coimbatore, India 33

2 The AC mains utility supply ideally is supposed to be cleaned and free from high oltage spikes and current harmonics in order to ensure good quality and efficient power system harmonics to electronics equipment. But in practical condition the ripples are ineitable, which needs to be minimized (Daut et al., 6). Various ongoing reseah proposals are focused with some limitation as follows. To reach the smooth soft switching, the ciuits proposed require more complex auxiliary ciuits which totally increase the conduction loss (Stein et al., ; Hsieh et al., 9). Due to extra inductor, the auxiliary unit is complex, een the main switches are ZCS and the auxiliary switches are ZVS. The main switches are ZCS at the turn-on transition, while in turn off the switching is hard (Stein et al., ). A better soft switching ciuit is proposed, but the conerter works in discontinuous mode with duty cycle less than 5% (Yao et al., 7). Een after analyzing with duty cycle more than 5%, the number of switching phases and switching timing is high due to increased auxiliary resonance and oltage stress to the auxiliary switch (Chen et al., ). The higher switching frequency may cause the higher switching losses, higher Electro-Magnetic Interference (EMI) and the lower oerall efficiency. The use of soft-switching techniques in conerter can contribute to reduce them (Felix and Kumar, ). In this study, a soft switching technique for an interleaed boost conerter with Zero Current Switching (ZCS) and Zero Voltage Switching (ZVS) for the main switches, which is operated in duty cycle greater than 5% with wide range of operating load, is proposed. In this topology, the oltage stress on the main switches is shared by the resonant tank composed of a resonant capacitor and inductor forming an effectie auxiliary ciuit. To increase the durability of the switch used, a coupling capacitor is added additionally with minimum resonance. Faster switching and suitable impedance matching is achieed with reduction in auxiliary ciuit reactance which has increased the oerall performance. Better current sharing between the switches is obtained by coupling the boost inductors. The oerall ripple and Total harmonics distortions are reduced with higher efficiency of the conerter. The forth coming sections will reeal the effectieness of the enhanced conerter.. MATERIALS AND METHODS.. Design and Analysis For the case analysis, the ciuit is analysed in Continuous Conduction Mode (CCM) with arious load ranges haing different duty cycle. The Proposed 33 interleaed Boost Conerter with LC coupled Soft Switching is shown in Fig.. It utilizes the interleaed boost conerter topology and applies enhanced soft switching methodology where the resonant tank itself triggers the switches for extreme condition. The resonant tank is composed of Resonant Capacitor C and Resonant Inductor L which in-turn act as a control ciuit for the auxiliary switch S ax, that is responsible for ZVS and ZCS function... Principle of Operation The ciuit is operated in fundamental mode with duty cycle D which is exact symmetrical in function. The ciuit is analysed with certain assumptions to simplify the ciuit analysis which are listed as: All switches and diodes are assumed to be in practical condition with an exponential decay α in the computation for theoretical analysis Idealizing the input and output reactance The two boost inductors are coupled Same duty cycles (D D ) for the main switches S s and S s The flow of current in initial stages through the boost inductor has an effect of interference which results in addition of ripples. Thus, for the initial input current to be clear from input ripple, a guard is introduced, which is a magnetic couple by a ferrite core which has high permittiity and hence the coupling is more effectie. Boost inductors B L and B L is energized by the magnetic flow across the inductor causing fluctuation in the input current. It is minimized by placing the iron core between the coils which looks like a transformer arrangement. Thus the flow of current is regulated by the magnetic coupling across the inductors. The mutual inductance exerted by both the boost inductor is gien by Equation : L m(ur LL )K () where, µ r and K are Permittiity of the core and coupling co-efficient respectiely. According to the ciuit theory, the coupled inductor can be realized with an uncoupled inductor which needs an additional inductor for coupling. There by Equation and 3: ' L L-L m ()

3 Fig.. Proposed interleaed boost conerter with LC coupled soft switching ' L L-L m (3) ' ' where, L and L are considered to be leakage inductances which has major influence oer the input current ripple. By regulating the coupling coefficient, the amount of ripples in the input current can be controlled. On the other hand, the output from the inductor is gien by the expression which depends only on the leakage inductance Equation 4 and 5: predetermined from the inductor current. Flow of current through the two switches is calculated by the following expressions Equation 7 and 8: (7) in (-D +D r+d )T l s ON s LL l (8) -(D +D +D ) in s ON s r r d L - i o o ' dt L +Lm L dil - dt L +L o ' ' (4) (5) The oerall cycle time is of the inductor output current with or without ripple and it can be expressed in the time of propagation of current in inductor, which is usually specified as a function of line frequency of input (i.e., Indian standards, 5 Hz) Equation 9: The oerall current in the conerter is gien by the Equation (6), which is the hypotenuses cosine function of the capacitance: c + c (6) t6 r sh I K cosh dt csh + c r The significance of the equation is that oerall effectieness of current sharing of the conerter is 333 T.37log t (9) Cycle p In this consideration of the switch S s, the total power applied to the auxiliary switch is gien by the expression (). The resistance in the parasitic (R) elements contributes for the maximum power usage in the switch Equation -: P s(l(t p)) R ()

4 Fig.. Related switches driing signal D>5% p tr I () l(t ) l (t)dt CCs Cr + C ax Vo sinh + tr L r(c+ C c) LrCCax I(t p) dt () ILC ax C + C r + cos t CCax CC r The oerall output current I(t p ) in the conerter is calculated as the integral of inductor current. The current purely depends on the resonant ciuit of the deice in use. It is an ineitable fact that, in practical conditions, it is not possible to produce the duty cycle exactly at 5%., hence the design is analysed for two different modes of operation iz duty cycle (D) lesser and greater than 5%..3. Operational Analysis when Duty Cycle is Greater than 5% In this analysis, there are operational modules which comprise of a complete cycle. Here, analysis is done only on 6 modes which are related to main switch S S. The operating modes of the ciuit for duty cycle greater than 5% is shown in Fig. and 3 shows the related wae forms under same condition. Fig. 4a-f shows the actie stages of the conerter during operation. Stage I [t t ] In this stage, due to the pre-excitation in duty cycle, all the switches (S s, S s, S ax ) are actie and the rectifier 334 diodes D r, D r and clamped diode D r are turned off. Here the main switch current I s and I s are less than preious mode. The main switch S s achiees ZCS at time t t Equation 3: t (D-t 7)T-(D-.5)T (3) Based on the equation at Stage 3 in D<5%. The inductor current between the interals is gien by Equation 4: I (t)i (t )+ L BL a Lin Stage II [t t ] s L C +C ax I (4) Here, the energy stored in the resonant ciuit [L,C ] is transferred to the output load by a clamped diode D r. This happens because auxiliary switch oltage attains zero. The flow of current from resonant ciuit I is equal to the total output current I which is equal to boost inductor current I BL (t) Equation 5: I Cax + C sh Iin cosh CshCax I I (t) K LB L LBL BL (5) The oerall execution of stage is based on the LC resonant that produces damped oscillation in LC network which is supported by an input oltage that makes the system to produce sustained output.

5 Fig. 3. Stages of the switches when it is operated with duty cycle greater than 5% Stage III [t t 3 ] At this stage, the damped diode D r is turned off. The energy stored in boost inductor BL and the parasitic capacitor C s is transferred to resonant ciuit and hence the rectifier diode D r is turned on. When the main switch oltage V s and resonant capacitor C increases to V at t t 3 Equation 6-8: CC C+ C V sin t + L (C+ C ) CC I Lr(t) I C C LC + X cos γ t C+ C LγC (7) t t + t t 3 3 I Lin LB + V π Iin L (Cs + Cs + C ) (6) t 3 π LrC t L (C + C ) (8) The parasitic capacitor C ax of the auxiliary switch is gien linearly by I BL -I to V. 335

6 DS Dr L Sax Ss Ss Ds Dax Ds (a) (b) (c) 336

7 (d) (e) (f) Fig. 4. Operating modules when the duty cycle is greater than 5% (a) Stage I (t-t), (b) Stage II (t-t), (c) Stage III (t-t3), (d) Stage IV (t3-t4), (e) Stage V (t4-t5), (f) Stage VI (t5-t6) 337

8 Stage IV [t 3 -t 4 ] In this stage, at t 4 the clamped diode D r is turned ON. The energy stored is the inductor L is transferred to output V o through clamped diode D r and the Switch S S turn-on has no effect on the main switch S S. In this the time, it is necessary to consider an intermediate time which is gien Equation 9 and : π t34 t 3 + (t ) D (9) π 3 t34 ωd ω π LC π ω D 3 L (Cs + Cs + C c) () So the excitation current I Lin (t n ) is gien is terms of time constrain Equation : I Lin(t) I Lin(t ) L (Cs + Cs + C c) Stage V [t 4 -t 5 ] (t 3 ) iv + 3 I () In this stage, both main and auxiliary switches are turned OFF. The stored energy in LC network is discharged to the load ia D r which is a clamped diode and that will act as a bypass for the current flow. Now the input current charges the parasitic capacitance in the switches. The resonant current continues to increase to the peak alue and the main switch oltage C s decrease to zero, because of the resonance, among elements, turns the switch S S to be in ON condition Equation and 3: L V t5 t3 i (t a) + V z L t t i (t ) a V L (Cs + C ) () (3) At this stage, all the oltages tend to equal. V (t 5 ) V c (t 5 ) V s (t 5 ) V cc (t 5 ) V Equation 4: V (I + i (t))dt (C C C C ) t 7 t Lin L s + s + r + (4) cc 6 Now at the end of this stage, the charged inductor helps the rectifier diode to turn ON. 338 Stage VI [t 5 t 6 ] When the resonant capacitor oltage V cr and the main switch oltage V s are equal to zero, the body diode D S of S S is turned ON. The time should be a fraction of normal operational time of stages. So in this stage one main switch S S achiees ZCS and other Main Switch S S achiees ZVS Equation 5: T (t + t + T ) t V (5) 3 6 LC.4. Voltage Ratio Boost inductor current i BL when switch is actie in duty cycle greater than 5%, where actie stages are (t,t 3,t 45 ) Equation 6-8: in s ONi L (t + t3 + t 45) (6) L in (D '.5D r D )T L + + (7) in (D r D )T L + (8) Boost inductor current i BL when switch is actie in duty cycle greater than 5%, where actie stages are (t, t 34, t 56 ). Total time for switch to be in ON is T-(t +t 34 +t 56 ) Equation 9 and 3: in s OFFi L (T (t + t34 + t 56)) (9) L [V V ] in out s OFFi L ( (Dr + D ))T (3) L in Voltage conersion ratio is gien by Equation 3: Vout V ( (D + D )) r.5. Simulation Design and Analysis.5.. Conerter Specification (3) The switching frequency f s 5 Hz, the output oltage V 44V and the range of output power P out are W-8W. The range of operating oltages 5V-V.

9 .6. Estimation of Boost Inductors and Output Capacitor To support wide range of load a ariable capacitor is used to proide impedance matching between the leels. The range of output capacitance is -7 µf most preferably aboe 4 µf. The boost inductors B L and B L are designed to operate in CCM. The design consideration of the parameters are gien by: Calculation of inductance-duty cycle greater than 5% Equation 3: B B Lmin L (Dr + D )[D (Dr + D ) R max] f µ H s (3) Thus aerage inductance for both the boost inductor is gien by B L and B L iws 3 µh..7. Estimation of Resonant Capacitor and Coupling Capacitor Resonant capacitor plays an important role in all aspects of switching, energy storage, impedance matching and load driing so the design of resonant capacitor enhances the oerall performance of the conerter. The total reactance of the system is the sum of reactance from capacitor and inductor which is equal to the oerall energy stored in the system: Q XL + X where, XL and are reactance of inductor and capacitor x C respectiely. Consider the charge and equialent energy charge per storage in resonant tank. The operating frequency of the tank ciuit is gien by 5Hz, so the calculation of resonant capacitor is obtained from (33) by substituting known alues Equation 33: π L r(cs + CS + Cc + C r) (33) f s By simplification with the known alues of maximum allowed parasitic capacitance in MOSFET switches, the coupling capacitance and resonant capacitance is gien as.5 µf and.5 µf respectiely..8. Estimation of Switching Time Switching time of the conerter is controlled by the resonant and parasitic elements by analyzing those elements which will gie necessary time constraint for soft switching. C 339 Table. Parameters and components of the conerter Input oltage 8-4V Duty cycle >5%, for simulation 6% Output oltage 44V Output current.5a-.45a Output power -8W Switching frequency 5Hz Boost_L &Boost_L 3µH and Ferrite core µ r Output capacitor -7 µf Resonant inductor 5 µf Resonant capacitor.5 pf Coupling capacitor.5 pf.9. Design of Arrial Time of ZVS Condition When time taken by the switch S S to achiee ZVS, the oltage across the soue to drain must be zero. The same is achieed in stage 5 for mode D>5%. The minimum time considered for the arrial of ZVS is gien by. For stage 5 (D > 5%), the calculation of ZVS arrial time is gien as Equation 34: D π L (CS + Cc + C ) > t S µ 785p 97.ns.. Design of Arrial Time of ZCS Condition (34) Time at which the switch S S achiee ZCS is in stage 6 for mode D>5%. The minimum time considered for the arrial of ZCS is gien by the resonant inductor current. In stage 6 (D >5%), the calculation of ZVS arrial time is gien as Equation 35 and 36: V i (t ) I (t ) + 7.5A > I (35) L 6 BL a in Z I o L + V o L (C C C ) π + + S c DS > t5a + ta6 5ns (36) Thus, the design can gie the Maximum Duty time of soft switching condition with the aboe constraints. All the aboe parameter alues are tabulated in Table.

10 .. Parametric Analysis of the Ciuit The interleaing technique in power conertor is simulated with desired specification of ZCS and ZVS. Furthermore for better understanding, Total Harmonic Distortion (THD), the efficiency, operational range, gain, stabilizing the duty cycle and reerse recoery loss are to be calculated. The oerall mathematical analysis is focused on such qualities for easier optimization of the ciuit... Total Harmonic Distortion (THD) In this study, the harmonics of interleaed boost conerter is analyzed from 3rd harmonic to 3th harmonic where the maximum harmonics can be obtained. Basically total harmonics is the Root Mean Square (RMS) alue of the total harmonics of the signal, by the RMS alue of its fundamental signal. Let the Fourier co-efficient are Equation 37: 4E bn cos(na) (37) n π For 3rd harmonic, the change of angle in the wae is gien by a 3 then the harmonic from 3rd is gien by the Mathematical Induction Equation 38: π( π d) 6cos a THD (38) 4cos(a) By changing the Fourier s co-efficient for two switches Equation 39: 4E b n ( cos(na ) + cos(na )) nπ where, n,3,5 THD X(n) a π π + aa ( cos(a ) + cos(a ) ) cos(a ) + cos(a ) By Fourier transform Equation 4: N n + n bncos(πfn) (39) a sin(π fn) + (4) By harmonic on stages of 3, 4, 5, 6, 7 is gien by. The angular change α is gien for harmonics is Equation 4: cos(a ) + cos(a ) + cos(a ) + cos(a 4) 4 cos(5a ) + cos(5a ) + cos(5a ) + cos(5a 4) cos(7a ) + cos(7a ) + cos(7a ) + cos(7a 4) cs(a ) + cos(a ) + cos(a ) + cos(a 4) cos(3a ) + cos(3a ) + cos3(a ) + cos(3a 4) (4) 34 By applying Newton-Raphson iteratie method Equation 4: a 6.6,a 8.9,a 7., 3 a 45.3, a THD π p π p + (i + )a i+ ( CO3(a i ) ) n 4 p CO3(a ) i i (4) On the basic calculation for the iteratie equations, the maximum THD is 7.93%..3. Current Sharing The current sharing in parallel path is a major design problem, which is minimized by using a coupled inductor in input stage. The magnetic interference on the adjacent path couples the flow of current and so the current sharing between the parallel conductors will turn to be effectie. Aerage current that is shared by the switches are equal i.e.,. z out (Dr + D + D r) Thus the current from an inductor B L is controlled by both the inductor, so maximum sharing of current can be easily achieed. This shows that the current flowing through the switches is equal to each other. The ciuit is symmetrical and hence the expressions for the flow of current through the paths are meant to be equal. From the aboe, the aerage Current Shared by Inductors I L and I L is manipulated to be 3.5A..4. Diode Conduction and Reerse Recoery Losses The recoery current in terms of charge and recoery time enable the calculation of the loss are found to be simple Equation 43 and 44: I Q RR RR (43) trr t Q di/dt RR rr (44) Total power loss in conduction of a diode is gien from the RMS alues of the conduction. This loss can only be minimized because there is power dissipation in conduction due to the recombination of electrons Equation 45: P cdb 4* *P * π**v F rms (45)

11 In switching the operation of diode for rectification of input the loss associated with the clamped diode is gien as a function of change in phase angle and with the total charge recoery of the diode Equation 46: P (V, θ ) Q *V *sin θ *f (46) I SDB i rr i Here θ, angle of recoery current Equation 47: P sinθ CS (47) *Vrms Power dissipation for a complete cycle of single stage boosting is gien from the total time (T) to the reerse recoery time (t rr ) Equation 48: V I P cycle *t rr * *trr + I T T (48) From the aboe calculation the total switching loss in a conerter is gien by Equation 49: P f *(V + V )*Q (49) s s ef rr Finally, the reerse recoery loss of oerall system including 8 diodes and 3 switches is.96 Watts which is just.6% of total power. 3. RESULTS AND DISCUSSION The operation of the conerter under the arious load from to 8W with the duty cycle greater than 5% are shown below. Based on the design consideration and required conditions, the proposed interleaed boost conerter with both ZVS and ZCS characteristics is built and it is shown in concerned places with proper indication. The simulated output waeforms (Fig. 5-6) of the proposed ciuit are obtained with an input oltage of 5V and the load current of ~.6A. While erifying the output of both the switches S S and S S, it will be same, as the ciuit is symmetrical. The proposed method has a designed switch with a practical decay constant (α) which is dependent factor on temperature, working life span, range of conductiity and arious physical factors. (a) (b) Fig. 5. Simulation waeforms of the main switches S S, S S (a) (b) ZVS and ZCS operation while operating in duty cycle aboe 5% with load current.55a (a) (b) Fig. 6. Simulation waeforms of the main switches S S, S S (a) (b) ZVS and ZCS operation while operating in duty cycle aboe 5% with load current.45a 34

12 Table. Comparison of arious parameters Yao et al. Proposed Parameters Lee et al. () Stein et al. () (7) Chen et al. () conerter Current Sharing by switches *Not exactly equal *Not exactly equal *Nearly equal *Nearly equal 3.5A (equal) THD % Reerse recoery loss % Time of ZVS *In range of ms *In range of ms *In range of ms ns 97ns Time of ZCS *In range of ms *In range of ms *In range of ms 49 ns 5ns Efficiency 94.% 95.9% 95% 95.5% 97.8% 5. REFERENCES Fig. 7. Efficiency measurement The efficiency measurement for arious loads is shown in Fig. 7, which shows the effectieness of the proposed conerter. Various parameters are tabulated in Table which compares the performance of existing conerters and proposed conerter. The switching timing of the proposed conerter indicates the fast switching transition of the ciuit when compared with existing topologies. Further, the results shows that the proposed conerter can be implemented with better power factor for the practical applications like Solar System, PV Panel, Grid Systems, Green Power System and Semiconductor Industries. 4. CONCLUSION An enhanced soft switching technique for an interleaed boost conerter with Zero Current Switching (ZCS) and Zero Voltage Switching (ZVS) for the main switches operated in duty cycle greater than 5% is proposed in this study. The conerter can drie wide range of load with higher efficiency. From this topology, decreased oltage stress of the main switches, faster switching, suitable impedance matching, better THD, reduced ripples, reduced reerse recoery loss and conduction loss, equal current sharing and better oerall efficiency is achieed, which effectiely reeal the performance of the proposed conerter. 34 Chen, Y.T., S.M. Shiu and R.H. Liang,. Analysis and design of a zero-oltage-switching and zerocurrent-switching interleaed boost conerter. IEEE Trans. Power Electr., 7: DOI:.9/TPEL Daut, I., R. Ali and S. Taib, 6. Design of a singlephase rectifier with improed power factor and low THD using boost conerter technique. Am. J. Applied Sci., 3: Felix, J.X. and S.P. Kumar,. Design and simulation of a soft switched dc boost conerter for switched reluctance motor. Am. J. Applied Sci., 9: Gallo, C.A., F.L. Tofoli and J.A.C. Pinto,. A passie lossless snubber applied to the ac-dc interleaed boost conerter. IEEE Trans. Power Electr., 5: DOI:.9/TPEL Hsieh, Y.C., T.C. Hsueh and H.C. Yen, 9. An interleaed boost conerter with zero-oltage transition. IEEE Trans. Power Electr., 4: DOI:.9/TPEL Jang, Y. and M.M. Joanoic, 7. Interleaed boost conerter with intrinsic oltage-doubler characteristic for uniersal-line PFC front end. IEEE Trans. Power Electr., : DOI:.9/TPEL.7.95 Lee, P.W., Y.S. Lee, D.K.W.Cheng and X.C. Liu,. Steady-state analysis of an interleaed boost conerter with coupled inductors. IEEE Trans. Indus. Electr., 47: DOI:.9/ Pan, C.T., C.M. Lai, M.C. Cheng and L.T. Hsu, 9. A low switch oltage stress interleaed boost conerter for power factor correction. Proceedings of the International Conference on Power Electronics and Drie Systems, No. -5, IEEE Xplore Press, Taipei, pp: DOI:.9/PEDS

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