A Modified Boost Topology to Minimize Distortion in PFC Rectifier. Muhammad Mansoor Khan * and Wu Zhi-Ming *

Transcription

1 A Modified Boost Topology to Minimize Distortion in PFC Rectifier Muhammad Mansoor Khan * and Wu Zhi-Ming * Department of Automation, Shanghai Jiaotong University Shanghai, 00030, P.R. China Abstract The cusp distortion is an inherent behavior of all boost PFC rectifiers. We will propose a new topology to minimize the distortion in boost rectifier. The main characteristic of the proposed topology besides improving the distortion in the boost rectifier is that it provides ZCS/ZVS switching of all components ecept for one hard switching during turn on transient. Furthermore it needs simple output feed bac control and requires fewer components; hence it is also economically feasible. For further verification, a prototype system was also built. 1. INTRODUCTION. Cusp distortion occurs just after the AC line input has crossed zero volts [1,]. At this point the amount of current, which is required by the programming signal eceeds the available current slew rate. When the input voltage is near zero there is very little voltage across the inductor when the switch is closed so the current cannot ramp up very quicly so the available slew rate is too low and the input current will lag behind the desired value for a short period of time. Once the input current matches the programmed value the control loop is bac in operation and the input current will follow the programming signal. The harmonic content of the cusp distortion increases with the value of the inductance used in the boost converter. Natarajan [1] proposed an active shunt filter to obtain the desired objective. The shortcoming of their proposed circuit is the compleity in implementation of etra four switches and need of a comple control algorithm to achieve the control of the system. Tse, and Chow [] have proposed Sheppard-Taylor converter to achieve the distortion-less input current in PFC. In their proposed system the control is simple but all switches in the system are operating under hard switching condition, consequently losses and noise levels are too high. In this paper we will propose a modified boost topology to minimize the cusp distortion. capacitor and utilize this energy near the zero crossing to improve the input current. Fig. 1 shows the proposed boost PFCs. It consists of, the regular boost converter with a snubber capacitor and a buc converter (dotted portion). In this converter, the buc converter in combination with C acts as a snubber when input current is high enough, so that the energy stored in the snubber capacitor during a cycle is only a small fraction of total energy transferred by the inductor L m. When the energy transferred to C m during a cycle is small, the voltages across the capacitor C 1 starts rising and the buc converter acts as an energy converter circuit besides serving as snubber.this is always true when the voltage is getting down in main inductor during the end of an each cycle. The energy stored in C 1 provides etra voltages in addition to V in during the start of each cycle to minimize the cusp distortion. current drawn bac by the buc converter during each cycle the voltage across C are very small. Then the whole circuit serves only as a simple boost converter with a snubber.. AN EXTENDED BOOST TOPOLOGY. In this section we will present an etended boost converter topology to improve the performance near line zero voltage. The basic idea behind this new scheme is to store some energy in an auiliary Fig. 1. Circuit diagram for modified PFC boost converter.

2 When the input voltage and average current in L m during each cycle are much greater than the average The different topologies the circuit attains in this case are shown in Fig.. As shown in Fig. operating stages eist during one switching cycle, which are described as follows. Stage 1 : The active switches are off, and the input current I flows through the output rectifier D 1 and L m D m. During this stage, the resonant capacitors voltages V are clamped at V C..The value of V depends on C the value of V in when V in is high enough, the current drawn by the inductor I is high and the voltages L m across this capacitor are almost zero. (d) (e) (a) (f) (b) (g) (c) (h) Fig.. Different stages of operation of the proposed PFC.

3 Stage t 1, t : At t 1, the auiliary switch Q is turned on under ZCS. The current I increases due to the resonance between L and C. Stage 3 t, t 3 : During this stage, the current L I L in- creases linearly up to I L when the output rectifier m D m is turned off under ZCS and ZVS. Stage 4 t 3, t 4 : The current I L continues to increase due to the resonance between L and C till the voltage V C reaches zero, the diode D 5 turns on. Stage 5 t 4, t 5 : To achieve soft commutation for the main switch, its turn-on signal should be applied while the diode is conducting At t 4, the main switch Q m is turned on under ZCS and ZVS condition. Stage 6 t 5, t 6 : At t 5, the auiliary switch Q turns off under ZCS condition. Simultaneously, the buc converter diode, D b turn on to continue the current ramping downward. The on switching process of the boost stage is completed at this point. The current in the main inductor L m ramps up under the influence of input voltages. The current in auiliary continues. The transient current due to switching action decays and the auiliary inductor try to follow the current in main inductor. Stage 7 t 6, t 7 : The off process starts at t 6. The main switch Q m turns off first in ZVS manner. The current in the main inductor continuous and starts charging the auiliary capacitor Q. Consequently the voltages across Q starts rising. The trend in the auiliary inductor is the same as discussed in stage 6. Stage 8 t 7, : At t= t 7 the voltage across the auiliary capacitor reaches the value of voltage across main capacitor C m. The main diode D m turns on and the turning off process is complete. Notice that all the switching in the circuit operation described in stage 1-8, all the switching are either ZCV or ZVS ecept the first switching in stage 1 where the diode D b turn off under hard switching mode. To overcome this drawbac, a lossless snubber can be inserted in buc converter. Fig. 3. System approimation for deriving buc converter stage model in continuous conduction. The results regarding this modification will be reported in future. 3. MODELING OF PROPOSED PFC CIRCUIT. This section is dedicated for the modeling of the proposed PFC circuit. The basic aim is to derive a simple model to describe the operation of the proposed PFC. In this paper, we will adopt the function-based approach described in [3,4,5] to model the system. To facilitate the modeling, we will consider the switching frequency of the circuit much higher than the line frequency; consequently the input voltage can be considered constant during each cycle. We also considered that the auiliary capacitor C 1 be big enough so that voltage across it can be considered constant during each cycle. Note that if the ESRs of the components in system are very small than these assumption are made without much loss in the accuracy of the circuit model. This is because the major current sources I L, and m IL are continuous at the input end, throughout the cycle, hence the resultant transfer effect of these currents, will be through the average component, as the other components in Fourier series epansion will integrate to zero in C 1. Similar remars also applies for V in. For further simplicity and saving space, instead of deriving the model of whole system, here we will construct the model for buc converter stage considering current in boost stage as rectified AC signal. The operation of the system can be divided in to two regions, continuous conduction mode and discontinuous conduction mode. a) Continuous conduction mode By continuous conduction mode we mean that the current in L is always greater than zero. For PFC, this mode occurs when the input current in L m is high enough to deliver energy more than it reflects bac through the snubber. The approimate model for buc stage of the system is given in Fig. 3. As the auiliary capacitor almost always charges to V c, where V c are much more greater than V, as C 1 >>C, hence, the transfer of energy form C to C 1 is always tae place in very small fraction of one cycle. So we can approimate the input voltage to buc converter by an impulse as shown in Fig. 3. Hence the initial current at the start of each cycle can be written as C IL = I L + V c, (1) L Now the differential equation for the inductor current can be written as dil L = V, () dt where, V represents the average voltage in th cycle across C 1,. Integrating above equation, results in

4 following equation for the evolution of the inductor current. + 1 h IL = I L V, L (3) The equation for incremental and average capacitor voltages are given by +1 h V =V + ( IL -I in), C1 (4) 1 V =V + IL -Iin C 1, (5) where h 1 I L = IL ( ) d h θ θ 0 h 1 I in = Iin ( θ) dθ h 0, (6) Substituting (6) in (5), we have following epression for average voltage across C ; V 1 L in 1 (V C +hi -h I ) = 3 (7) (h +6C L )L Substituting this value of average value in (3) and (4) we have following model for the evolution of voltages across the auiliary capacitor; V h 1 3h = 1- V + h- I L (h +6C1L ) C1 (h +6C1L ) 3 1 3h h- I C1 in (h +6C1L ) + 1-6C1h -3h L +1 = + L (h +6C1L ) (h +6C 1*L ) 3h + I in (h +6C 1*L ) I V I (8) (9) b) Discontinuous conduction mode By discontinuous conduction mode we mean that the current in inductor L becomes zero before the end of each cycle and stays at zero up to the end of the cycle. This happens when the voltages across C are high enough to ramp down the current in (3) before the end of the cycle. Hence the current in L is always zero at the end of the cycle. Consequently current in L is no longer a state variable in sampled data model. Considering the transfer of energy from the auiliary capacitor C during turn off transition to the auiliary capacitor C 1 taing place in a small fraction of duty cycle, we can approimate this transfer to be impulsive. Hence we can write; C VC = V 1 C + V 1 c, (10) C1 Now following will be equation for incremental capacitor voltages; +1 h V =V - Iin, (11) C1 and average voltages will be given by h V =V - Iin. (1) C1 Eample 1. To verify the model proposed in the present section, we used the following system parameters. L m =10mH, L = 150µH, C = 0.1µF, C 1 = 47µF, V c = 400V dc, V in = 0V AC, I in = 8.5sin(π50t). We made the computer simulation and compared them with the numerical simulation through Simulin. The results of this simulation are shown in Fig. 4. It can be observed that the results of model constructed in this section are in good agreement with the numerical simulation performed using SIMULINK. Fig. 4. Comparison of simulation results of the proposed PFC buc converter stage for numerical simulation through SIMULINK and sampled-data model. 4. EXPERIMENTAL RESULTS To verify the PFC rectifier proposed in last section, an eperimental prototype system was constructed. The specifications of the PFC are given in table 1. Notice that the value of the main inductor L m has specially been chosen big enough to cause cusp distortion in conventional PFC boost rectifier. The controller of the system was designed using guidelines in [6]. Following was the transfer function for the controller.

5 ( ) C s 000 = s Table 1 System Parameters V in V c 15 sin(ωt) Volts. 38 Volts. C µf C µf L 150 µh L m 1000 µf h 75 µf (a) Fig. 5. Eperimental results for proposed PFC. (Top) Line current was measured across 0.1-ohm resistance. (bottom) Line voltages Scale =5ms, Channel 100mV/div, Channel 5V/div. (b) Fig. 7. Comparison of line input current of proposed boost PFC and conventional boost PFC. (a) Proposed PFC (b) Conventional boost PFC. Scale X=5 ms. Y= volts/div Fig. 6. Voltage across auiliary capacitor C 1. Scale X=5mS. Y=volts/div. Fig. 8. Voltage across auiliary capacitor C. Scale X=5mS. Y=0volts/div.

6 Fig. 5-Fig. 8 show the results for this eperimental setup. We set the input to follow nominal current 3.sin(ωt) the resultant input current with input voltages are shown in Fig. 5a. Notice that in spite of large value of L m, system is still giving satisfactory performance. The actual and simulated voltages across auiliary capacitor C 1 are shown in Fig. 6. The value for simulated pea capacitor voltages is larger than the actual response Fig. 6b, because we considered zero ESRs for all the components and zero forward voltage drop across diodes. Fig. 7 shows the waveform of proposed converter in comparison with the conventional boost converter for same PI controller. Notice that the conventional boost converter is giving big cusp distortion at the start of the cycle, which later results in ripples in closed loop system and cause further distort the line current waveform. Fig. 8 shows the waveform for voltages across C 1. DC-DC converter system, IEEE IECON 01 Conf. Pro., 001, pp [5] Muhammad Mansoor Khan and Wu Zhi-Ming, Modeling PWM dc-dc converter as discrete input/continuous output system and its application to system local controllability, IEEE IECON 01 Conf. Pro., 001 pp [6] Todd, P., UC3854 controlled power factor correction circuit design, Application, Note U-134, Unitrode Inc., CONCLUSION. Cusp distortion is a common problem in boost rectifier system. Though the harmonic contribution of cusp distortion in not significant, but it imposes constraint on design of the converter and specifically the controller, hence hinders the maimum possible performance of the PFC converter. To minimize the cusp distortion we proposed a new modified boost rectifier system, which minimizes the cusp distortion and at the same time provides ZVS/ZCS switching of the main switch and other switches in the system, hence also reduces high frequency distortion in the system and minimize the noise problem inherent in PWM converter systems. Another feature of the proposed boost rectifier is that it allows simple output feedbac control hence it is compatible to eisting boost PFC controllers. To further evaluate the performance of the proposed PFC a laboratory prototype converter was also built and tested. 6. REFERENCES [1] Natarajan, K, Control of Cusp Distortion in Power Factor Correcting Boost Converter, IEEE CCECE Conference proceedings, 1997, pp [] Tse, C. K., and Chow, M. H. L., New Single-Stage PFC Regulator Using the Sheppard Taylor Topology, IEEE Transactions on Power Electronics, 13/5, 1998, pp [3] Muhammad Mansoor Khan and Wu Zhi-Ming, A functionbased approach for modelling multi-module PWM DC-DC distributed converter systems, International Journal of Electronics, Vol.89/, 00, pp [4] Muhammad Mansoor Khan and Wu Zhi-Ming, A generalized framewor for sampled-data model analysis of closed-loop PWM