Doctoral Thesis. Multilevel Converters: Topologies, Modelling, Space Vector Modulation Techniques and Optimisations

Transcription

1 Doctoral Thesis Multilevel Converters: Topologies, Modelling, Space Vector Modulation Techniques and Optimisations University of Seville Electronic Engineering Department Power Electronics Group Author: José Ignacio León Galván Advisor: Prof. Leopoldo García Franquelo

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3 To my family 3

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5 CONTENTS: 1. Introduction and objectives 1.1. Introduction 1.2. Objectives 2. Multilevel Converter Topologies 2.1. Introduction 2.2. Multilevel Converter Topologies Diode-Clamped Converter (DCC) Advantages and disadvantages of DCC topology Flying Capacitor Converter (FCC) Flying capacitor voltage ratios Advantages and disadvantages of FCC topology Cascaded Converter Different DC voltage source ratios in multilevel cascaded converters Advantages and disadvantages of Cascaded topology 2.3. Converter Connecting Configurations Three-Leg Four-Wire Topologies Three-Leg Four-Wire Topologies Four-Leg Four-Wire Topologies 3. Multilevel Converter Models 3.1. Introduction 3.2. Diode-Clamped Converter Model Three-Leg Three-Wire Diode-Clamped Converter Model Three-Leg Four-Wire Diode-Clamped Converter Model Four-Leg Four-Wire Diode-Clamped Converter Model 3.3. Flying Capacitor Converter Model 5

6 Three-Leg Three-Wire Flying Capacitor Converter Model Three-Leg Four-Wire Flying Capacitor Converter Model Four-Leg Four-Wire Flying Capacitor Converter Model 4. Modulation Techniques for Multilevel Converters 4.1. Introduction 4.2. Classic PWM modulations 4.3. Space Vector PWM Modulation Three-Leg Three-Wire Topologies Three-Leg Four-Wire Topologies Four-Leg Four-Wire Topologies 5. Solving the balancing of the DC-Link capacitors in Multilevel Converters 5.1. Introduction 5.2. Quasi-solution of the balancing problem 5.3. Balancing problem depending on the converter topology Diode-Clamped Converter Topology N-level Three-Leg Three-Wire Diode-Clamped Converter Topology N-level Four-Leg Four-Wire Diode-Clamped Converter Topology N-level Three-Leg Four-Wire Diode-Clamped Converter Topology Flying Capacitor Converter Topology 5.4. Controllability limits 6. Contributions and General Conclusions 7. Future works 8. Publications derived from the thesis work 9. References 10. Acknowledgments 6

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8 Chapter 1 Introduction and Objectives 1.1 Introduction The Electronic Engineering Department at University of Seville has been involved in multilevel converter topics during last 10 years. The research has been focused on the development of new modulation strategies and new control strategies [1]-[4]. The performance of this thesis has been the pinnacle of this research and it would be the base for future multilevel converters research in our department. 8

9 1.2 Objectives The objectives in this thesis have been focused on improvements on multilevel converter features. The first objective is centered on minimizing the computational cost of the modulation strategy. In this thesis, the design of simple and fast Space Vector Modulation (SVPWM) techniques reducing the computational cost for different multilevel converter topologies is the first aim. On the other hand, multilevel converters present problems to achieve the balance of DC capacitors. The second objective of this thesis is the development of simple and low-cost control strategies to get voltage balance based on the use of redundant vectors using proposed SVPWM strategies. These control algorithms should be completely generalized and they could be applied to different multilevel converter topologies and for any number of levels. 9

10 Chapter 2 Multilevel Converter Topologies 2.1 Introduction This thesis is focused on the development of different modulation techniques and several optimisations to improve some specific characteristics of multilevel converters. But, in order to make the text understandable, it is necessary to make a brief overview of the most common multilevel converter topologies introducing the used nomenclature and the operation basis of this type of converters. So, this chapter is dedicated to introduce the way of switching for multilevel converters and to show the possible output voltages that can be achieved depending on the choosing converter topology. Multilevel converters present great advantages compared with typical and very well known two-level converters [5][6]. These advantages are fundamentally 10

11 focused on improvements in the output signals quality and a nominal power increase in the converter. These properties make multilevel converters very attractive to the industry and nowadays, researchers all over the world are spending great efforts trying to improve multilevel converters performance as the control simplification and the performance of different optimisation algorithms in order to enhance the Total Harmonic Distortion (THD) of the output signals, the balancing of the DC capacitors voltage, the ripple of the load currents,, etc. For instance, nowadays researchers are centered on the harmonic elimination using pre-calculated switching functions [7]-[11], the development of new multilevel converter topologies (hybrids or new ones) and the development of new control strategies. This thesis is not focused on the harmonic elimination topic and the control strategies for the complete system are not discussed. New topologies are not presented in this thesis but using common multilevel converter topologies, new voltage strategies are proposed. 2.2 Multilevel Converter Topologies In order to facilitate the understanding of the text, it is going to be presented the state-of-art of the different multilevel converter topologies. Although there are a large number of multilevel converter topologies in the literature, in this chapter the most common topologies will be presented. The most typical multilevel converter topologies are: Diode-Clamped Converter (DCC), Flying Capacitor Converter (FCC), and Cascaded Converter. Several surveys of multilevel converters have been published to present these topologies [12]-[19]. 11

12 2.2.1 Diode-Clamped Converter (DCC) In 1980s, power electronics concerns were focused on the converters power increase (increasing voltage or current). In fact, Current Source Inverters were the main focus for researchers in order to increase the current. However, other authors began to work on the idea of increasing the voltage instead the current. In order to achieve this objective, authors were developing new converter topologies. In 1981, A. Nabae, I. Takahashi and H. Akagi presented a new neutral-point-clamped PWM inverter (NPC-PWM) [20]. This converter was based on a modification of the classic two-level converter topology. In conventional two-level case (see Figure 2.1), each transistor must have at the most a voltage stress equal to V DC and they should be dimensioned to tolerate this voltage. Figure 2.1. Two-level conventional converter The proposed modification to get the three-level converter added two new transistors per phase (see Figure 2.2). Using this new topology, each transistor tolerates at the most a voltage equal to V DC /2. So, if these new transistors have 12

13 the same characteristics than the transistors in two-level case, the DC-Link voltage can be doubled achieving a value equal to 2V DC. But, this converter topology still has a problem. If transistors S 1 and S 2 are switched on and transistors S 3 and S 4 are switched off, V DC voltage should be equally shared between transistors S 3 and S 4. But, there is not any mechanism that assures it. The solution of this problem appears thanks to use the clamping diodes. In each phase, two diodes clamp each transistor voltage. Finally, in Figure 2.2, a three-level Diode Clamped Converter (DCC) is shown. In this converter topology, the DC-Link voltage is equally shared between capacitors C 1 and C 2. Figure 2.2. Three-level Diode-Clamped Converter It can be explained why this converter is named three-level converter. In order to show it, possible switching configurations of this converter topology can be presented. There are only three possible switching configurations in the threelevel DCC. Other switching possibilities are not allowed because they create 13

14 short-circuit in some DC-Link capacitor or they let the output opened. For instance, if S 1, S 2 and S 3 are switched on, a short-circuit is created in capacitor C 2. Besides, the voltage in transistor S 4 is V DC being its maximum admissible voltage equal to V DC /2. The possible switching configurations are shown in TABLE 2.I. Only three possible output phase voltages with respect to 0 (middle point of the DC-Link) appear using this converter and this is the reason to name this converter as a three-level converter. S 1 S 2 S 3 S 4 Phase-0 voltage ON ON OFF OFF V DC /2 OFF ON ON OFF 0 OFF OFF ON ON -V DC /2 TABLE 2.I. Possible switching configurations in a three-level DCC After introducing the three-level DCC topology, it can be extended trying to achieve more levels in the output phase voltages with respect to 0 [21]. In order to show it, a phase of a five-level DCC is represented in Figure 2.3. Now, using this configuration there are more possible switching configurations and they can be seen in TABLE 2.II. S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 Phase-0 voltage ON ON ON ON OFF OFF OFF OFF V DC /2 OFF ON ON ON ON OFF OFF OFF V DC /4 OFF OFF ON ON ON ON OFF OFF 0 OFF OFF OFF ON ON ON ON OFF -V DC /4 OFF OFF OFF OFF ON ON ON ON -V DC /2 TABLE 2.II. Possible switching configurations in a five-level DCC 14

15 Figure 2.3. Single phase Five-level Diode-Clamped Converter In general, for N-level DCC topology all the possible switching configurations have N-1 adjacent transistors switched on in each phase and the possible output phase voltages with respect to 0 take N discrete values in equally spaced out in the voltage range {-V DC /2, V DC /2}. 15

16 Advantages and disadvantages of FCC topology The main advantages of the DCC topology are: The number of capacitors is low compared with other topologies as the flying capacitor converter. This fact is very important due to the cost of these reactive devices. This topology does not require any transformer There is only one DC-Link bus The change between adjacent states is done changing only the state of two transistors. The main drawbacks of DCC topology are: The possibilities to control the balance of the DC-Link capacitors voltage are limited. In fact, other topologies as the Flying Capacitor topology present more possibilities to achieve the balance. This type of converter is still not a final product of companies as ABB, Semikron,, etc. Therefore, all the actual converters are homemade custom design prototypes. DCC topology has become very popular between researchers all over the world and other hybrid topologies have been developed trying to improve the converter features [22]-[24] Flying Capacitor Converter (FCC) Multilevel Flying Capacitor Converter (FCC) topology has been recently introduced and it present advantages and disadvantages compared with other multilevel topologies [25][26]. FCC topology uses several floating capacitors in each phase that connect several points in the converter to achieve different voltage levels in the output signals. This topology presents the floating capacitors instead the clamped diodes of DCC topology. In Figure 2.4, a conventional threephase three-level FCC is shown. 16

17 Figure 2.4. Conventional three-phase three-level Flying Capacitor Converter The topology can be extended trying to achieve more levels in the output phase voltages with respect to 0. In order to show it, a phase of an extended FCC is represented in Figure 2.5. All the switching configurations in FCC can be studied using a systematic method. There is not a complete freedom in the transistors switching in each phase. In fact, each transistor can be associated with other transistor in the same phase forming different couples and only one of the transistors in each couple can be switched on at the same time. Each transistors couple forms one basic cell of the converter. If both transistors were switched on at the same instant, a short-circuit would be created in the flying capacitor of the basic cell. Multilevel FCC topology can be represented in a different way showing that the converter can be built connecting several basic cells in series. An M-cell single-phase FCC is achieved thanks to M basic cells connected in series [26]. A FCC basic cell and the M-cell single phase FCC topology are shown in Figure 2.6 and Figure 2.7 respectively. 17

18 18 Figure 2.5. Phase of an extended Flying Capacitor Converter

19 Figure 2.6. Basic flying capacitor cell Figure 2.7. M-cell Flying Capacitor Converter Topology The switching configurations study can be done defining each transistor couple state in a basic cell as a binary value specifying if the couple state is low (the lowest transistor of the basic cell is switched on) or high (the highest transistor of the basic cell is switched on). So, for a single phase x M-cell FCC, binary factors H xi can be defined as follows: 19

20 0, Sxi = OFF Hxi = with i= 1,..., M 1, Sxi = ON (2.1) So, in general, for M-cell FCC case, there are 2 M-1 possible switching configurations where H xi with i=1,, M marks the state of each transistors couple in the basic cell i in the single phase x [27] Flying capacitor voltage ratios In general, for multilevel FCC, several flying capacitor voltages V x1 :V x2 :V x3 :..:V x(m-1) can be considered [27]. The first presented FCC topology had floating capacitors voltage ratios equal to M-1:..:2:1 (named in this work OFBCS voltage ratio). A four-cell single phase FCC using OFBCS voltage ratio is shown in Figure 2.8 in order to show the ratio performance. Figure 2.8. Four-cell single phase FCC using OFBCS voltage ratio 20

21 Using this voltages ratio, there are only four possible switching configurations in each phase for two-cell single phase FCC and they are shown in TABLE 2.III using basic cells binary values H xi. Other possibilities are not allowed because they create short-circuit in some capacitor or they let the output opened. It is important to say that two different switching configurations achieve the same output phase voltage with respect to 0. This is very important because this type of converter has redundant switching configurations. It will be shown later that this property can be used to improve the floating capacitors voltage control. From TABLE 2.III it can be concluded that two-cell single phase FCC is a three-level single phase FCC with one redundant switching configuration. The state of each phase is denoted by an integer number where 0 means that the output V xo voltage is the minimum voltage possible. S X1 S X2 H X1 H X2 Phase x -0 Phase x voltage State ON ON 1 1 V DC /2 2 ON OFF OFF ON OFF OFF 0 0 -V DC /2 0 Redundant switching configurations TABLE 2.III. Possible switching configurations in two-cell single phase FCC using OFBCS voltages ratio The same calculations can be done using the four-cell single phase FCC topology with OFBCS voltages ratio. In this case, there are more possible switching configurations and they are shown in TABLE 2.IV. The calculation results show that this topology achieves five different output voltage levels presenting several redundant switching configurations. Using OFBCS voltages ratio, the number of 21

22 output levels (N) is the number of basic cells (M) plus one. In general, there is an easy way to calculate the output phase voltage with respect to 0 thanks to the couples binary values using OFBCS voltages ratio. Phase _ State= H x i= 1 VDC V Vout = Phasex _ State M 2 M xi DC (2.2) H X1 H X2 H X3 H X4 Phase x -0 voltage Phase x _State V DC / V DC / V DC / V DC / V DC / V DC / V DC / V DC / V DC / V DC /2 4 TABLE 2.IV. Possible switching configurations in four-cell single phase FCC using OFBCS voltages ratio 22

23 It can be seen from TABLE 2.III and TABLE 2.IV that increasing the number of cells of the converter, the switching configurations redundancy increases. This redundancy implies that the same output phase voltage can be achieved thanks to different switching configurations. This property does not appear in DCC and in chapter 5 it will be shown that it introduces some control advantages. However, it should not be forgotten that the control complexity increases with the number of FCC cells because there will be more redundant switching configurations. In [27] new flying capacitors voltage ratios were presented in order to achieve more output voltage levels with the same number of power devices. In [27][28], the comparison between these voltage ratios was presented using the Full Binary Combination Schema (FBCS) concept demonstrating that, with the same number of power devices, the number of levels in the output voltages changes depending on the voltage ratios used in FCC. Several voltage ratios generate higher number of levels compared with OFBCS. Therefore, at first sight, they improve the behaviour of the converter because they achieve better output signals quality with the same cost. However, all these possible configurations achieve phase to middle point of the DC-Link output voltage signals in the range {-V DC /2,V DC /2}. These voltage ratios consider that the flying capacitors voltages have the same polarity. All the flying capacitors are charged with the desired voltage in the same sense. A new voltage ratio is presented considering OFBCS voltage ratios but doing that flying capacitors voltages can be positive or negative. In the proposed voltage ratio, the sign of flying capacitor voltages (V xi ) is alternatively positive and negative considering positive the DC-Link voltage. This proposed voltage ratio is named New FBCS (NFBCS). In Figure 2.9, a FCC performed with four basic cells using NFBCS is shown. 23

24 Figure 2.9. Four-cell single phase FCC using NFBCS voltages ratio Using this voltage configuration, the output phase to middle point of DC-Link voltage (V x0 ) can be calculated. In TABLE 2.V, the results using OFBCS and NFBCS voltage ratios are shown. It can be seen that with the same number of devices (only with 4 basic cells), OFBCS achieves five output levels and NFBCS achieves 15 levels. So, it is clear that using this new voltages ratio, with the same number of power devices, the number of output voltage levels increases. Other important result can be concluded from TABLE 2.V. Using OFBCS, output V x0 voltages are located in the range {-V DC /2, V DC /2} where V DC is the DC-Link voltage. However, using NFBCS voltages ratio the output voltages are in the range {-2V DC, 2V DC } with the same DC-Link voltage. Therefore, two clear advantages appear using NFBCS voltage ratio. In general, for a M-cell FCC using OFBCS voltages ratio, the number of output levels is N=M+1. However, using NFBCS the number of levels increases exponentially. In Figure 2.10, the number of output levels achieved by both voltage ratios is represented in order to show the increase of levels using NFBCS voltages ratio. 24

25 Switching Configuration H X1 H X2 H X3 H X4 Output Phase x -middle point of DC-Link OFBCS Voltage/V DC NFBCS /2-1/ /4-3/ /4 1/ /4-7/ /4-5/ /4 5/ /4 7/ /4-1/ /4 3/ /4 1/2 TABLE 2.V. Output voltages for four-cell FCC using OFBCS and NFBCS voltages ratios 25

26 Figure Number of levels achieved by OFBCS and NFBCS voltages ratios depending of the number of FCC basic cells Output voltages V x0 range also depends on the chosen voltages ratio. Using OFBCS, V x0 is always in the range {-V DC /2, +V DC /2} and this range does not depend on the number of basic cells in FCC. However, using NFBCS the output voltage range increases. In Figure 2.11, the output voltage range depending on the used voltages ratios is represented showing the increase depending on the number of basic cells in the FCC. Previously, the advantages using NFBCS in FCC have been shown. However, some possible drawbacks appear using this new voltages ratio. Changing the sign of flying capacitor voltages, the power semiconductors of the converter should be chosen very carefully. Using OFBCS, each power device must support a maximum voltage equal to V DC /M where M is the number of basic cells in the FCC. But using NFBCS voltage ratio, each power device must support higher voltages and due to this fact, the specifications of each power device must be chosen in order to support this voltage. For an M-cell FCC using NFBCS, the maximum voltage that each power device must support is (2M-1)V DC /M. This problem also appears using other previously published voltage ratios [28]. 26

27 Figure Maximum output voltage obtained by OFBCS and NFBCS voltage ratios depending of the number of FCC basic cells On the other hand, the topology of power devices using NFBCS voltages ratio must be different because they must be bidirectional. Actually these bidirectional power devices are used in other converter topologies as matrix converters and they can be found easily in the market [29]. These bidirectional power devices use to be diode bridges or back-to-back switches. The diagram of a back-to-back switch is shown in Figure 2.12 and it is built using a module of two reverse blocking IGBTs. This module controls the current flow within each switch. These power devices are actually well extended and for instance, bidirectional power devices are performed by Dynex Semiconductors, Semelab or EUPEC. 27

28 Figure Back-to-back bidirectional switch As it was shown before, using NFBCS voltages ratio it is achieved a higher number of output voltage levels (see TABLE 2.V). However, these output voltage levels are not equally spaced out. This can lead to an increase in the ripple in the output voltage signals due to the fact that there are different voltage steps between the possible output voltage levels. In order to minimize this problem, other voltage ratios can be taken into account. It can be considered a new voltages ratio similar to NFBCS but doing all the flying capacitors voltages equal to V DC /M where M is the number of basic cells of the FCC. This new ratio is named NEFBCS. In Figure 2.13, a four-cell FCC using NEFBCS voltages ratio is shown. All possible output V x0 voltages can be easily determined and they are shown in TABLE 2.VI. From TABLE 2.VI, it can be seen that output voltage levels are equally spaced out and all the voltage steps are equal to V DC /M. However, NEFBCS ratio makes smaller the output voltage range. In general, for a M-Cell FCC the output voltage range is {(-3/2+1/M)V DC,(-3/2+1/M)V DC }. So, it can be seen that increasing the number of basic cells, the maximum output voltage using NEFBCS is smaller than the obtained using NFBCS. Besides, the number of output voltage levels depends on the chosen voltages ratio. Figure 2.14 and Figure 2.15 show a comparison between OFBCS, NFBCS and NEFBCS voltages ratios. 28

29 Switching Configuration S x1 S x2 S x3 S x4 Output Phase-middle point of DC-Link Voltage/V DC NFBCS NEFBCS /2-1/ /4-3/ / / / / / /4-3/ /4 3/ / / / / / /4 3/ /2 1/2 TABLE 2.VI. Output voltages V X0 in four-cell FCC using NFBCS and NEFBCS voltages ratios 29

30 Figure Four-cell single phase FCC using NEFBCS voltages ratio Figure Maximum output voltage depending on the number of basic cells in FCC using different flying capacitor voltage ratios 30

31 Figure Number of output voltage levels depending on the number of basic cells in the FCC using different flying capacitor voltage ratios As conclusions, new flying capacitor voltages ratios using the Full Binary Combination Schema (FBCS) have been studied in order to improve the output signals features for multilevel FCC. These voltage ratios use positive and negative flying capacitor voltages. The results show that an increase in the output voltages range and an increase in the number of levels of the converter is achieved with the same number of power devices and with the same DC-Link capacitors voltage. Therefore, to obtain the same maximum output voltage, the DC-Link capacitors voltage can be reduced and the power devices can have lower voltage requirements. Besides, discussions about the physical implementation and possible drawbacks of these voltage ratios have been introduced. 31

32 Advantages and disadvantages of FCC topology Finally, the main advantages of the FCC topology are: This topology presents more possibilities to control the DC-Link capacitors voltage compared with other multilevel topologies using the redundant switching configurations. This topology does not require any transformer The main drawbacks of FCC topology are: The number of capacitors is high compared with other topologies as the diode clamped converter. This fact is very important due to the cost of these reactive devices. The change between adjacent states is done changing the states of one several transistors. This fact increases the number of commutations in the transistors and the power losses in the converter. The clamping capacitors must be set up with the required voltage levels. So, there is necessary an initialization of the converter. This type of converter is still not a final product of companies as ABB, Semikron,, etc. Therefore, all the actual converters are homemade custom design prototypes Cascaded Converter The cascaded converter or full-bridge converter is formed by two single-phase inverters with independent voltage sources [30]. In Figure 2.16, a phase of a three-level cascaded converter is shown. 32

33 Figure Phase of the three-level cascaded converter Considering the three-level basic cell, it is clear that only one transistor of each leg (S 1 -S 1, S 2 -S 2 ) can be switched on at the same time. In order to facilitate the notation of the possible switching configurations, for each basic cell in phase x, binary factors H xi can be defined as follows: H xi 0, = 1, S = ON and S = OFF xi' S = OFF and S = ON xi' xi xi (2.3) So, using this binary notation, the possible switching configurations of the threelevel basic cell are shown in TABLE 2.VII. 33

34 H X1 H X2 V AB V DC 1 0 V DC TABLE 2.VII. Possible switching configurations in a three-level cascaded converter using the binary notation This three-level converter is the basic cell that is used to build multilevel cascaded converters. A multilevel cascaded converter is easily built connecting basic three-level cells in series. For instance, the two basic cells cascaded converter is shown in Figure It is important to notice that each basic cell needs an independent voltage source and this is one of the most important drawbacks of this multilevel converter topology. Figure Two basic cells cascaded converter 34

35 Different DC voltage source ratios in multilevel cascaded converters The cascaded converter topology has the same property than FCC topology. Different DC voltage source ratios can be applied in order to achieve different voltage levels in the output signals [31]. The classic cascaded converter assumes that all the DC voltage sources have exactly the same value. Assuming conventional voltage sources ratio and considering the two basic cells cascaded converter, the possible switching configurations are shown in TABLE 2.VIII. The phase state can be defined as the voltage level achieved by the converter where 0 means the lowest voltage level. This converter achieves five possible output voltages and, therefore it is a five-level converter. Analytically, it is easy to know the output phase-to-neutral voltage and the phase state defining the FC xi parameter for M-cell cascaded converter as: 0, Hxi = Hxi ( + 1) FCxi = 1, Hxi = 0 and Hxi ( + 1) = 1 with i = 1,..., M 1, Hxi = 1 and Hxi ( + 1) = 0 (2.4) And finally, the phase state and the output phase-to-neutral voltages can be determined using the FC xi parameter as follows: 35

36 Phase _ State= M FC x i= 1 V = V Phase _ State MV = V FC xn DC x DC DC xi i= 1 M xi M (2.5) Cell 1 Cell 2 H X1 H X2 H X3 H X4 V xn voltage Phase x _State V DC V DC V DC V DC V DC V DC V DC V DC V DC V DC TABLE 2.VIII. Output voltages for a two basic cells cascaded converter using classic voltage ratio (all DC voltage sources have the same value) 36

37 Using classic voltage sources ratio, a diagram of the necessary basic cells to obtain multilevel cascaded converters is shown in Figure The number of three-level basic cells to build a N-level cascaded converter is (N-1)/2 with N odd. Figure Diagram of the necessary basic three-level cells to obtain different multilevel single-phase cascaded converters 37

38 Other DC voltage sources ratios can be taken into account [31]. A generalized study can be done for the two basic cells single phase cascaded converter. In this case, the possible output phase-to-neutral voltages can be calculated and they are shown in TABLE 2.IX. Cell 1 Cell 2 H X1 H X2 H X3 H X4 V xn voltage V DC V DC V DC V DC1 + V DC V DC1 - V DC V DC V DC V DC2 - V DC V DC1 -V DC V DC V DC V DC TABLE 2.IX. Generalized output phase-to-neutral voltages for a two basic cells single phase cascaded converter 38

39 So, depending on the DC voltage sources values, different number of levels can be obtained in the output voltages. For instance, if V DC2 is three times V DC1, nine different levels appear in the output voltages. It can be seen in TABLE 2.X. Cell 1 Cell 2 H X1 H X2 H X3 H X4 V xn voltage Phase x _State V DC V DC V DC V DC V DC V DC V DC V DC V DC V DC V DC V DC TABLE 2.X. Output phase-to-neutral voltages for a two basic cells single phase cascaded converter considering V DC2 =3V DC1 39

40 It is important to notice that depending on the chosen DC voltage sources ratio, the number of output voltage levels change. Besides, the switching configurations redundancy also depends on the DC voltage sources ratio. So, the cascaded converter topology behavior is similar to FCC topology because both converter topologies can apply different voltage ratios depending on the needed industrial application Advantages and disadvantages of cascaded converter topology The main advantages of the Cascaded Converter topology are: This topology is based on basic cells (full-bridge converters) connected each other. So, its modularity is important and the controller can be distributed. This makes for a simpler controller structure than for either of the two previously discussed topologies. This type of converters is a final product of companies as ABB, Semikron,, etc. Therefore, the cost of using this type of converters is lower because other topologies are completely custom made. The main drawback of Cascaded Converter topology is: This topology has not been applied at low power levels to date because of the need to provide separate isolated DC supplies for each full-bridge converter element. 40

41 2.3 Converter Connecting Configurations Three-Leg Three-Wire Topologies In previous points of this chapter, the most common multilevel converter topologies have been presented showing all possible switching configurations in each converter phase. In the same way, Three-phase systems can be developed thanks to use three single phase converters. Three-leg three-wire (3L3W) converter topologies are defined as three-phase converters connected to a threephase load with the neutral point of the load unconnected. For instance, a 3L3W three-level diode-clamped converter is shown in Figure Figure L3W three-level Diode-clamped converter 41

42 2.3.2 Three-Leg Four-Wire Topologies A new topology appears if the neutral point of the load is connected to the middle point of the DC-Link bus. This connection changes the operation conditions due to the fact that in this case the sum of the phase currents would not be zero. These converters are named Three-Leg Four-Wire (3L4W) Converters. As an example, a 3L4W three-level diode-clamped converter is shown in Figure Figure L4W three-level DCC 42

43 2.3.3 Four-Leg Four-Wire Topologies A new topology can be developed connecting the neutral point of the load to a new phase of the converter (the fourth leg). These converters are named Four- Leg Four-Wire (4L4W) Converters. In this case, as in 3L4W case, it is clear that the sum of the phase currents would not be zero. But now, there are several possibilities to connect the neutral point of the load depending on the switching configuration of the fourth leg. As an example, a 4L4W two-level conventional converter is shown in Figure Figure Four-Leg Four-Wire two-level conventional converter 43

44 Chapter 3 Multilevel Converter Models 3.1 Introduction It is very important to develop mathematical models for multilevel converters to carry out simulations to find out the system response to different control strategies. In fact, the first step of the implementation of a control algorithm is to simulate it and to see if the simulation results are satisfactory. In this thesis, several multilevel converters analytical models have been developed. These models are built thanks to commutation models and the definition of the switching functions that will be presented in this chapter. The simulation models were developed using MatLab/Simulink software helping to the performance of the control algorithms presented in this thesis. All mathematical models are based on the determination of state equations for dynamical variables introduced in [1]. These models are conspicuous by their extreme simplicity in front of other previous analytical models presented in the literature [32]-[36]. 44

45 In order to introduce the commutation model of a multilevel converter, a phase of the very well known conventional two-level converter is shown in Figure 3.1. Figure 3.1. Phase of the conventional two-level converter In this converter, only one of the transistors can be switched on at the same time. If S 1 transistor is switched on, the output phase voltage with respect to the reference (see figure 3.1) is V DC /2 and if S 2 transistor is switched on, the output phase voltage with respect to the reference is -V DC /2. In order to simplify the circuit, it is possible to replace the phase using an ideal switch that connects the output to the possible voltage connection points of the system. The switching functions are defined as S ij where i is the phase and j is the point where the phase i output is connected (it is supposed that 0 is the lowest voltage connection value). The switching function S ij is equal to 1 if the phase i is connected to the voltage connection point j and 0 if the phase i is connected to other voltage connection point. The simplification of the two level single phase converter can be seen in Figure

46 Figure 3.2. Phase of the conventional two-level converter using an ideal switch This type of commutation model using switching functions simplifies the graphical display of multilevel converters and is completely generalized because any type of transistors can be considered in the system. In this way, the study of multilevel converters is completely generalized obtaining the simulation results using ideal switches. Some transistors real effects as the turn-on time, turn-off time, internal resistance, internal losses,, etc, are neglected. However, the main advantage of this type of commutation model is its simplicity and its easy implementation in simulation softwares in order to study complex systems as multilevel converters. The implemented analytical models need the state equations for the DC capacitors voltages and the phase currents. This chapter is focused on the determination of these state equations depending on the multilevel converter topology. Using matrix notation, the state equations can be described as follows. dw dt Jx1 = A W + B V (3.1) JxJ Jx1 Jx1 DC 46

47 3.2 Diode-Clamped Converter (DCC) Model Three-Leg Three-Wire Diode-Clamped Converter (3L3W-DCC) Model Figure 3.3 shows the commutation model of a three-phase 3L3W three-level DCC. As a three level converter, it can be seen that each phase can be connected to level 0, 1 or 2. The mathematical model uses the switching functions S ij for i Є {a,b,c} and j Є {0,1,2}. Figure 3.3. Commutation model of three-level Diode-Clamped Converter 3L3W Three-level DCC can be easily extended increasing the number of levels. The commutation model of the 3L3W N-level DCC is shown in Figure 3.4. In the N-level case, the mathematical model uses switching functions S ij where i Є {a,b,c} and j Є {0,1,, N-1}. 47

48 Figure 3.4. Commutation model of N-level Diode-Clamped Converter All developed mathematical models are calculated assuming that multilevel converters are connected to three-phase RL loads. The N-level DCC connected to this load is represented in Figure

49 Figure 3.5. Commutation model of a three-level 3L3W Diode-Clamped Converter connected to a RL load In general for N-level DCC, the currents that flow through the DC-Link capacitors can be determined using the switching functions. dv N 2 N 3 N i = C = F F F... F... F F F C N 1 N 4 N 3 N 2 dt N 1 N 1 N N 1 N 1 N 1 dv 1 N 3 N i = C = F F F... F... F F F C N 1 N 4 N 3 N 2 dt N 1 N 1 N N 1 N 1 N 1 dvc3 1 2 N i3= C3 = F1+ F2 F3... F... F F F dt N 1 N 1 N 1 2 N 1 N 1 N 1 N 1 N 4 N 3 N 2 2 dv i = C = F+ F + F... F... F F F C N 1 N 4 N 3 N 2 dt N 1 N 1 N N 1 N 1 N 1 dv N 4 N 3 N 2 i = C = F+ F + F + + F + + F + F N F CN ( 1) N 1 N N 1... N 4 N 3 dt N 1 N 1 N N 1 N N (3.2) 49

50 where ( ) F = Si + Si + Si (3.3) i ai a bi b ci c And finally, the state equations of the DC-Link capacitors voltages are presented. dv dv dt C1 dv dt C2 dv dt C3 dv dt C4 CN ( 1) dt 1 1 = ff ff ff... F... gf gf gf C N 1 3 N 4 2 N 3 1 N = gf ff ff... F... gf gf gf C N 1 3 N 4 2 N 3 1 N = gf + gf ff... F... gf gf gf C N 1 3 N 4 2 N 3 1 N = gf + gf + gf... F C... gf gf gf N 1 3 N 4 2 N 3 1 N = gf + gf + gf F ff + ff ff C N 1 3 N 4 2 N 3 1 N 2 N (3.4) where N 1 i fi = N 1 i gi = N 1 (3.5) In order to determine the state equations for the phase currents, the output phase voltages with respect to 0 (lowest point of the DC-Link) are calculated as follows. 50

51 V = S V + S ( V + V ) + S ( V + V + V ) a0 a1 C1 a2 C1 C2 a3 C1 C2 C a SaN ( 2) ( VC1 VC2... VCN ( 2) ) SaN ( 1) VDC L dt di V = S V + S ( V + V ) + S ( V + V + V ) b0 b1 C1 b2 C1 C2 b3 C1 C2 C b SbN ( 2) ( VC1 VC2... VCN ( 2) ) SbN ( 1) VDC L dt di (3.6) V = S V + S ( V c0 c1 C1 c2 + V ) + S ( V + V + V ) C1 C2 c3 C1 C2 C c ScN ( 2) ( VC1 VC2... VCN ( 2) ) ScN ( 1) VDC L dt di 3L3W topology fulfils that the voltage of the neutral point of the load with respect to 0 is determined as follows. V N0 = V + V + V 3 a0 b0 c0 (3.7) The phase voltages with respect to the neutral point of the load are determined. V = V V = Ri an a0 N0 a a V = V V = Ri bn b0 N0 b b V = V V = Ri cn c0 N0 c c (3.8) And finally, the phase currents state equations are presented. 51

52 dia Ra VC1 = ia+ 2( Sa SaN ( 2) ) ( Sb SbN ( 2) ) ( Sc ScN ( 2) ) + dt L 3L VC2 + 2( S + + a2... SaN ( 2) ) ( Sb SbN ( 2) ) ( Sc ScN ( 2) ) + 3L VC3 + 2( Sa SaN ( 2) ) ( Sb SbN ( 2) ) ( Sc ScN ( 2 3L )) VCN ( 2) + (2 SaN ( 2) SbN ( 2) ScN ( 2) ) + 3L VDC + (2 SaN ( 1) SbN ( 1) ScN ( 1) ) 3L dib Rb VC1 = i b ( Sa 1... SaN ( 2) ) + 2( Sb SbN ( 2) ) ( Sc ScN ( 2) ) + dt L 3L VC2 + ( Sa SaN ( 2) ) + 2( Sb SbN ( 2 3L )) ( Sc ScN ( 2) ) + VC3 + ( S a3... SaN ( 2) ) 2( Sb3... SbN ( 2) ) ( Sc3... ScN ( 2) ) + 3L VCN ( 2) + ( SaN ( 2) + 2 SbN ( 2) ScN ( 2) ) + 3L VDC + ( SaN ( 1) + 2 SbN ( 1) ScN ( 1) ) 3L dic Rc VC1 = ic+ ( Sa SaN ( dt L 3L 2) ) ( Sb SbN ( 2) ) + 2( Sc ScN ( 2) ) + VC2 + ( Sa SaN ( 2) ) ( Sb2... SbN ( 2) ) 2( Sc2... ScN ( 2) ) + 3L VC3 + ( Sa SaN ( 2) ) ( Sb SbN ( 2) ) + 2( Sc ScN ( 2) ) + 3L VCN ( 2) + ( SaN ( 2) SbN ( 2) + 2 ScN ( 2) ) + 3L VDC + ( SaN ( 1) SbN ( 1) + 2 ScN ( 1) ) 3L (3.9) 52

53 3.2.2 Three-Leg Four-Wire Diode-Clamped Converter (3L4W-DCC) Model The mathematical model of this topology is very similar to 3L3W-DCC model. In fact, the only difference is that, in this topology, V N0 voltage is constant and equal to V DC /2. The commutation model for this topology is shown in Figure 3.6. Figure 3.6. Commutation model for N-level 3L4W Diode-Clamped Converter connected to a RL load 53

54 So, the expressions presented for the 3L3W topology are valid but imposing that V N0 is equal to the middle DC-Link voltage. Hence, state equations for the DC- Link capacitors voltage for 3L4W DCC are (3.4). Nevertheless, the phase currents state equations change due to the presence of the fourth wire connecting the neutral point of the load with the middle point of the DC-Link. So, using 3L4W-DCC topology, the phase voltages with respect to the neutral point of the load can be determined. VDC V = V 0 = Ri 2 VDC V = V 0 = Ri 2 VDC V = V 0 = Ri 2 an a a a bn b b b cn c c c (3.10) And finally, the phase currents state equations are presented. dia Ra VDC 1 = ia + VC1( Sa SaN ( 2) ) + VC2( Sa SaN ( 2) ) + dt L 2L L... V S V S + + CN ( 2) an ( 2) + DC an ( 1) dib Rb VDC 1 = i + b VC 1( Sb SbN ( 2) ) + VC2( Sb SbN ( 2) ) + dt L 2L L V S + V S CN ( 2) bn ( 2) DC bn ( 1) (3.11) dic dt Rc VDC 1 = ic + VC1( Sc ScN ( 2) ) + VC2( Sc ScN ( 2) ) + L 2L L... V S V S + + CN ( 2) cn ( 2) + DC cn ( 1) 54

55 3.2.3 Four-Leg Four-Wire Diode-Clamped Converter (4L4W-DCC) Model The commutation model of the 4L4W N-level DCC is shown in Figure 3.7. The commutation model has been validated connecting the converter to a R-L load. This system is going to be described in detail. Figure 3.7. Commutation model for N-level 4L4W Diode-Clamped Converter connected to a RL load It can be seen that the DC-Link capacitors voltages state equations can be determined using (3.4) where f i and g i were defined in (3.5) but assuming that F i functions can be determined as follows. 55

56 F = Si + Si + Si + Si = ( S S ) i + ( S S ) i + ( S S ) i (3.12) i ai a bi b ci c di N ai di a bi di b ci di c On the other hand, the voltage of the neutral point of the load with respect to 0 (lowest point of the DC-Link) can be determined. V = SV + S ( V + V ) + S ( V + V + V ) N0 d1 C1 d2 C1 C2 d3 C1 C2 C3 + S ( V V ) + S V dn ( 2) C1 CN ( 2) dn ( 1) DC (3.13) The phase voltages with respect to 0 are calculated thanks to expression (3.6) and finally, using (3.8), the phase currents state equations are presented. 56

57 dia Ra VC 1 = i a+ ( Sa SaN ( 2) ) ( Sd SdN ( 2) ) + dt L L VC2 + ( S + + a2... SaN ( 2) ) ( Sd SdN ( 2) ) + L VC3 + ( S + + a3... SaN ( 2) ) ( Sd SdN ( 2) ) L VCN ( 2) + S an ( 2) SdN ( 2) + L VDC + SaN ( 1) S dn ( 1) L dib Rb VC 1 = i b+ ( Sb SbN ( 2) ) ( Sd SdN ( 2) ) + dt L L VC2 + ( S + + b2... SbN ( 2) ) ( Sd SdN ( 2) ) + L VC3 + ( S + + b3... SbN ( 2) ) ( Sd SdN ( 2) ) L VCN ( 2) + S bn ( 2) SdN ( 2) + L VDC + SbN ( 1) S d( L N 1) (3.14) dic Rc VC1 = i c + ( Sc ScN ( 2) ) ( Sd SdN ( 2) ) + dt L L VC2 + ( S + + c2... ScN ( 2) ) ( Sd SdN ( 2) ) + L VC3 + ( S + + c3... ScN ( 2) ) ( Sd SdN ( 2) ) L VCN ( 2) + S cn ( 2) SdN ( 2) + L VDC + ScN ( 1) L S dn ( 1) 57

58 3.3 Flying Capacitor Converter Model Three-Leg Three-Wire Flying Capacitor Converter (3L3W-FCC) Model All developed FCC models assume that the converter is connected to an RL load. Each multilevel single phase FCC can is represented in Figure 3.8. In order to build the commutation model of the flying capacitor converter, it is necessary to use FC xi factor definition using each basic cell binary values H xi defined in (2.1) for M-cell single phase x FCC. Figure 3.8. Single phase FCC. In the three-phase model, each phase is connected to an RL load. 58

59 0, Hxi = Hxi ( + 1) FCxi = 1, Hxi = 0 and Hxi ( + 1) = 1 with i= 1,..., M 1 1, Hxi = 1 and Hxi ( + 1) = 0 (3.15) Using this definition, the state equations for multilevel FCC can be easily determined. In general, for M-cell FCC it can be determined currents that flow through the floating capacitors in phase x. dvcx1 i 1 = C 1 = FC 1i dt dvcx2 i 2 = C 2 = FC 2i dt... Cx p x x Cx x x x dv i C FC i dt Cx( M 1) Cx( M 1) = xm ( 1) = xm ( 1) x (3.16) And the state equations of the floating capacitor voltages can be determined. dv dt dv dt FC i = C Cx1 x1 x x1 FC i = C Cx2 x2 x... x2 dv FC i = dt C Cx( M 1) xm ( 1) x xm ( 1) (3.17) These expressions are valid for every flying capacitor voltage ratio only taking into account that depending on the chosen flying capacitor voltage ratio (OFBCS, NFBCS or NEFBCS), the flying capacitor voltages (V Cxi ) magnitude and sign change. 59

60 In order to determine the state equations for the phase currents, only the two-cell FCC case is shown because increasing the number of cells, expressions are not easily extended. Anyway, expressions for a large number of cells can be calculated following the same steps presented in this thesis. The output phase voltages with respect to 0 (lowest point of the DC-Link) are calculated as follows using two-cell OFBCS ratio. VDC VDC dia Va0 = Sa1[ + FCa1( VCa1)] + Sa2VDC L 2 2 dt VDC VDC dib Vb0 = Sb1[ + FCb1( VCb1)] + Sb2VDC L 2 2 dt (3.18) VDC VDC dic Vc0 = Sc1[ + FCc1( VCc1)] + Sc2VDC L 2 2 dt For two-cell NFBCS and NEFBCS ratios, dia Va0 = Sa0VCa1+ Sa2VDC + Sa3( VDC + VCa1) L dt dib Vb0 = Sb0VCb1+ Sb2VDC + Sb3( VDC + VCb1) L dt (3.19) dic V = S V + S V + S ( V + V ) L dt c0 c0 Ca1 c2 DC c3 DC Cc1 3L3W topology fulfils that the voltage of the neutral point of the load with respect to 0 is determined using (3.7) and the phase voltages with respect to the neutral point of the load are determined using (3.8). Finally, the phase currents state equations for two-cell FCC using OFBCS ratio are presented. 60

61 dia Ra = i a SFC a1 a1 V Ca1+ SFC b1 b1 V Cb1+ SFC c1 c1 V Cc1+ dt L 3L 3L 3L 1 1 { [ 1(1 1) 2 2] [ 1(1 1) 1(1 1) 2( 2 2)] } + V S + FC + S S + FC + S + FC + S + S 3L 6L DC a a a b b c c b c dib Rb = i b SFC b1 b1 V Cb1+ SFC a1 a1 V Ca1+ SFC c1 c1 V Cc1+ dt L 3L 3L 3L VDC [ Sb 1 (1 + FCb 1 ) + 2 Sb2] [ Sa1(1 + FCa 1) + Sc1(1 + FCc1) + 2( Sa2+ Sc2)] 3L 6L { } (3.20) dic Rc = i c SFC c1 c1 V Cc1+ SFC a1 a1 V Ca1+ SFC b1 b1 V Cb1+ dt L 3L 3L 3L 1 1 { [ 1(1 1) 2 2] [ 1(1 1) 1(1 1) 2( 2 2)] } + V S + FC + S S + FC + S + FC + S + S 3L 6L DC c c c a a b b a b The phase currents state equations for two-cell FCC using NFBCS and NEFBCS ratios are presented. dia Ra 1 = i a+ [2 V Ca1 ( S a0+ S a3 ) V Cb1 ( S b0+ S b3 ) V Cc1 ( S c0+ S c3 ) + dt L 3L V (2S + 2 S S S S S )] DC a2 a3 b2 b3 c2 c3 dib Ra 1 = i b+ [ V Ca1 ( S a0 + S a3 ) + 2 V Cb1 ( S b0 + S b3 ) V Cc1 ( S c0 + S c3 ) + dt L 3L V ( S S + 2S + 2 S S S )] dic dt DC a2 a3 b2 b3 c2 c3 Rc 1 = ic+ [ VCa1 ( Sa0+ Sa3 ) VCb 1 ( Sb0+ Sb3 ) + 2 VCc1 ( Sc0+ Sc3 ) + L 3L V ( S S S S + 2S + 2 S )] DC a2 a3 b2 b3 c2 c3 (3.21) 61

62 3.3.2 Three-Leg Four-Wire Flying Capacitor Converter (3L4W-FCC) Model The state equations of 3L4W FCC can be determined. In general, for N-cell converter the floating capacitor voltages state equations are exactly the same that equations presented for 3L3W DCC in (3.17). The state equations of 3L4W FCC can be easily determined applying expressions (3.10), (3.18) and (3.19). For two-cell OFBCS ratio, dia Ra VDC Sa1 = i + [ S (1 FC ) + 2S 1] + V FC dt L 2L L dib Rb VDC Sb1 = i + [ S (1 FC ) + 2S 1] + V FC dt L 2L L dic Rc VDC Sc1 = i + [ S (1 FC ) + 2S 1] + V FC dt L 2L L a a1 a1 a2 Ca1 a1 b b1 b1 b2 Cb1 b1 c c1 c1 c2 Cc1 c1 (3.22) And for two-cell NFBCS and NEFBCS ratios, dia Ra VCa1 VDC 1 = ia + ( Sa3 Sa0) + ( Sa2 + Sa3 ) dt L L L 2 dib Rb VCb1 VDC 1 = ib + ( Sb3 Sb0) + ( Sb2 + Sb3 ) dt L L L 2 dic Rc VCc1 VDC 1 = ic + ( Sc3 Sc0) + ( Sc2 + Sc3 ) dt L L L 2 (3.23) 62

63 3.3.3 Four-Leg Four-Wire Flying Capacitor Converter (4L4W-FCC) Model The state equations of 4L4W FCC can be determined. In general, for N-cell converter the floating capacitor voltages state equations are exactly the same that equations presented for 3L3W DCC in (3.17). The flying capacitor current state equations of 4L4W FCC can be determined applying (3.8). In 4L4W FCC, V N0 voltage is calculated depending on the chosen voltage ratio. For two-cell OFBCS, VDC VDC V 0 = S 1[ FC 1( V 1 ) + ] + S 2V 2 2 N d d Cd d DC (3.24) And for two-cell NFBCS and NEFBCS, V = ( S + S ) V + ( S S ) V (3.25) N0 d2 d3 DC d3 d0 Cd1 Finally, using (3.18) and (3.19), the flying capacitor current state equations are presented. For two-cell OFBCS ratio, 63

64 di a dt dib dt dic dt VDC = [ Sa1(1 FCa1) + 2( Sa2 Sd2) Sd1(1 FCd1)] + 2L VCa1 VCd1 Ra + Sa1FCa1 Sd1FCd1 ia L L L VDC = [ Sb1(1 FCb1) + 2( Sb2 Sd2) Sd1(1 FCd1)] + 2L VCb1 VCd1 Rb + Sb1FCb1 Sd1FCd1 ib L L L VDC = [ Sc1(1 FCc1) + 2( Sc2 Sd2) Sd1(1 FCd1)] + 2L VCc1 VCd1 Rc + Sc1FCc1 Sd1FCd1 ic L L L (3.26) And for two-cell NFBCS and NEFBCS ratios, dia Ra VCa 1 VCd1 VDC = ia+ ( Sa3 Sa0) ( Sd3 Sd0) + ( Sa2+ Sa3 Sd2 Sd3) dt L L L L dib Rb VCb1 VCd1 VDC = ib+ ( Sb3 Sb0) ( Sd3 Sd0) + ( Sb2+ Sb3 Sd2 Sd3) dt L L L L dic Rc VCc1 VCd1 VDC = ic + ( Sc3 Sa0) ( Sd3 Sd0) + ( Sc2+ Sc3 Sd2 Sd3) dt L L L L (3.27) 64

65 Two-cell 3L3W FCC state equations using OFBCS voltage ratio di a a R 0 0 SFC a1 a1 SFC b1 b1 SFC c1 c1 dt L 3L 3L 3L R b dib 0 0 SFC a1 a1 SFC b1 b1 SFC [2 Sa 1 (1 + FCa 1 ) + 4 Sa2 Sb 1 (1 + FCb 1 ) 2 Sb2 Sc 1 (1 + FCc 1 ) 2 Sc2 ] c1 c1 6L dt L 3L 3L 3L ia di Rc i c 0 0 SFC a1 a1 SFC b1 b1 SFC b [2 Sb 1 (1 + FCb 1 ) + 4 Sb 2 Sa 1 (1 + FCa 1 ) 2 Sa2 Sc 1 (1 + FCc 1 ) 2 S 2] c c1 c1 6L dt L 3L 3L 3L i = c dv FC + a1 Ca V 1 [2 S Ca1 c1 (1 + FCc 1 ) + 4 Sc2 Sa 1 (1 + FCa 1 ) 2 Sa2 Sb 1 (1 + FCb 1 ) 2 S 2 ] V b 6L dt Ca 1 V Cb1 dv FC 0 Cb1 b V Cc1 0 dt Cb 1 dvcc 1 0 FCc 1 dt Cc 1 DC

66 Two-cell 3L3W FCC state equations using NFBCS or NEFBCS voltages ratio di a a R 0 0 ( Sa 0+ Sa3) ( Sb0+ Sb 3) ( Sc0+ Sc 3) dt L 3L 3L 3L Rb dib 0 0 ( Sa 0+ Sa 3) ( Sb 0+ Sb 3) ( Sc0+ Sc 3) [2 Sa 2+ 2 Sa 3 Sb2 Sb3 Sc2 Sc3 ] 3L dt L 3L 3L 3L ia di Rc i b [ S c 0 0 ( Sa 0+ Sa 3) ( Sb0+ Sb 3) ] ( 0 3) a Sa + Sb + Sb Sc S S c c + S c 3L dt L 3L 3L 3L i = c 1 dv FC + a1 Ca1 1 [ S V Ca a S a3 Sb2 Sb 3+ 2Sc2+ 2 S 3] V c 3L dt Ca 1 V Cb1 dv FC 0 Cb1 b V Cc1 0 dt Cb 1 dvcc 1 0 FCc 1 dt Cc 1 DC 66

67 Two-cell 3L4W FCC state equations using OFBCS voltage ratio di a 1 a R 0 0 SFC a1 a1 0 0 dt L L R 1 1 b dib SFC [ Sa 1 (1 FCa 1 ) + 2 Sa2 1] b b L L i 2L dt a di Rc 1 i 1 b c SFC [ S b1 (1 FCb 1 ) 2 S 2 1] + b c1 c1 2L dt L L i c = dv FC 1 + a1 [ Ca (1 1 ) 2 2 1] V V S 1 c FCc + Sc Ca 2L dt C a1 V Cb1 dv FC 0 Cb1 b VCc1 0 dt Cb 1 dv Cc1 FC 0 c dt Cc 1 DC 67

68 Two-cell 3L4W FCC state equations using NFBCS or NEFBCS voltages ratio di a 1 a R 0 0 ( Sa 3 Sa0) 0 0 dt L L R b dib ( Sb 3 Sb0) 0 ( Sa2+ Sa 3 ) L L L 2 dt ia di Rc c ( Sc 3 Sc0) i b ( S b2 S 3 ) + b L 2 dt L L i c = dv FC a1 ( Ca ) V V Sc + Sc Ca L 2 dt C a1 V Cb1 dv FC 0 Cb1 b VCc1 0 dt Cb 1 dv 0 FC Cc1 c1 dt Cc 1 DC 68

69 Two-cell 4L4W FCC state equations using OFBCS voltage ratio Ra 1 1 dia 0 0 SFC a1 a1 0 0 SFC d1 d1 dt L L L Rb 1 1 dib SFC b1 b1 0 SFC 1 d1 d1 dt L L L [ Sa 1 (1 FCa 1 ) + 2( Sa 2 Sd2 ) Sd1 (1 FCd 1 )] 2L ia Rc 1 1 dic SFC c1 c1 SFC 1 d1 d1 i b [ Sb 1 (1 FCb 1 ) + 2( Sb2 Sd2 ) Sd 1 (1 FC 1 )] d dt L L L 2L FC dv ic a1 Ca1 = [ 1 (1 1 ) 2 C VCa 1 + Sc FCc + ( Sc2 Sd2) Sd 1(1 FC 1)] d dt a1 V 2L DC dv FC VCb 1 Cb1 b dt C 0 V b1 Cc1 0 dvcc 1 FC V Cd1 c1 0 0 dt Cc 1 0 dvcd1 FCd 1 dt C d1 69

70 Two-cell 4L4W FCC state equations using NFBCS or NEFBCS voltages ratio Ra ( Sa 3 Sa0) 0 0 ( Sd3 Sd0) L L L dia Rb 1 1 dt ( Sb 3 Sb0) 0 ( Sd3 Sd0) 1 L L L ( Sa 2+ Sa 3 Sd2 Sd3 ) dib L R ia c 1 1 dt ( Sc3 Sc0) ( Sd3 Sd0) 1 i b ( Sb 2+ Sb 3 Sd2 S 3 ) d di L L L L c FC i dt = 1 ( ) dv L Ca1 dt FC V Cb1 0 b dv C V Cb1 b1 Cc1 0 dt FC V Cd1 c dvcc 1 Cc 1 0 dt FCd C d1 c a C V S Ca1 + c + Sc Sd S d V a1 DC 70

71 Chapter 4 Modulation Techniques for Multilevel Converters 4.1 Introduction In previous chapters, several multilevel converter topologies have been presented. Each topology has different switching configurations in order to achieve the desired output signals. The converter switching must be controlled to follow a control reference and modulation strategies are in charge to define the switching control in the converter. The primary objective of the modulation algorithm is to synthesize a control reference obtaining a pulse train with the same averaged value. Several modulation strategies have been proposed in the literature. Pulse Width Modulation (PWM) and Space Vector PWM (SVPWM) techniques are typical modulation strategies and they are explained in the next points.

72 4.2 Classic PWM Modulations Pulse Width Modulation (PWM) strategy is carried out obtaining a pulse train where the pulse s width has the modulation information [37]. The simplest PWM technique implementation can be done using a triangular carrier signal with frequency f c trying to modulate a reference signal with lower frequency f s. In Figure 4.1, a sinusoidal reference signal is modulated using a triangular carrier obtaining a high frequency PWM pulse train [37]. Multilevel PWM can be obtained using more than one triangular carrier. For an N-level converter, N-1 carriers are arranged in contiguous bands across the full linear modulation range of the multilevel converter. All the carriers have the same frequency and amplitude and the reference waveform is placed in the middle of the carrier bands [38][39]. As an example, a five-level PWM schema is shown in Figure 4.2. Different possibilities appear because several relative carrier phases can be used. In the first case (Figure 4.2), all the carriers were in phase and this PWM is named Phase Disposition PWM or PD-PWM. Other possibility lies in to use a 180º phase shifts between positive and negative carriers. This possibility is named Phase Opposition Disposition PWM or POD-PWM and it can be seen in Figure 4.3. Other possible PWM can be carry out doing that each carrier is alternately out of phase with its neighbour. This possibility is named Alternative Phase Opposition Disposition PWM or APOD-PWM and it can be seen in Figure 4.4 [40]. 72

73 Figure 4.1. Conventional two-level PWM. The low frequency reference signal is modulated using a triangular carrier with higher frequency. Figure 4.2. Five-level PWM schema using four triangular carriers disposed to carry out PD-PWM. 73

74 Figure 4.3. Five-level PWM schema using four triangular carriers disposed to carry out POD-PWM. Figure 4.4. Five-level PWM schema using four triangular carriers disposed to carry out APOD-PWM. 74

75 Some authors have compared the different PWM strategies showing the spectral analysis produced by the modulation processes [41]. These studies say that PD- PWM is harmonically superior across the bulk of the modulation region because is the only technique which places harmonic energy into a common mode carrier harmonic which cancels in the line to line voltage. In order to show the modulation quality of the presented PWM schemes, the total harmonic distortion (THD) using PD-PWM, POD-PWM and APOD-PWM are shown in Figure 4.5, Figure 4.6 and Figure 4.7 respectively and several PWM comparisons are present in the literature [42]-[44]. Finally, it must be noticed that many more strategies have been proposed in order to improve some characteristics of the converter operation [45]-[50]. Figure 4.5. Total Harmonic Distortion (% of fundamental) for a five-level converter using PD-PWM 75

76 Figure 4.6. Total Harmonic Distortion (% of fundamental) for a five-level converter using POD-PWM Figure 4.7. Total Harmonic Distortion (% of fundamental) for a five-level converter using APOD-PWM 76

77 4.3 Space Vector PWM Modulation An alternative PWM method is the Space Vector Modulation (SVPWM) [51]. This modulation method presents important advantages compared with PWM modulation [43][44]. As it was seen before, PWM modulation calculates the multilevel converter switching configurations automatically. In fact, it is an automatic method that completely marks the switching of the converter and there is no ANY freedom degree and the control algorithm has not the possibility of changing for instance the order of the switching configurations in the switching sequence. So, there is no freedom in order to improve some characteristics of the converter as balancing of DC-link capacitors, harmonic content, load currents ripple,,etc [52]. In front of this fact, SVPWM modulation calculates the switching configurations and chooses their order into the switching sequence [51]. Besides, SVPWM modulation introduces the concept of the redundant vectors and their important contribution to the converter control [53]. First of all, the State Vectors Space of a converter is going to be introduced to present this modulation method. Several converter configurations presented in chapter 2 are considered: three-leg threewire converters, three-leg four-wire converters and four-leg four-wire converters Three-leg three-wire converters (3L3W) Three-phase converters without connecting the neutral point of the load are named three-leg three-wire systems (3L3W systems) and they were presented in chapter 2. A 3L3W two-level conventional converter is shown in Figure

78 V DC 2 C 1 S 1 a S 3 b S 5 c V DC 2 C 2 S 2 S 4 S 6 load load load Figure L3W two-level conventional converter Output phase-to-neutral voltages (V xn ) for two-level conventional converter can be determined. V xn can be represented using αβγ coordinates resulting that V xn γ coordinate is equal to zero and the state vectors can be placed on the αβ plane. The state vectors space for two-level conventional converter is shown in Figure 4.9. Two possible states are placed in the same point in the plane. These state vectors are named redundant vectors and they are completely equal seen from the load. Each 3L3W state vector of the converter is defined as xyz where x is the state of phase a, y is the state of phase b and z is the state of phase c. In two-level case, if the highest phase transistor is switched on, the associated parameter is equal to 1 and if the lowest phase transistor is switched on, the associated parameter is equal to 0. So, for example, the state vector 100 means that transistors S 1, S 4 and S 6 are switched on and S 2, S 3 and S 5 are switched off. 78

79 Figure 4.9. State vectors space for two-level conventional converters SVPWM considers a complex voltage vector as the reference waveform to follow. This reference signal ( u ref ) is sampled with a constant frequency and the converter generates it using a linear combination of possible state vectors. So, the modulation technique samples the reference signal and looks for the three nearest state vectors determining their three duty cycles respectively [51]. Hence, the output signal achieved by the converter is equal to the reference signal averaged over a sampling period. In order to illustrate SVPWM method, in Figure 4.10 the reference voltage ( u ref ) is generated thanks to carry out a linear combination of the three nearest vectors (100, 110 and 000 or 111). 79

80 Figure Reference vector synthesis using the three nearest state vectors in the control region The state vectors space increasing the number of levels of the converter can be determined in the same way that two-level converter control region was calculated [53]. For instance, the state vectors space for a five-level DCC is shown in Figure In this case, there are 27 possible different state vectors and they are also placed in the αβ plane forming two concentric hexagons. Only 19 different positions in the αβ plane cover the 27 different state vectors and therefore, there are 8 redundant vectors in five-level DCC state vectors space. Figure State vectors space for five-level DCC 80

81 It is easy to determine the state vectors space for N-level DCC and it is shown in Figure It is clear that increasing the number of levels, new and concentric hexagons appear. Besides, the redundancy of the vectors increases if the state vectors are close to the origin. Increasing the number of levels in the DCC, the number of triangular sectors that compose the total control region increases and the search for the three nearest state vectors increases its difficulty. Several generalized modulation algorithms for multilevel converters have been recently proposed [53]-[63]. An effective approach that drastically reduces the computational load using a decision-making algorithm was presented in [64]. The proposed method was based on the decision-based pulse width modulation introduced in [65]. As it was said before, any modulation algorithm has to carry out two different tasks. The first one is to identify the three nearest state vectors to the reference vector. After that, the modulation algorithm has to calculate each state vector duty cycle. Figure State vectors space for N-level DCC 81

82 One of the most important contributions of [64] is that the normalised reference voltage vector u* is transformed into u flat scaling u* imaginary part and multiplying it by 1 3. The modulation algorithm input is the normalised reference voltage vector. The normalisation depends on the number of levels of the multilevel converter and the voltage level value of the DC-link capacitors. Using the proposed transformation, multilevel converter state vectors space is flattened. The state vectors space after the transformation is a hexagon where all the sectors are separated by 45º lines. This property is very useful due to the fact that the modulation algorithm can easily find out the triangular sector where u flat is pointing to by comparing their real and imaginary parts. This transformation drastically reduces the modulation algorithm computational cost doing it very fast and efficient. The state vectors space before and after the transformation is shown in Figure Figure The state vectors space is flattened multiplying by 3 the imaginary part of the reference vector making the search for the nearest state vectors very simple and fast 82

83 In [64], the first problem is solved for the reference vector in the first sextant. However, this reference vector can be located in any of the six sectors of the regular hexagon which contain the switching state vectors. This problem was solved rotating the reference vector anti-clockwise by an angle (n-1)π/3, where n is the sextant number, n = 1,,6. This rotation displaces any reference vector to the first sextant to be studied there. This algorithm clearly improves the results of previous modulation algorithms due to the fact that its simplicity is very high. Nevertheless, there are several complex operations as the rotation to the first sextant and the inverse rotation to obtain the final switching sequence and the final on-state durations. In order to eliminate these complex operations, a new and faster modulation algorithm was proposed in [66]. On the same way, the state vectors space is flattened in order to achieve 45º lines but online calculations are reduced due to the fact that the modulation algorithm implies only very simple calculations. The modulation algorithm obtains the switching sequence and the duty cycles in the simplest way. This modulation algorithm based on geometrical considerations. One N-level state vectors space sector is shown in Figure Each state vector is represented using the expression {x,y,z}. For example, if it is considered the state vector {320}, that means that x=3 (phase a state is 3), y=2 (phase b state is 2) and z=0 (phase c state is 0). It can be easily determined x graphically. y can be calculated limiting vertically the region where the reference vector is pointing to. Thus, every reference vector located in this state vectors space sector fulfils that z component is always zero. x = integer (u αn +u βn ) y=integer (2u βn ) z=0 (4.1) 83

84 u n=-u n+1 u n u n=-u n u n=2 u n=1.5 u n=1 u n= u n Figure N-level state vectors space sector Once x, y and z are determined, it is known that the reference voltage is pointing to a sub-region in this sector. Figure 4.15 shows a generic sub-region in zone 1. This sub-region is divided in two different triangles. Figure Sub-region of N-level state vectors space 84

85 It is necessary to know which is the triangle where the reference vector is found to determine the other states and the switching times. The condition that the reference vector should fulfill to be found in triangle number one is: u < u + y x u u < ( y x) (4.2) βn αn βn αn It must be noticed that this modulation algorithm drastically reduces the online calculations due to the fact that the search for the nearest state vectors implies only very simple calculations. The modulation algorithm obtains the switching sequence and the duty cycles in the simplest way Three-leg four-wire converters (3L4W) Three-phase converters connecting the neutral point of the load to the middle point of the DC-link bus are named three-leg four-wire systems (3L4W systems) and they were presented in chapter 2. A 3L4W two-level conventional converter is shown in Figure Figure Two-level 3L4W conventional converter 85

86 In 3L4W converters zero current can flow through the neutral wire and the phase currents could be not equilibrated. In this case, the γ coordinate of the phase-toneutral voltages (V XN ) could be not equal to zero and the state vectors space can not be represented only using the αβ plane. Therefore, a three dimensional representation must be used in order to represent the state vectors space for 3L4W converters. Previous authors have represented the state vectors space for 3L4W converters using three dimensional αβγ coordinates [67]. It can be easily represented and for instance, the state vectors space for two-level 3L4W conventional converters and five-level 3L4W DCC are shown in Figure 4.17 and Figure 4.18 respectively. Figure State vectors space for two-level 3L4W conventional converters using αβγ coordinates 86

87 Figure State vectors space for five-level 3L4W DCC In the three dimensional case, the reference voltage ( u ref ) must be generated carrying out a linear combination of the four nearest vectors. These nearest state vectors form a volume (a tetrahedron) and therefore 3D SVPWM algorithms have to find out the tetrahedron where the reference vector is pointing to. After discovering the tetrahedron, the modulation algorithm knows the four nearest vectors (they are the vertexes of the tetrahedron) to carry out the linear combination of them in order to generate the reference vector averaged over a sampling period. An example of the reference vector generation in a five-level DCC is shown in Figure

88 Figure Reference vector generation using the four nearest vectors in a fivelevel 3L4W DCC Using αβγ coordinates, the possible tetrahedrons that compose the state vectors space have different shapes and volumes. Several volume shapes appear and it is not easy to develop computationally efficient modulation algorithms to find out the tetrahedron where the reference vector is pointing to. In spite of it, some authors have developed 3D SVPWM algorithms using αβγ coordinates for 3L4W topologies [67]. But these algorithms are complex and their computational cost is important. This is the fundamental drawback of this type of 3D SVPWM algorithms. 88

89 Therefore, it is necessary to change the representation way of the multilevel state vectors space. This is the reason because abc coordinates are used by other authors doing modulation algorithms more simple and more easily implemented [70]. In order to reduce the 3D SVPWM computational cost, 3L4W converters state vectors space can be represented using abc coordinates instead αβγ coordinates. The state vectors space for two-level 3L4W conventional converters is shown in Figure Figure State vectors space for two-level 3L4W conventional converters using abc coordinates It must be noticed that for 3L4W case, there are not redundant vectors because the state vectors are located in different positions. The 3L4W converter state vectors space increasing the number of levels can be done. For instance, the three-level 3L4W converter state vectors space is shown in Figure

90 Figure Three-level 3L4W converter state vectors space using abc coordinates Increasing the number of levels of the converter, the state vectors space for an N- level 3L4W converter forms a cube in the 3D-space. This cube is formed by a certain number of sub-cubes depending on the number of the levels of the converter. Only one sub-cube for two-level converters, eight sub-cubes for threelevel converters, twenty-seven sub-cubes for four-level converters. In general, (N-1) 3 sub-cubes into the total cube, where N is the number of levels of the multilevel converter. Using abc coordinates, the modulation algorithm computational cost is lower than using αβγ coordinates. In fact, abc coordinates divide the volume control in cubes doing easier and faster the search for the four nearest vectors to the reference vector. A fast and efficient generalized multilevel 3D SVPWM algorithm was presented in [70]. It is based on a generalization of 3D SVPWM 90

91 presented in [66] and it is the basis of other developed multilevel 3D SVPWM algorithms presented in this thesis. Besides, using [70] the number of switching commutations and the number of calculations to determine the switching sequence and the duty cycles are minimized. In this generalized modulation algorithm, the N-level generalization is done thanks to the reduction of the multilevel problem into a two levels one. This basic 3D SVPWM algorithm is based on several steps: Step 1: Calculate the coordinates of the sub-cube reference vertex where the reference vector is found. The multilevel control region is divided in several sub-cubes and the first step of the modulation algorithm is to find the sub-cube where the reference vector is pointing to. Considering this sub-cube using abc coordinates and changing the origin coordinates to the nearest to (0,0,0) sub-cube vertex, the problem is reduced to a two level case because the two level control region is one sub-cube. For a certain reference vector in three-phase coordinates (u an, u bn, u cn ), the integer part of each component (a,b,c) is calculated with u an, u bn, u cn {0,..., 2(N-1)}. a = integer (u an ), b = integer (u bn ), (4.3) c = integer (u cn ), The coordinates (a,b,c) are the coordinates origin corresponding to the reference system of the sub-cube where the reference vector is pointing to. This sub-cube is exactly equal as the two-level state vectors space case. So, the multilevel case is reduced to a two levels case only calculating the factors a, b and c. This is shown in Figure

92 Figure Sub-cube reference coordinates in generalized 3D SVPWM algorithms Step 2: Divide the sub-cube in several tetrahedrons. Once (a,b,c) coordinates are known, the algorithm calculates the four state vectors corresponding to the four vertices of the tetrahedron into the selected sub-cube where the reference vector is located. These vectors will generate the reference vector. The first option to divide the sub-cube was presented in [70]. Using this subcube division, the tetrahedron where the reference vector is located is easily found using comparisons with three 45º planes into the 3D space which define the six tetrahedrons inside the sub-cube. These tetrahedrons are shown in Figure In [70], the diagram flow to find out the nearest four vectors is shown and it is important to notice that they are calculated using a maximum of three 92

93 comparisons for calculating the suitable tetrahedron. The modulation algorithm is so easy due to the 45º planes dividing the sub-cube. This space division is named SD45 in this work. But other sub-cube divisions can be considered. 3D SVPWM algorithms look for the best tetrahedron to generate the reference vector. The best solution is to use the tetrahedron where all the distances between the reference vector and the four state vectors are minimum. In fact, the ideal solution would be to increase infinitely the number of levels of the converter doing that the reference vector is always perfectly generated using only one state vector. So, minimizing the distances between the reference vector and the state vectors, the ripple of the resultant output signals will be minimized. Other planes can be used to divide each sub-cube and in this thesis, new division planes are presented. Four new planes are used to divide the sub-cube volume and resulting tetrahedrons are shown in Figure In this case, five tetrahedrons compose the sub-cube volume where there is one central tetrahedron and four external ones. Five is the minimum number of tetrahedrons to compose the sub-cube. This fact is mathematically demonstrated in [1]. This new space division is named SD1. 93

94 94 Figure Sub-cube division using 45º planes (named SD45 space division). Six tetrahedrons compose the total sub-cube volume

95 b CASE 1 b CASE a 100 a c c b CASE b CASE a 100 a c c b 001 CASE a c Figure Sub-cube division using new planes (named SD1). Five tetrahedrons compose the total sub-cube volume 95

96 Using the same notation described in [70], the flow diagram to find out the tetrahedron where the reference vector is pointing to using SD1 is shown in Figure Once the tetrahedron is found, the state vectors to be used and their duty cycles can be determined using Table I. Normalized reference vector: (u an, u bn, u cn ) a = integer (u an ) b = integer (u bn ) c = integer (u cn ) r a =u an -a r b =u bn -b r c =u cn -c Yes r a +r b -r c < 0 No Case 1 No r a -r b +r c < 0 Yes Yes r a +r b +r c > 2 No Case 4 Case 3 Yes r a -r b -r c > 0 No Case 2 Case 5 Figure Flow diagram to find out the tetrahedron where the reference vector is pointing to using space division SD1 96

97 More possible sub-cube divisions can be considered using SD1 but rotating them 90º over b axis. The obtained tetrahedrons (named space division SD2) are represented in Figure In the same way that using previous 3D space divisions, other flow diagram can be defined to find out the tetrahedron where the reference vector is pointing to. The flow diagram for space division SD2 is shown in Figure Step 3: Duty cycles calculation. The reference vector is generated by a linear combination of four state vectors determined in step 2. j S in is the phase i state located in position j in the switching sequence and d j is the duty cycle j. The duty cycles calculation can be described using the following matrix expression an bn cn San Sbn Scn San Sbn Scn San Sbn Scn [ r r r 1] = [ d d d d ] a b c S S S R= DS i D= RS i 1 (4.4) Using these equations, the modulation algorithm can determine the duty cycles. The final results using SD45, SD1 and SD2 are shown in TABLE 4.I, TABLE 4.II and TABLE 4.III respectively. These tables summarize the switching sequences and the duty cycles for all possible locations of the reference vector inside the two-level sub-cube. 97

98 b CASE 6 b CASE a a c c b CASE 8 b CASE a a c b c 001 CASE a c Figure Sub-cube division SD2. Five tetrahedrons compose the total subcube volume 98

99 Normalized reference vector: (u an, u bn, u cn ) a = integer (u an ) b = integer (u bn ) c = integer (u cn ) r a =u an -a r b =u bn -b r c =u cn -c Yes -r a +r b +r c > 1 No Case 6 No r a +r b -r c > 1 Yes Yes r a +r b +r c > 2 No Case 7 Case 8 Yes r a -r b -r c < 0 No Case 9 Case 10 Figure Flow diagram to find the tetrahedron where the reference vector is pointing to using space division SD2 99

100 TABLE 4.I SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON THE TETRAHEDRON CASE USING SPACE DIVISION SD45 Tetrahedron State vectors sequence Duty cycles Case 1 (S 1 an, S 1 bn, S 1 cn) = (a, b, c) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b, c) (S 3 an, S 3 bn, S 3 cn) = (a + 1, b, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b + 1, c + 1) d 1 = 1 -r a, d 2 = r a - r c, d 3 = -r b + r c, d 4 = - r b, Case 2 (S 1 an, S 1 bn, S 1 cn) = (a, b, c) (S 2 an, S 2 bn, S 2 cn) = (a, b + 1, c) (S 3 an, S 3 bn, S 3 cn) = (a, b + 1, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b + 1, c + 1) d 1 = 1 - r b, d 2 = r b - r c, d 3 = - r a + r c, d 4 = r a, Case 3 (S 1 an, S 1 bn, S 1 cn) = (a, b, c) (S 2 an, S 2 bn, S 2 cn) = (a, b, c + 1) (S 3 an, S 3 bn, S 3 cn) = (a + 1, b, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b + 1, c + 1) d 1 = 1 - r c, d 2 = - r a + r c, d 3 = r a - r b, d 4 = r b, Case 4 (S 1 an, S 1 bn, S 1 cn) = (a, b, c) (S 2 an, S 2 bn, S 2 cn) = (a, b + 1, c) (S 3 an, S 3 bn, S 3 cn) = (a + 1, b + 1, c) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b + 1, c + 1) d 1 = 1 - r b, d 2 = - r a + r b, d 3 = r a - r c, d 4 = r c, Case 5 (S 1 an, S 1 bn, S 1 cn) = (a, b, c) (S 2 an, S 2 bn, S 2 cn) = (a, b, c + 1) (S 3 an, S 3 bn, S 3 cn) = (a, b + 1, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b + 1, c + 1) d 1 = 1- r c, d 2 = - r b + r c, d 3 = - r a + r b, d 4 = r a, Case 6 (S 1 an, S 1 bn, S 1 cn) = (a, b, c) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b, c) (S 3 an, S 3 bn, S 3 cn) = (a + 1, b + 1, c) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b + 1, c + 1) d 1 = 1- r a, d 2 = r a - r b, d 3 = r b r c, d 4 = r c, 100

101 TABLE 4.II SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON THE TETRAHEDRON CASE USING SPACE DIVISION SD1 Tetrahedron State vectors sequence Duty cycles Case 1 (S 1 an, S 1 bn, S 1 cn) = (a, b, c + 1) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b, c + 1) (S 3 an, S 3 bn, S 3 cn) = (a, b + 1, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a, b, c) d 1 = -r a -r b +r c, d 2 =1-d 1 -d 3 -d 4, d 3 = r b, d 4 = 1-r c, Case 2 (S 1 an, S 1 bn, S 1 cn) = (a + 1, b, c) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b + 1, c) (S 3 an, S 3 bn, S 3 cn) = (a + 1, b, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a, b, c) d 1 = r a -r b -r c, d 2 = 1-d 1 -d 3 -d 4, d 3 = r c, d 4 = 1- r a, Case 3 (S 1 an, S 1 bn, S 1 cn) = (a + 1, b + 1, c + 1) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b + 1, c) (S 3 an, S 3 bn, S 3 cn) = (a + 1, b, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a, b + 1, c + 1) d 1 = r a +r b +r c -2, d 2 = 1-r c, d 3 = 1-d 1 -d 2 -d 4, d 4 = 1-r a, Case 4 (S 1 an, S 1 bn, S 1 cn) = (a, b + 1, c) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b + 1, c) (S 3 an, S 3 bn, S 3 cn) = (a, b + 1, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a, b, c) d 1 = -r a +r b -r c, d 2 = 1-d 1 -d 3 -d 4, d 3 = r c, d 4 = 1-r b, Case 5 (S 1 an, S 1 bn, S 1 cn) = (a + 1, b + 1, c) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b, c + 1) (S 3 an, S 3 bn, S 3 cn) = (a, b + 1, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a, b, c) d 1 = 0.5 (r a +r b -r c ), d 2 = 0.5 (r a -r b +r c ), d 3 = 1-d 1 -d 2 -d 4, d 4 =1-0.5 (r a +r b +r c ), 101

102 TABLE 4.III SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON THE TETRAHEDRON CASE USING SPACE DIVISION SD2 Tetrahedron State vectors sequence Duty cycles Case 6 (S 1 an, S 1 bn, S 1 cn) = (a + 1, b, c + 1) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b + 1, c + 1) (S 3 an, S 3 bn, S 3 cn) = (a, b, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b, c) d 1 = r a -r b +r c -1, d 2 =1-d 1 -d 3 -d 4, d 3 = 1-r a, d 4 = 1-r c, Case 7 (S 1 an, S 1 bn, S 1 cn) = (a, b, c) (S 2 an, S 2 bn, S 2 cn) = (a, b + 1, c) (S 3 an, S 3 bn, S 3 cn) = (a, b, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b, c) d 1 = 1-r a -r b -r c, d 2 = 1-d 1 -d 3 -d 4, d 3 = r c, d 4 = r a, Case 8 (S 1 an, S 1 bn, S 1 cn) = (a, b + 1, c + 1) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b + 1, c + 1) (S 3 an, S 3 bn, S 3 cn) = (a, b + 1, c) (S 4 an, S 4 bn, S 4 cn) = (a, b, c + 1) d 1 = -1-r a +r b +r c, d 2 = 1-d 1 -d 3 -d 4, d 3 = 1-r c, d 4 = 1-r b, Case 9 (S 1 an, S 1 bn, S 1 cn) = (a + 1, b + 1, c) (S 2 an, S 2 bn, S 2 cn) = (a + 1, b + 1, c + 1) (S 3 an, S 3 bn, S 3 cn) = (a, b + 1, c) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b, c) d 1 = -1+r a +r b -r c, d 2 = r c, d 3 = 1-r a, d 4 = 1-d 1 -d 2 -d 3, Case 10 (S 1 an, S 1 bn, S 1 cn) = (a + 1, b + 1, c + 1) (S 2 an, S 2 bn, S 2 cn) = (a, b + 1, c) (S 3 an, S 3 bn, S 3 cn) = (a, b, c + 1) (S 4 an, S 4 bn, S 4 cn) = (a + 1, b, c) d 1 =0.5(-1+r a +r b +r c ), d 2 =0.5(1-r a +r b -r c ), d 3 =0.5(1-r a -r b +r c ), d 4 =1-d 1 -d 2 -d 3, 102

103 In order to compare SD45 and SD1 space divisions, the distances between the reference vector and the four state vectors that compose the tetrahedron where the reference vector is pointing to can be determined. These distances are named x 1, x 2, x 3, and x 4. In Figure 4.28, the distances x i using SD45 and SD1 are shown. Figure Generation of the reference voltage using the four nearest state vectors using SD45 (a) and SD1 (b). The distances between the state vectors and the reference vector are different Depending on the used space division, the reference vector is generated using different state vectors. Mathematically, the reference vector is correctly generated using any space division but the distances x i change and consequently the ripple of the output signals also changes. The output current ripple is related to the value of the distances x i. If these distances decrease, it means that the reference vector is generated with nearer state vectors and therefore the instantaneous error due to each state vector is lower. A merit figure can be defined in order to show x i distances in each case and what is the best solution depending on the reference vector location. This merit figure is defined as: 103

104 F = x x x x where if > 1000 = 1000 for i= x x i i (4.5) In order to pick out what is the best sub-cube division depending on the reference vector location inside the two-level sub-cube, F functions for both space divisions are calculated (F SD45 and F SD1 ). Finally, it is defined the function F T as the difference of F SD1 and F SD45. F = F F (4.6) T SD1 SD 45 F T can be determined for all possible locations of the reference vector in the subcube. In the control regions where F T is lower than zero, SD45 appears as the better solution. On the other hand, in the control regions where F T is greater than zero, SD1 improves the ripple behaviour. In Figure 4.29, F T function is represented for several values of b coordinate in two-level sub-cube. It is clear that inside the central tetrahedron defined by SD1, SD45 improves F T. However, in the outer parts of this central tetrahedron, SD1 improves the F T function. So, if the reference vector is located into the central tetrahedron, the best solution is to use SD45 space division and if the reference vector is outside central tetrahedron, it is better to use SD1 space division. 104

105 Figure Merit figure F T for several b coordinate values between 0 and 1. If F T is positive or negative, the distances between the reference vector and the state vectors are smaller using SD1 or SD45 respectively Simulations have been carried out to show the SD1 performance. The simulated system is a four-leg four-wire three-level diode clamped converter connected to an RL load. The DC-Link voltage is equal to 1600 V, L=5 mh, R=22 Ω and the switching frequency is 5 khz. The reference is a pure sinusoidal waveform with modulation index equal to Simulation results using SD45 and SD1 are shown in Figure 4.30 and Figure 4.31 respectively. It is clear that undesired and unexpected ripple effects in the output phase currents using SD1 appear. 105

106 Figure Output phase currents using SD45 for a three-level 4L4W DCC considering VDC=1600V, L=5mH, R=22 Ω and the modulation index m= The reference voltage is a pure sinusoidal waveform and the switching frequency is 5 khz Figure Output phase currents using SD1 for a three-level 4L4W DCC considering VDC=1600V, L=5mH, R=22 Ω and the modulation index m= The reference voltage is a pure sinusoidal waveform and the switching frequency is 5 khz 106

107 Using SD1, the distortion in the output phase currents occur when the reference vector moves from a sub-cube (sub-cube 1) to an adjacent sub-cube (sub-cube 2). Adjacent tetrahedrons from both sub-cubes only have two common state vectors. In the transition between adjacent tetrahedrons, there is one not common state vector with non zero duty cycle that generates the reference vector. This is shown in Figure In the figure, the not common state vector between adjacent tetrahedrons in adjacent sub-cubes is emphasized using a circle. The contribution of this state vector to the output currents is completely different and undesired ripple effects appear. Figure Transition between adjacent sub-cubes using space division SD1. State vectors with non zero duty cycle create output current distortion 107

108 In order to avoid the presence of not common state vectors, adjacent sub-cubes in the total control region are divided using SD1 and SD2 alternately. Using this configuration in the control region, adjacent tetrahedrons from adjacent subcubes have three common state vectors and in the transition instant, the fourth state vector has zero duty cycle. So, the movement between adjacent sub-cubes is done avoiding the presence of state vectors with non negligible duty cycles. This space division is named SD12 and is represented in Figure Figure Adjacent sub-cubes in the total control region divided using SD1 and SD2 alternately (named SD12 space division) Considering the combination of the SD1 and SD2 control region division, the same simulations can be carried out. In Figure 4.34, simulation output phase currents results using SD12 space division are shown. It can be seen that the obtained results are very similar. 108

109 Figure Output phase currents using SD12 space division generating a pure sinusoidal reference for a three level four-leg four-wire diode clamped converter considering VDC=1600V, L=5mH, R=22Ω and the modulation index m= The reference voltage is a pure sinusoidal waveform and the switching frequency is 5 khz As the obtained phase current results are similar at first sight, total harmonic distortion (THD) values are calculated using SD45 and SD12. THD using SD45 and SD12 space division are represented in Figure 4.35 and Figure 4.36 respectively showing that both space divisions achieve similar THD contents. 109

110 Figure Obtained output phase current total harmonic distortion (% of fundamental) using SD45 space division Figure Obtained output phase current total harmonic distortion (% of fundamental) using SD12 space division 110

111 Three dimensional generalized space vector modulation algorithms are discussed in this work. Two new space divisions and its related multilevel modulation algorithms are shown. Finally, the combination of two different space divisions is used to avoid undesired output phase current ripple effects. A comparison between previous 3D modulation algorithm and the proposed algorithms is done. The presented modulation algorithms calculate the state vectors and the duty cycles without using angles, trigonometric functions or look-up tables. The computational cost of the proposed method is very low, is always the same and is independent of the number of levels of the converter. In general, the presented algorithms are useful in systems with or without neutral, unbalanced load, and harmonics generation Four-leg four-wire converters (4L4W) Converters connecting the neutral point of the load to a converter phase are named four-leg four-wire systems (4L4W systems) and they were presented in chapter 2. A 4L4W two-level conventional converter is shown in Figure Figure L4W two-level conventional converter 111

112 It can be seen that 4L4W multilevel converter state vectors space forms a dodecahedron in the 3D-space [67][68][71]. This dodecahedron can be decomposed into several sub-cubes, and each one can be divided in different tetrahedrons that generate the total volume of each sub-cube. The 3Ddodecaedron containing the state vectors which generate the reference vector in 4L4W three-level converter is shown in Figure As another example, a 4L4W five-level converter is illustrated in Figure Figure Generalized 3D state vectors space for 4L4W three-level converter 112

113 Figure Generalized 3D state vectors space for 4L4W five-level converter The search for the nearest state vectors in multilevel 4L4W converters can be solved using the same coordinates change that was proposed for 3L4W multilevel converters and shown in Figure Using the sub-cube coordinates, 4L4W multilevel modulation problem is reduced to a 3L4W two-level problem [72] and the same 3L4W two-level modulation algorithms presented before can be used. All the expressions proposed before can work equally in the 4L4W multilevel converter topology. 3D SVPWM algorithms has been successfully tested by simulation and using a laboratory prototype. The considered conditions are 55 Ω resistive load, 1.2 mh smoothing inductance, 10 khz switching frequency and 40V DC-Link voltage. The algorithms have been successfully implemented using Matlab (Simulink). The multilevel simulation results have been obtained using switching models formulated in terms of control functions and presented in chapter 3 of this thesis. 113

114 The experimental results have been obtained with a real prototype using a TMS320VC33 DSP microprocessor. In order to test the proposed technique an unbalanced voltage reference composed of a fundamental component with 20V amplitude, 20% of zero sequence and 20% inverse sequence has been used. Voltage references for each phase are represented in Figure Voltage references of each phase are illustrated in Figure 4.41.a, Figure 4.42.a and Figure 4.43.a. The simulation results are shown in Figure 4.41.b, Figure 4.42.b and Figure 4.43.b and the experimental results are shown in Figure 4.41.c, Figure 4.42.c and Figure 4.43.c. Figure Voltage reference for each phase composed of a fundamental component with 20V amplitude, 20% of zero sequence and 20% inverse sequence 114

115 Figure Voltage for phase a, composed of a fundamental component with 20V amplitude, 20% of zero sequence and 20% inverse sequence Figure Voltage for phase b, composed of a fundamental component with 20V amplitude, 20% of zero sequence and 20% inverse sequence 115

116 Figure Voltage for phase c, composed of a fundamental component with 20V amplitude, 20% of zero sequence and 20% inverse sequence Another reference vector containing a fundamental component with 40 3 V amplitude and 120% of the third harmonic has been proved for the sake of clarity. Voltage reference for each phase is illustrated in Figure The voltage reference, the simulated results and the experimental results of this experiment are shown in Figure Clearly, the voltage signal across the phase resistor follows the input reference signal. These results show the good performance of the proposed algorithm. 116

117 Figure Voltage reference composed of a fundamental component with 40 V amplitude and 120% of the third harmonic 3 Figure Voltage signals with 40 V amplitude and 120% of the third 3 harmonic 117

118 Chapter 5 Solving the Balancing of the Capacitors Voltage in Multilevel Converters 5.1 Introduction Multilevel converters present several advantages compared to classical two-level converters [5][6]. They improve the harmonic content of the output signals and they accept a power increase in the DC-link due to its voltage can be shared between more transistors. As disadvantages, the multilevel converters increase the control and the implementation complexity. Recently the control complexity has been reduced thanks to the use of new and powerful microprocessor systems [73]-[75]; hence the balance of the DC capacitors voltage is one of the most important drawbacks of this type of converter topologies. In this chapter, control strategies to carry out the balance the DC capacitors voltage for multilevel 118

119 converters are presented. These strategies use the well known technique based on choosing the correct redundant vector using Space Vector Modulation algorithms in order to reduce the voltage unbalance [77]-[89]. It is important to notice that the proposed methods are completely generalized and due to it, they are independent of the load and independent of the number of levels of the converter. Some simulation and experimental results show the obtained balance using the proposed techniques. If any unbalance in the DC capacitors voltage appears, the output phase voltages have distortion and the harmonic content of the output signals decreases its quality. In fact, if the switching control is not be made carefully and a control algorithm is not carried out, the problem immediately appears and the DC capacitors voltage will be unbalanced. 5.2 Quasi-solution of the voltage balancing problem Redundant vectors using SVPWM techniques can be used to achieve DC capacitors voltage balance [77]-[89]. These vectors have the same phase-toneutral output voltages but their effect in the DC capacitors voltage is completely different. This chapter shows that the balancing problem of the DC capacitors voltage in multilevel converters topologies can be solved using the redundant vectors. However, the increasing complexity with the number of levels makes very difficult to choose the best redundant vector to control the voltage unbalance. In fact, sometimes this choosing is impossible due to there are cases where all the possible redundant vectors do not decrease the unbalance. 119

120 It should be noticed that increasing the number of levels, the number of redundant vectors in multilevel state vectors space increases exponentially. In fact, the number of state vectors for N-level 3L3W DCC converter is N 3. The number of redundant vectors (NRV) for N-level 3L3W DCC can be determined using the expression (5.1). The evolution of the total number of state vectors and redundant vectors is shown in Figure 5.1. N 2 NRV = N + 6( in i) (5.1) i= 1 Figure 5.1. Number of redundant vectors depending on the number of levels in DCC topology 120

121 Depending on the multilevel converter topology, the DC capacitor voltages must take different values. For instance, in multilevel DCC topology, all DC-link capacitors must equally share the DC-link voltage [20]. Three-level DCC topology is represented in Figure 5.2 showing that capacitors C 1 and C 2 share the DC-Link voltage. For N-level DCC case, V Ci can be defined as the unbalance of the capacitor C i as follows: V = V Ci Ci VDC N 1 (5.2) Figure 5.2. Three-level DCC topology. DC-Link voltage is equally shared between capacitors C 1 and C 2 121

122 On the other hand, in multilevel FCC topology, each flying capacitor voltage value is different [26]. For instance, a four-cell conventional FCC using OFBCS flying capacitor voltages ratio is represented in Figure 5.3 showing the flying capacitor voltages values. For M-cell OFBCS FCC, V Ci can be defined as the unbalance of the flying capacitor C i as follows: ( M i) VCi = VCi VDC (5.3) M Figure 5.3. Four-cell FCC topology showing the different flying capacitors voltage values using OFBCS flying capacitor voltages ratio 122

123 High number of publications has been focused on the development of control strategies to solve the voltage unbalance for multilevel converters [77]-[91]. As it was said in chapter 4, depending on the multilevel converter topology, different redundant vectors appear in the converter state vectors space. Previous authors have proposed control algorithms based on choosing the best redundant vector to control the DC capacitors voltage [89]-[91]. In this thesis, generalized algorithms using the redundant vectors concept are presented for any number of levels in the converter. The proposed control algorithms are based on the calculation of the currents that flow through DC capacitors (i Si ) depending on instantaneous state vector applied to the multilevel converter. These algorithms could seem very complex at first sight but it will be shown that they are very fast and simple. All the calculations are completely generalized and they do not imply complex operations or look-up tables. Generalized expressions for N-level converters have been developed. An important contribution is the performance of a systematic method to study any multilevel converter topology to develop control algorithms for future converter topologies. 5.3 Voltage balancing problem depending on the multilevel converter topology The balancing control algorithms proposed in this thesis are based on the determination of the currents that flow through DC capacitors that can suffer the voltage unbalance. In general, these currents depend on the state vector applied to the converter. In next points, a deep study of the calculation of these currents depending on the converter topology is presented. The knowledge of the expressions of these currents and the capacitors voltage unbalance are the base of 123

124 the balancing control algorithms. In this thesis it is assumed that the DC-Link voltage is constant thanks to an external voltage source (controlled rectifier, external independent voltage source ). As it was said before it was defined V Ci as the unbalance of capacitor C i determined by the difference between the real capacitor voltage and the desired capacitor voltage (see expressions (5.2(5.3). Depending on the converter topology, the voltage unbalance expression is different. Using the signal criteria defined in Figure 5.4, the control strategy to achieve DC capacitors voltage balance can be easily developed. If current i Si sign and unbalance V Ci sign are not equal, the unbalance will decrease. So, the control algorithms should choose the redundant vector that fulfils this property. C i isi V Ci V DC + - Cj isj V Cj Figure 5.4. Signs criterion used in the control strategies 124

125 Sometimes the perfect redundant vector choosing to reduce the voltage unbalance is impossible due to there are cases where all the possible redundant vectors do not decrease the unbalance. Several balancing control algorithms were tested depending on the redundant vectors choosing criterion. The balancing control algorithms studied were: 1. To find the most unbalanced capacitor and to choose the redundant vector that puts the best current through this capacitor. 2. To find the highest current in absolute value and to choose the redundant vector that achieves the best capacitor configuration. 3. To find the redundant vector that achieves the best capacitor configuration to minimize the negative effects in the voltage balance. 4. To find the redundant vector that achieves the best capacitor configuration to maximize the positive effects in the voltage balance. 5. To find the redundant vector that achieves the best capacitor configuration taking into account the negative and the positive effects in the capacitors voltages. Studying these balancing control algorithms by simulations using Matlab/Simulink models presented in chapter 3 it can be concluded that: Controlling multilevel converters with algorithms number one and four do not reach good results. The system turns unstable. Controlling multilevel converters with the other balancing algorithms reaches good results achieving the stability but only under some conditions. Finally, the balancing control algorithm number five was chosen because it takes into account all the system and all the control variables. For N-level converters, the balancing control algorithm finds the best redundant vector in the simplest way. The algorithm chooses the state vectors that minimize the sum of the 125

126 products of V Ci and i Si with i=1,.,n-1. In this way, the control algorithm assures that the final chosen redundant vectors maximize, in average, the tendency to the voltage balance of all DC capacitors. In fact, this control method really implies a minimization of the electrical energy stored in the chain of DC capacitors [91]. The minimization of this parameter directly means the minimization of the averaged unbalance of DC capacitors. But in general, increasing the number of levels and considering N-level, it is not always possible to find a redundant vector that tends to equilibrate all the DC capacitors voltage. It is important to notice that all the necessary expressions to be applied in the control algorithms are very simple and they can be easily implemented in a microprocessor system being the control strategy computational cost very low. Besides, the control method is completely generalized and due to it, it is independent of the load type and it is independent of the number of levels of the converter Diode-Clamped Converter Topology Using this converter topology and assuming that SVPWM algorithm applies a specific state vector to the converter, the DC-link capacitors are divided in several blocks. Each block is composed by several capacitors in series. Considering that all capacitors have the same capacitance value C, they can be associated forming different capacitors C/k i where k i is the number of capacitors in series in each block. The sum of k i is the total number of DC-link capacitors that is equal to N-1 in an N-level DCC topology. This concept will be shown clearly in the next points. 126

127 m i= 1 4 for 3 wire converters ki = N 1 with m= 5 for 4 wire converters (5.4) It can be assumed that V DC is approximately constant due to the converter is usually connected to a device, e.g. a rectifier, that supports the total DC-link voltage. Supposing that total DC-link voltage is constant, it is a fact that there is a relation between the currents through the DC-link capacitors (i Si ). V DC = m i= 1 d C dt V Si (5.5) 0 dv C dt m S1 = = m i= 1 i= i ki i Si V Ci is the unbalance of capacitor C i and the expression was presented in expression (5.2). Using the signal criteria defined in Figure 5.4, the control strategy to achieve the balance of the DC-Link voltage can be easily developed. If the sign of the current i Si and the sign of V Ci are not equal, the unbalance will decrease. 127

128 N-level three-leg three-wire Diode-Clamped (3L3W DCC) Topology The control algorithm for the DC-Link capacitor voltages balancing needs to find out the currents that flow through those DC capacitors. As it was said before, k i is defined as the number of DC capacitors connected in series applying a specific state vector to the converter and therefore, it takes values between 0 and N-1 for N-level DCC. In N-level 3L3W DCC, each phase load is connected to some DC-Link point applying the state vector imposed by the SVPWM algorithm. These connections depending on the applied state vector can be represented in a very simple way considering ideal power switching devices and assuming that all capacitors have the same capacitance value. In N-level 3L3W DCC only two different cases must be studied to determine i Si currents for all possible redundant state vectors. Current i P3 is the phase current flowing through the phase connected to the highest level, i P1 is the phase current flowing through the phase connected to the lowest level and i P2 is the phase current flowing through the phase connected to a medium level. I. State vectors where k 2 >0, k 3 >0 and k 4 and k 1 can not be simultaneously zero This configuration is the generalized version of a redundant vector where the phases of the load are connected to different points of the DC-Link. In fact, if k 1 =0 and k 4 =0 simultaneously, the state vector is not redundant. This configuration is shown in Figure

129 Figure L-3W DCC with case 1 configuration (k 2 >0, k 3 >0 and k 4 and k 1 can not be simultaneously zero) Analyzing this case, i Si expressions can be determined as follows. V + V + V + V = V C4 C3 C2 C1 DC d C dt ki + ki = ki ki 4 S4 1 S1 2 S2 3 S3 ki 2 P2 + ( k2 + k3) ip3 is4 = is1 = is is = N 1 ( k2 + k3 + 1 N) ip3 + ki 2 P2 is3 = is ip3 = N 1 ( k + k + 1 N) ip + ( k + 1 Ni ) is2 = is + ip1 = N P2 (5.6) 129

130 II. State vectors where k 1 and k 4 are not simultaneously equal to zero and k 3 =0, k 2 >0 or k 2 =0, k 3 >0 Figure L-3W DCC with case 2 configuration (k 1 and k 4 are not simultaneously equal to zero and k 3 =0, k 2 >0 or k 2 =0, k 3 >0) Analyzing this case, i Si expressions can be determined as follows. V + V + V = V ki + ki = ki C4 C2 C1 DC 4 S4 1 S1 2 S2 ki 2 P 2 is4 = is1 = is is = N 1 ( k1 + k4) is2 = is ip2 = ip2 N 1 (5.7) 130

131 All the redundant state vectors can be studied changing the values of k i factors and recalculating i Si values. After determining the currents through the DC-link capacitors associated to each redundant state vector, the balancing control algorithm must choose carefully the best redundant state vector in order to equilibrate the DC-link capacitors voltage N-level four-leg four-wire Diode-Clamped (4L4W DCC) Topology As it was said before, it can be assumed that V DC is approximately constant due to the converter is usually connected to a device, e.g. a rectifier, that supports the total DC-link voltage. Supposing it, the relation between the currents through the DC-link capacitors (i Si ) can be rewritten. V = V + V + V + V + V DC C1 C2 C3 C4 C5 d C dt dv dv dv dv dv 0 = C + C + C + C + C dt dt dt dt dt 0 = ki + ki + ki + ki + ki C1 C2 C3 C4 C5 1 S1 2 S2 3 S3 4 S4 5 S5 (5.8) In order to generalize the study and to know the way to choose the best redundant vector to carry out the balance of the DC-link voltage, all the possibilities are studied. Several possible switching configurations appear depending on the position of the connection of the fourth leg. All the cases can be summarized in 131

132 Figure 5.7 (case 1), Figure 5.8 (case 2), Figure 5.9 (case 3) and Figure 5.10 (case 4). As it was said for 3L3W DCC case, current i P3 is the phase current flowing through the phase connected to the highest level, i P1 is the phase current flowing through the phase connected to the lowest level and i P2 is the phase current flowing through the phase connected to a medium level. Besides, i N is the current that flows through the phase connected to neutral point of the load (the fourth leg). 132

133 Figure 5.7. First case of possible switching state configuration of multilevel 4L4W DCC 133

134 Figure 5.8. Second case of possible switching state configuration of multilevel 4L4W DCC 134

135 Figure 5.9. Third case of possible switching state configuration of multilevel 4L4W DCC 135

136 Figure Fourth case of possible switching state configuration of multilevel 4L4W DCC 136

137 All the cases can be easily solved and i Si results can be summarized as follows. Case 1: 1 is1= [ ki 2 P1+ ( k2+ k3 ) ip2+ ( k2+ k3+ k4 ) ip3 ] N 1 1 is2 = [( N 1 k2 ) ip 1+ ( k1+ k4+ k5 ) ip2+ ( k1+ k5 ) ip3 ] N 1 1 is3 = [ ki 2 P1 ( k1+ k4+ k5 ) ip2 ( k1+ k5 ) ip3 ] N 1 1 is4 = [ ki 2 P1+ ( k2+ k3 ) ip2 ( k1+ k5 ) ip3 ] N 1 Case 2: 1 is1= [ ki 2 P1+ ki 3 P2+ ( k3+ k4) ip3] N 1 1 is2 = [( N 1 k2 ) ip 1+ ki 3 P2+ ( k3+ k4 ) ip3 ] N 1 1 is3 = [ ki 2 P1+ ( N 1 k3 ) ip2+ ( k1+ k2+ k5 ) ip3 ] N 1 1 is4 = [ ki 2 P1+ ki 3 P2 ( k1+ k2+ k5 ) ip3 ] N 1 Case 3: (5.9) 1 is 1= [ ( k2+ k3 ) ip 1 ki 3 P2+ ki 4 P3 ] N 1 1 is2 = [( k1+ k4+ k5 ) ip 1 ki 3 P2+ ki 4 P3 ] N 1 1 is3 = [( k1+ k4+ k5 ) ip 1+ ( N 1 k3 ) ip2+ ki 4 P3 ] N 1 1 is4 = [( k2+ k3 ) ip 1+ ki 3 P2+ ( N 1 k4 ) ip3 ] N 1 Case 4: 1 is1= [( k2+ k3+ k4 ) ip 1+ ( k3+ k4 ) ip2+ ki 4 P3 ] N 1 1 is2 = [( k1+ k5 ) ip 1 ( k3+ k4 ) ip2 ki 4 P3 ] N 1 1 is3 = [( k1+ k5 ) ip 1+ ( k1+ k2+ k5 ) ip2 ki 4 P3] N 1 1 is4 = [( k1+ k5 ) ip 1+ ( k1+ k2+ k5 ) ip2+ ( N 1 k4 ) ip3 ] N 1 137

138 It can be studied, for instance, the three-level case. In this case, several double and triple redundant state vectors appear. These redundant state vectors can be summarized in TABLE 5.I. All the possible redundant vectors can be classified in the four cases explained before. Using the expressions proposed in TABLE 5.I, i Si currents can be easily calculated depending on the selected redundant state vector. In the three-level case, there are only two DC-Link capacitors; hence i S1 and i S2 can be determined. It can be remembered that using the expression (5.8) it must be fulfilled the expression i S2 =-i S1. As it was presented in (5.2), V Ci in the three-level case is: VDC VCi = VCi (5.10) 2 Considering three-level 4L4W DCC, in all the possible cases, the current through capacitor C 1 (i S1 ) in the redundant state vectors has opposite signs. This result is very important because in three-level case, the control algorithm can always select the sense of currents flowing through DC-link capacitors C 1 and C 2 choosing the redundant vector that tends to equilibrate the DC-link voltage. 138

139 State vector Redundant vectors Case TABLE 5.I. Each redundant vector in 4L4W DCC can be studied using one of the four simplified cases presented in Figure 5.7, Figure 5.8, Figure 5.9 and Figure

140 Simulation experiments have been carried out considering three-level 4L4W DCC topology connected to an RL load composed by R = 22Ω, L = 5mH, f sw (switching frequency)=5khz, C 1 =C 2 =500µF and V DC (DC-Link voltage) =1600V. The reference waveform is a sinusoidal signal with modulation index m=0.99 and 80% third harmonic. The good performance of the control algorithm is shown in Figure 5.11 where the one DC-Link capacitor voltage and the output phase currents are shown.. Figure DC-Link Capacitor C 1 voltage and output phase currents showing the good performance of the balancing control algorithm for three-level 4L4W DCC 140

141 In order to show the good performance of the control algorithm, some simulation results with higher number of levels are shown. It can be considered the same experiment described in the three-level case (see Figure 5.11) but using a fivelevel converter and assuming that the modulation index is equal to An initial unbalance in the DC-link capacitors voltages is applied to show the unbalance dynamics using the control algorithm. Therefore the simulation experiment has been carried out considering five-level 4L4W DCC topology connected to an RL load composed by R=22Ω, L=5mH, f sw (switching frequency)=5 khz, C 1 =C 2 =500 µf and V DC (DC-Link voltage)=1600v. The reference waveform is a sinusoidal signal with modulation index m=0.56 and 80% third harmonic. Using five-level DCC four capacitors compose the DC-link and their desired voltages are V DC /4 that is 400 volts in this case. In this simulation, initially, V C1 =470v, V C2 =360v, V C3 =370v and V C4 =400v. In Figure 5.12 simulation results of the DC-link voltages are represented. Figure DC-link Capacitors voltage showing the good performance of the balancing control algorithm starting with a initial unbalance using a five-level 4L4W DCC 141

142 A 50KW real prototype three level 4L4W-DCC was developed in Norwegian University of Science and Technology (NTNU) in Trondheim (Norway) in order to test the proposed balancing control algorithm. The control hardware is composed by TMS320F2812 microprocessor system and virtex XCV400BG432 FPGA. The DSP is responsible for the control algorithm and the FPGA makes the switching of the transistors implementing the duty cycles making the system more versatile and efficient [92][93]. The total DC-Link capacitors value is C=3300µF. The prototype is shown in Figure Figure kw real prototype three-level 4L4W DCC developed in Norwegian University of Science and Technology (Trondheim, Norway) 142

143 Several experiments were carried out to test the converter and the 4L4W DCC balancing control algorithm. All the expressions presented before can be applied directly only doing the factor N (number of levels of the converter) equal to 3. In the experiments, the converter is connected to a three-phase RL load where R=23.5Ω and L=1.4mH. The total DC-Link voltage is 80 volts. It is assumed a sinusoidal reference voltage where the modulation index was equal to 1 and an 80% of third harmonic content. In Figure 5.14, phase to phase voltage and the voltage across the resistor (phase to neutral of the load voltage) is shown demonstrating that the 3D-SVPWM algorithm presented in [72] is carried out properly. But this figure does not include the DC-Link capacitors voltages measure. If this experiment is carried out without using the balancing control algorithm, the DC- Link capacitors voltages turn unstable because the 3D-SVPWM algorithm does not consider any special choosing between the redundant vectors in the switching sequence. This voltage unbalance is shown in Figure A detail of this experiment is shown in Figure The modulation is carried out correctly generating the reference signal but DC-Link capacitors voltages begin to be unbalanced immediately after starting the execution of the modulation algorithm. Figure 5.15 and Figure 5.16 clearly show the need to include a balancing control algorithm in the modulation algorithm. If the proposed balancing algorithm is used, the DC-Link capacitor voltages will be balanced while the reference voltage is still be correctly generated. The good performance includes situations where the DC-Link capacitors voltages are initially unbalanced. In Figure 5.17, it can be seen that an initial unbalance is applied to the converter and the modulation algorithm and the balancing control algorithm begin to be executed. The output voltages are generated while the voltages unbalance quickly begins to decrease. It can be seen that some distortion 143

144 appears in the initial output voltages due to the voltages unbalance present in the converter. The balancing control algorithm continues working all the time achieving the balance of DC-Link capacitors voltages. It is shown in Figure 5.18 and Figure After balancing the DC-Link voltages, the initial distortion in the output voltages have disappeared demonstrating that it is created by the DC-Link capacitors unbalance. It is shown in Figure The balancing control algorithm does not suppose any restriction in the load. In fact, it works with balance or unbalance loads because it is absolutely independent of the load. In order to test it, it was carried out the same experiment but using an unbalanced load using L=1.4mH and R=23.5 Ω in two phases and L=1.4mH and R=47Ω in the third phase. The experimental results were completely satisfactory achieving the voltages balance and generating the reference waveforms. Figure Experimental results considering modulation index equal to 1 and 80% of third harmonic content. Phase to phase voltage and the voltage across the resistor load 144

145 Figure Experimental results considering modulation index equal to 1 and 80% of third harmonic content. DC-Link capacitors voltages unbalance without using the balancing control algorithm Figure Experimental results considering modulation index equal to 1 and 80% of third harmonic content. Detail of DC-Link capacitor voltages unbalance without using the balancing control algorithm 145

146 Figure Experimental results considering modulation index equal to 1 and 80% of third harmonic content. DC-Link capacitor voltages balance using the balancing control algorithm starting from an unbalanced situation Figure Experimental results considering modulation index equal to 1 and 80% of third harmonic content. Good performance of the balancing control algorithm to balance of the DC-Link capacitors voltage starting from an unbalanced situation 146

147 Figure Experimental results considering modulation index equal to 1 and 80% of third harmonic content. Detail of DC-Link capacitor voltages balance using the balancing control algorithm starting from an unbalanced situation Figure Experimental results considering modulation index equal to 1 and 80% of third harmonic content. Permanent response of the balancing control algorithm achieving the balanced voltage situation 147

148 It is important to note that the balancing control algorithm is independent of the number of levels of the converter because the same equations are used for any number of levels. However, it is clear that increasing the number of levels, the number of redundant vectors increase and the number of calculations to make the best choosing increases. One of the most important contributions of this thesis is the proposal of this control algorithm. In fact, it is the first control algorithm to balance the DC-link capacitor voltages for 4L4W DCC. All possible redundant vectors are deeply studied showing all possible simplified converter models. The analytical expressions to determine the currents flowing through DC-link capacitors are presented. The balancing control algorithm uses these equations and finds the best redundant state vectors in order to minimize the voltage unbalance in average. It is important to note that the algorithm computational cost is really low and it is independent of the load type and independent of the number of levels of the converter. A 50KW real prototype of a 4L4W-DCC was built and experimental results showing the good performance of the proposed algorithm are presented N-level three-leg four-wire Diode-Clamped (3L4W DCC) Topology In 3L4W topologies, the neutral point of the load is connected to the middle point of the DC-Link bus. Simplified models for 3L4W topologies can be developed considering that a state vector is applied to the converter. In this way, each phase load is connected to a point of the DC-Link and the fourth wire is connected to the middle point of the DC-Link bus. All simplified models for 4L4W DCC can be used imposing that the neutral wire is connected to the middle point of DC- Link bus. So, for instance, Figure 5.7 can represent a N-level 3L4W DCC with k 1 148

149 equal to (N-1)/2. In the same way, Figure 5.8, Figure 5.9 and Figure 5.10 are valid with k 1 + k 2, k 1 + k 2 + k 3 and k 1 + k 2 + k 3 + k 4 equal to (N-1)/2 respectively. Therefore, the study of this topology is a particularization of the study of 4L4W DCC topology and the DC capacitor currents equations for 3L4W DCC topology are exactly the same as 3L4W DCC topology but applying the fourth wire restriction. Case 1: N 1 k1 = k2 + k3 + k4 + k5 = 2 Case 2: N 1 k1+ k2 = k3 + k4 + k5 = 2 Case 3: N 1 k1+ k2 + k3 = k4 + k5 = 2 Case 4: N 1 k1+ k2 + k3 + k4 = k5 = 2 (5.11) However, using 3L4W topologies redundant vectors do not appear due to the fact that the fourth wire can not change its connection point. So, the control algorithm can not choose the redundant vector to minimize the voltages unbalance. The SVPWM algorithm directly applies the state vectors and there is not any possibility to change them. 149

150 5.3.2 Flying-Capacitor Converter (FCC) Topology Flying Capacitor Converters (FCC) use several floating capacitors in each phase to achieve different output voltage levels as it was explained in chapter 2. Multilevel FCC is built connecting flying capacitor basic cells in series. In Figure 5.21, M-cell single phase FCC is presented. Figure (N-1)-cell single phase Flying Capacitor Converter In a single phase M-cell FCC there are only 2 M different switching configurations depending on binary S xi values and therefore all possible converter switching configurations can be defined using M bits. An easy way to calculate output phase voltages with respect to the middle point of the DC-link labelled as point 0 (V x0 ) using each single cell binary value (S xi ) is the following: M V V = ( S S S S ) V + ( S S ) 2 DC x0 xi x( i+ 1) xi x( i+ 1) xi x1 x1 (5.12) i= 1 150

151 Considering OFBCS voltage ratio the number of output voltage levels is the number of basic cells plus one. It can be defined phase x state (PS x ) as an integer value that shows the output voltage level in phase x. PS x equal to zero means that the minimum possible voltage is in the phase output. For N-level OFBCS FCC, the output phase voltage V x0 and the factor PS x can be easily determined by V x0 PS x = N 1 i= 1 S xi VDC V = PSx N 1 2 DC (5.13) In the three-level case, the obtained OFBCS FCC is shown in Figure Studying this case, the possible switching configurations are shown in TABLE 5.II. It can be seen that in the three level FCC, two different switching configurations obtain the same output phase voltage referred to 0. Figure Three-level FCC using OFBCS voltages ratio. 151

152 S X1 S X2 Phase x -0 voltage Phase x State ON ON V DC /2 2 ON OFF 0 1 OFF ON 0 1 OFF OFF -V DC /2 0 Redundant switching configurations TABLE 5.II. Switching configurations in three-level single phase OFBCS FCC If the number of levels of OFBCS FCC is increased, the switching configuration redundancy also increases. This property does not appear in Diode Clamped Converters (DCC) where there is only one possibility to impose an specific converter output phase state. In general, for N-level OFBCS FCC, the number of redundant switching configurations to obtain the phase state k (RPS k ) is a permutation with repetition of k elements in a group of N-1 elements. This redundancy increase is shown in Figure RPS k = P = kn, 1 k N 1 ( N 1! ) ( ) k! N 1 k! (5.14) The proposed balancing control algorithm for OFBCS FCC is based on the existence of redundant switching configurations. Considering other voltage ratios presented in [28], this property does not appear and there is not any redundant switching configuration to obtain the same output voltage in the FCC. So, if some of these voltage ratios are chosen, the balancing control algorithm will be less efficient in order to solve the balancing voltage problem. So, the proposed balancing control algorithm assumes that OFBCS voltage ratio is used. 152

153 Figure Switching configurations redundancy for each OFBCS FCC phase state depending on the number of levels It can be assumed that SVPWM algorithm calculates the switching sequence to generate a specific reference signal. This work uses the SVPWM algorithm presented in [66] due to its simplicity and low computational cost. On the other hand, in multilevel OFBCS FCC each output phase state can be obtained in general by different ways due to the switching configuration redundancy. So, for multilevel OFBCS FCC there are two different redundancies: Redundancy in the state vectors space: considering the complete threephase system, different state vectors achieve the same output phase to neutral voltages. This redundancy appears in other topologies as DCC topology. 153

154 Redundancy in the switching configurations in each phase: Different switching configurations in each phase achieve the same output phase-0 voltage. Therefore, both redundancies can be taken into account to develop a balancing control algorithm. As it was shown for multilevel DCC topology, the balancing control algorithm chooses the redundant state vectors that minimize the voltage errors in average as much as possible but for OFBCS FCC, the switching configurations redundancy introduces new freedom degrees in the switching sequence determination. In order to present the N-level OFBCS FCC balancing control algorithm, it is necessary to use the FCxi factor definition presented in (3.15). Using this definition, the flying capacitor currents expressions can be easily determined using (3.16). On the other hand, in the multilevel OFBCS FCC topology, each operation flying capacitor voltage is different. So, the voltage error Vxi can be defined as the measured voltage minus the desired voltage of the flying capacitor Cxi using (5.3). The SVPWM algorithm determines the switching sequence that must be applied to the converter. The balancing control algorithm studies these state vectors and applies the redundancy properties to minimize and compensate the voltage errors in the floating capacitors. The control algorithm studies all the state vectors of the switching sequence one by one following the flow diagram shown in Figure Each redundant state vector in the switching sequence is studied considering each phase separately because each phase state can be achieved by several redundant switching configurations. The balancing control algorithm considers each possibility and finally, chooses the best switching configuration to balance the flying capacitors voltage minimizing the sum of the products of the currents that flow through to the flying capacitors and their unbalances. This sum is defined as G and it is related with the energy in the system [91]. 154

155 M 1 Sxi i= 1 G= i V (5.15) xi At this point, the balancing control algorithm knows the best switching configuration in each phase of the converter supposing an specific state vector. So, the control algorithm must repeat this step using all possible redundant state vectors. Figure Balancing control algorithm flow diagram. Each state vector in the switching sequence is studied applying the best redundant state vector Finally, the balancing control algorithm chooses the best redundant state vector with the best switching configuration. So, the final election determines the state vector in the converter and the switching configuration in each phase of the converter that minimizes G factor. 155

156 An example with the three-level OFBCS FCC is shown. As it was seen in TABLE 5.II, this topology presents two possible switching configurations in each phase to obtain the phase state 1. In the example, it can be considered that the SVPWM algorithm determines the switching sequence and one of the state vectors is equal to {101}. In the 2D state vectors space this state vector presents the redundant state vector {212}. The flying capacitor voltages are unbalanced and in general, they are equal to: VDC V,,, x1 = + x1 with x= abc (5.16) 2 A. Switching Redundant Configurations Considering the state vector {101}, the balancing control algorithm studies the switching configuration for each phase separately. So, it considers phase a with phase state equal to 1. This phase state can be achieved by two different switching configurations (configurations 1 and 2 in TABLE 5.II). So, the balancing control algorithm calculates G factor for phase a using configuration 1 (G a1 ) and configuration 2 (G a2 ). Finally, the control algorithm determines the configuration that minimizes the factor G. {, } G min G G = (5.17) opt_ a1 a1 a2 At this point, the control algorithm knows the best switching configuration in phase a assuming phase a state equal to 1. In the same way, the control algorithm can determine the best switching configuration in phase b supposing the phase state equal to 0 and in phase c supposing the phase state equal to 1. It can be noticed that phase state equal to 0 has not switching redundancy and there is only one possible switching configuration to obtain that phase state. 156

157 G = G + G + G (5.18) opt1 opt_ a1 opt_ b1 opt_ c1 B. State Vectors Redundancy The balancing control algorithm knows in this moment the best switching configuration in all the phases supposing the state vector {101}. So, all the calculations must be repeated considering its redundant state vector {212} and factor G opt2 can be calculated. Finally, the balancing control algorithm must choose the best state vector and the best switching configuration in each phase that minimize the G factor. { 1, 2} G = min G G (5.19) opt opt opt The proposed balancing control algorithm is completely generalized. In fact, it is independent of the load type and the balance control algorithm uses very simple expressions with very low computational cost. The good performance of the control algorithm is demonstrated by simulations. The OFBCS FCC simulation model has been developed using MatLab/Simulink and it was presented in chapter 3. In the simulations, a three-level OFBCS FCC inverter is connected to an RL load. The values for the experiments are R=22Ω, L=3.5mH, C=2200µF. The reference signal is a pure sinusoidal waveform and the total DC-Link voltage is 700 volts. The switching frequency is 10 khz. The modulation index m is equal to In Figure 5.25, the flying capacitors C x1 balance for each phase is shown. The control algorithm achieves the voltages balance maintaining the ripple below 20 volts peak-to-peak. In Figure 5.26, the phase currents for this experiment are represented showing the low distortion of the output currents. 157

158 Figure Three-level flying capacitor C x1 voltages Figure Phase currents using a three-level OFBCS FCC 158

159 Summarizing, a new and generalized balancing control algorithm for multilevel OFBCS FCC has been presented. This algorithm uses very simple and efficient Space Vector Modulation strategy and it is based on the choosing of the best switching configuration studying the possible redundant vectors in the switching sequence. The algorithm is completely generalized, any number of levels can be studied and it is independent of the load. Simulation results are presented in order to show the good performance of the control algorithm. 5.4 Controllability limits In literature, previous works have demonstrated that multilevel DCC have no possibilities to balance the DC-link with a high number of levels under all the working operation conditions [84][88][90]. In fact, some authors have presented the analytical expressions for the operation limits of multilevel 3L3W DCC [91]. These limits depend on the modulation index of the reference signal and the phase load angle. In Figure 5.27, a simulation considering a five-level 3L3W DCC with C 1 =C 2 =C 3 =C 4 =C=4mF and DC-link voltage equal to 700 volts and connected to R=22Ω and L=15mH is presented. The reference voltage is defined as a 50 Hz sinusoidal waveform initially with modulation index equal to 50%. Assuming these conditions, the system is stable. But if the modulation index is increased to an 80%, it can be seen that the DC-Link capacitor voltages are not controlled and turn unstable. In [91][94], voltage balancing limits for 3L3W DCC are presented showing a figure where the limits for N-level 3L3W-DCC are depicted (see Figure 5.28). 159

160 Figure DC-link Capacitor voltages working in unstable conditions. Figure DC-link capacitor voltages controllability limits for N-level 3L3W DCC depending on the modulation index and the phase angle 160

161 Using the simulation model presented in chapter 3, controllability limits for OFBCS-FCC topology were deeply studied carrying out simulations for all modulation indexes and load phase angles values. So, a voltage balance control comparison between DCC and OFBCS-FCC topologies can be done. In this comparison, clearly OFBCS-FCC topology improves DCC behaviour because the stable control region is greater. However, there is still an unstable control region in OFBCS-FCC topology when the phase load angle is lower than 60 degrees. The heuristic results for this study are shown in Figure This result is logical and it was expected due to the fact that OFBCS-FCC topology presents switching redundant configurations and therefore has more possibilities to use the redundant vectors in order to balance the capacitors voltages than other multilevel converter topologies. Figure DC-link Capacitors voltage limits comparison between 3-level 3L3W OFBCS-FCC and N-level 3L3W DCC 161

162 If 4L4W multilevel converter topologies are considered, voltage balancing controllability limits also appears but in this case, the representation of the limits should be three dimensional. A qualitative representation of the possible limit of the DC-Link balancing algorithm is shown in Figure 5.30 [95]. Figure DC-link Capacitors voltage limits for 4L4W multilevel converters Anyway, these controllability limits only show the control region using the redundant vectors in SVPWM techniques. External control loops can be applied trying to make bigger the region under control [96] and control for back-to-back converters can be studied [97][98]. Besides, other optimization algorithms can be 162